CLA40P1200FC
Phase leg
High Efficiency Thyristor
2 4 31 5
Part number
CLA40P1200FC
Backside: isolated
TAV
T
V V1,19
RRM
40
1200
=
V=V
I=A
2x
Features / Advantages: Applications: Package:
● Thyristor for line frequency
● Planar passivated chip
● Long-term stability
● Line rectifying 50/60 Hz
● Softstart AC motor control
● DC Motor control
● Power converter
● AC power control
● Lighting and temperature control
i4-Pac
● Industry convenient outline
● RoHS compliant
● Epoxy meets UL 94V-0
● Soldering pins for PCB mounting
● Backside: DCB ceramic
● Reduced weight
● Advanced power cycling
● Isolation Voltage: V~
3000
The data contained in this product data sheet is exclusively intended for technically trained staff. The user will have to evaluate the suitability of the product for the intended application and
the completeness of the product data with respect to his application. The specifications of our components may not be considered as an assurance of component characteristics. The
information in the valid application- and assembly notes must be considered. Should you require product information in excess of the data given in this product data sheet or which concerns
the specific application of your product, please contact the sales office, which is responsible for you.
Due to technical requirements our product may contain dangerous substances. For information on the types in question please contact the sales office, which is responsible for you.
Should you intend to use the product in aviation, in health or live endangering or life support applications, please notify. For any such application we urgently recommend
- to perform joint risk and quality assessments;
- the conclusion of quality agreements;
- to establish joint measures of an ongoing product survey, and that we may make delivery dependent on the realization of any such measures.
Terms Conditions of usage:
IXYS reserves the right to change limits, conditions and dimensions. 20150827cData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA40P1200FC
V = V
kA²s
kA²s
kA²s
kA²s
Symbol
Definition
Ratings
typ.
max.
I
V
IA
V
T
1,25
R0,8 K/W
min.
40
VV
50T = 25°C
VJ
T = °C
VJ
mA4V = V
T = 25°C
VJ
I = A
T
V
T = °C
C
95
P
tot
150 WT = 25°C
C
40
1200
forward voltage drop
total power dissipation
Conditions
1,49
T = 25°C
VJ
125
V
T0
V0,86T = °C
VJ
150
r
T
7,9 mΩ
V1,19T = °C
VJ
I = A
T
V
40
1,50
I = A80
I = A80
threshold voltage
slope resistance for power loss calculation only
µA
125
VV1200T = 25°C
VJ
IA63
P
GM
Wt = 30 µs 10
max. gate power dissipation
P
T = °C
C
150
Wt = 5
P
P
GAV
W0,5
average gate power dissipation
C
J
25
junction capacitance
V = V400 T = 25°Cf = 1 MHz
RVJ
pF
I
TSM
t = 10 ms; (50 Hz), sine T = 45°C
VJ
max. forward surge current
T = °C
VJ
150
I²t T = 45°C
value for fusing
T = °C150
V = 0 V
R
V = 0 V
R
V = 0 V
V = 0 V
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
t = 10 ms; (50 Hz), sine
t = 8,3 ms; (60 Hz), sine
VJ
R
VJ
R
thJC
thermal resistance junction to case
T = °C
VJ
150
650
700
1,54
1,48
A
A
A
A
555
595
2,12
2,04
1200
300 µs
RMS forward current
T(RMS)
TAV
180° sine
average forward current
(di/dt)
cr
A/µs
150repetitive, I =T
VJ
= 150 °C; f = 50 Hz
critical rate of rise of current
V
GT
gate trigger voltage
V = 6 V T = °C25
(dv/dt) T = 150°C
critical rate of rise of voltage
A/µs500
V/µs
t = µs;
I A; V = ⅔ V
R = ∞; method 1 (linear voltage rise)
VJ
DVJ
120 A
T
P
G
= 0,3
di /dt A/µs;
G
=0,3
DRM
cr
V = ⅔ V
DRM
GK
1000
1,5 V
T = °C-40
VJ
I
GT
gate trigger current
V = 6 V T = °C25
DVJ
50 mA
T = °C-40
VJ
1,6 V
80 mA
V
GD
gate non-trigger voltage
T = °C
VJ
0,2 V
I
GD
gate non-trigger current
3 mA
V = ⅔ V
D DRM
150
latching current
T = °C
VJ
125 mA
I
L
25t µs
p
=10
I A;
G
= 0,3 di /dt A/µs
G
= 0,3
holding current
T = °C
VJ
100 mA
I
H
25V = 6 V
D
R = ∞
GK
gate controlled delay time
T = °C
VJ
2 µs
t
gd
25
I A;
G
= 0,3 di /dt A/µs
G
= 0,3
V = ½ V
D DRM
turn-off time
T = °C
VJ
200 µs
t
q
di/dt = A/µs10 dv/dt = V/µs20
V =
R
100 V; I A;
T
= 40 V = ⅔ V
DRM
tµs
p
= 200
non-repet., I = 40 A
T
125
R
thCH
thermal resistance case to heatsink
K/W
Thyristor
1300
RRM/DRM
RSM/DSM
max. non-repetitive reverse/forward blocking voltage
max. repetitive reverse/forward blocking voltage
R/D
reverse current, drain current
T
T
R/D
R/D
200
0,20
IXYS reserves the right to change limits, conditions and dimensions. 20150827cData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA40P1200FC
Ratings
odu
c
t
M
a
rk
in
g
Date Code
Part No.
Logo
UL listed
IXYS
Assembly
Code
Assembly
Line
ISOPLUS®
XXXXXXXXX
®
abcdZyyww
C
L
A
40
P
1200
FC
Part description
Thyristor (SCR)
High Efficiency Thyristor
(up to 1200V)
Phase leg
i4-Pac (5)
=
=
=
Current Rating [A]
Reverse Voltage [V]
=
=
=
=
Package
T
op
°C
T
VJ
°C150
virtual junction temperature
-40
Weight g9
Symbol
Definition
typ.
max.
min.
Conditions
operation temperature
F
C
N120
mounting force with clip
20
VV
t = 1 second
V
t = 1 minute
isolation voltage
mm
mm
1,7
5,1
d
Spp/App
creepage distance on surface | striking distance through air
d
Spb/Apb
terminal to backside
I
RMS
RMS current
70 A
per terminal
125-40
terminal to terminal
i4-Pac
Delivery Mode Quantity Code No.Ordering Number Marking on ProductOrdering
50/60 Hz, RMS; I ≤ 1 mA
ISOL
CLA40P1200FC 510210Tube 25CLA40P1200FCStandard
3000
ISOL
T
stg
°C150
storage temperature
-40
2500
threshold voltage
V0,86
mΩ
V
0 max
R
0 max
slope resistance *
5,4
Equivalent Circuits for Simulation
T =
VJ
I
V
0
R
0
Thyristor
150 °C
* on die level
IXYS reserves the right to change limits, conditions and dimensions. 20150827cData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA40P1200FC
b4
4x e
E
W
A
A2
A1
c4x b2
5x b
E1
D1
D2
L1
L
D
R
Q
1 2 53 4
D3
D
i
e
kon
v
e
x
e
F
o
r
m
des
S
ubs
t
r
a
t
es
i
s
t t
y
p
.
<
0
.
05
mm
übe
r
der Kunststoffoberfläche der Bauteilunterseite
The convexbow of substrate is typ. < 0.05 mm over plastic
surface level ofdevice bottom side
min max min max
A 4.83 5.21 0.190 0.205
A1 2.59 3.00 0.102 0.118
A2 1.17 2.16 0.046 0.085
b 1.14 1.40 0.045 0.055
b2 1.47 1.73 0.058 0.068
b4 2.54 2.79 0.100 0.110
c 0.51 0.74 0.020 0.029
D 20.80 21.34 0.819 0.840
D1 14.99 15.75 0.590 0.620
D2 1.65 2.03 0.065 0.080
D3 20.30 20.70 0.799 0.815
E 19.56 20.29 0.770 0.799
E1 16.76 17.53 0.660 0.690
e 3.81 BSC 0.150 BSC
L 19.81 21.34 0.780 0.840
L1 2.11 2.59 0.083 0.102
Q 5.33 6.20 0.210 0.244
R2.54 4.57 0.100 0.180
W-0.10 -0.004
Di
m.
Millimeter Inches
2 4 31 5
Outlines i4-Pac
IXYS reserves the right to change limits, conditions and dimensions. 20150827cData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved
CLA40P1200FC
0 40 80 120 160
0
10
20
30
40
50
60
70
80
10 100 1000
1
10
100
1000
0,01 0,1 1
100
200
300
400
500
6
0
0
0,0 0,5 1,0 1,5 2,0 2,5
0
30
60
90
120
1
50
1 10 100 1000 10000
0,0
0,2
0,4
0,6
0,8
I
T
[A]
t [s]
V
T
[V]
2 3 4 5 6 7 8 9 011
100
1000
10
0
00
I
2
t
[A
2
s]
t [ms]
I
TSM
[A]
T
VJ
= 25°C
T
VJ
= 125°C
T
VJ
= 45°C
50 Hz, 80% V
RRM
T
VJ
= 125°C
T
VJ
= 45°C
V
R
= 0 V
V
G
[V]
I
G
[mA]
I
T(AV)M
[A]
T
case
[°C]
Z
thJC
[K/W]
t [ms]
Fig. 1 Forward characteristics Fig. 2 Surge overload current
I
TSM
: crest value, t: duration
Fig. 3 I
2
t versus time (1-10 s)
Fig. 4 Gate voltage & gate current Fig. 6 Max. forward current at
case temperature
Fig. 7 Transient thermal impedance junction to case
t
gd
[µs]
I
G
[mA]
lim.
typ.
Fig. 5 Gate controlled delay time t
gd
0 10 20 30 40 50
0
20
40
60
I
T(AV)
[A]
P
(AV)
[W]
Fig. 7a Power dissipation versus direct output current
Fig. 7b and ambient temperature
0 50 100 150
T
amb
[°C]
T
VJ
= 125°C
R
thHA
0.6
0.8
1.0
2.0
4.0
8.0
dc =
1
0.5
0.4
0.33
0.17
0.08
dc =
1
0.5
0.4
0.33
0.17
0.08
T
VJ
= 125°C
1 10 100 1000 10000
0,1
1
10
4: P
GAV
= 0.5 W
5: P
GM
= 1 W
6: P
GM
= 10 W
1: I
GD
, T
VJ
= 150°C
2: I
GT
, T
VJ
= 25°C
3: I
GT
, T
VJ
= -40°C
1
23
45
6
i R
thi
(K/W) t
i
(s)
1 0.01 0.0004
2 005 0.009
3 0.17 0.014
4 0.36 0.05
5 0.21 0.36
Thyristor
IXYS reserves the right to change limits, conditions and dimensions. 20150827cData according to IEC 60747and per semiconductor unless otherwise specified
© 2015 IXYS all rights reserved