93LC56CX-I/PG - Microchip Technology, Inc.

93AA56A/B/C, 93LC56A/B/C,

93C56A/B/C

Device Selection Table

Features:

• Low-power CMOS technology

• ORG pin to select word size for ‘56C’ version

• 256 x 8-bit organization ‘A’ ver. devices (no ORG)

• 128 x 16-bit organization ‘B’ ver. devices (no

ORG)

• Self-timed erase/write cycles (including

auto-erase)

• Automatic ERAL before WRAL

• Power-on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device Status signal (R ead y/Bu sy )

• Seque nti al read function

• 1,000,000 E/W cycles

• Data retention > 200 y ears

• Temperature ranges supported:

Pin Function Table

Description:

The Microchip Technology Inc. 93XX56A/B/C devices

are 2K bit low-voltage serial Electrically Erasable

PROMs (EEPROM). Word-selectable devices such as

the 93AA56C, 93LC56C or 93C56C are dependent

upon external logic levels driving the ORG pin to set

word size. For dedicated 8-bit communication, the

93XX56A devices are available, while the 93XX56B

devices provide dedicated 16-bit communication.

Advanced CMOS technology makes these devices

ideal for low-power, nonvolatile memory applications.

The entire 93XX Series is available in standard

packages including 8-lead PDIP and SOIC, and

advanced packaging including 8-lead MSOP, 6-lead

SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. Pb-free

(Pure Matte Sn) finish is available.

Part Number VCC Range ORG Pin Word Size Temp Ranges Packages

93AA56A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT, MC

93AA56B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT, MC

93LC56A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC

93LC56B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC

93C56A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC

93C56B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC

93AA56C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST, MS, MC

93LC56C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS, MC

93C56C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS, MC

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

Name Function

CS Chip Select

CLK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

VSS Ground

NC No interna l conn ec tio n

ORG Memory Configuration

VCC Power Supply

2K Micr owire Compatible Serial EEPROM

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

Package Types (not to scale)

CLK

ORG

PDIP/SOIC

(P, SN)

CLK DI

NC ORG*

ROTATED SOIC

(ex: 93LC46BX)

TSSOP/MSOP

CLK

ORG*

(ST, MS) SOT-23

CLK

(OT)

* ORG pin is NC on A/B devices

DFN

CLK

ORG*

VSS

VCC

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins......................................................................................................................................................≥ 4kV

TABLE 1-1: DC CHARACTERISTICS

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stress rating only and funct ional operati on of th e dev ice at those or any other c ondit ions a bove those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

All parameters apply over the specified

ranges unless otherwise noted. Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No. Symbol Parameter Min Typ Max Units Conditions

D1 VIH1

VIH2High-level input voltage 2.0

0.7 VCC —

—VCC +1

VCC +1 V

VVCC ≥ 2.7V

VCC < 2.7V

D2 VIL1

VIL2Low-level input voltage -0.3

-0.3 —

—0.8

0.2 VCC V

VVCC ≥ 2.7V

VCC < 2.7V

D3 Vol1

Vol2 Low-level output voltage —

——

—0.4

0.2 V

VIOL = 2.1 mA, VCC = 4.5V

IOL = 100 μA, VCC = 2.5V

D4 VOH1

VOH2High-level output voltage 2.4

VCC - 0.2 —

——

—V

VIOH = -400 μA, VCC = 4.5V

IOH = -100 μA, VCC = 2.5V

D5 ILI Input leakage current — — ±1 μAVIN = VSS or VCC

D6 ILO Output leakage current — — ±1 μAVOUT = VSS or VCC

D7 CIN,

COUT Pin capacitance (all inputs/

outputs) ——7pFVIN/VOUT = 0V (Note 1)

TA = 25°C, FCLK = 1 MHz

D8 ICC write Write current —

——

500 2

—mA

μAFCLK = 3 MHz, V c c = 5. 5V

FCLK = 2 MHz, Vcc = 2.5V

D9 ICC read Read current —

—

100

500

—

μA

FCLK = 3 MHz, VCC = 5.5V

FCLK = 2 MHz, VCC = 3.0V

FCLK = 2 MHz, VCC = 2.5V

D10 ICCS Standby current —

——

—1

5μA

μAI – Temp

E – Temp

CLK = CS = 0V

ORG = DI = VSS or VCC

(Note 2) (Note 3)

D11 VPOR VCC voltage detect —

—

1.5

3.8

—

93AA56A/B/C, 93LC56A/B/C

(Note 1)

93C56A/B/C

Note 1: This parameter is periodically sampled and not 100% tested.

2: ORG pin not available on ‘A’ or ‘B’ versions.

3: Ready/Busy status must be cleared from DO, see Section 3.4 "Data Out (DO)".

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

TABLE 1-2: AC CHARACTERISTICS

All parameters apply ov er the specified

ranges unless otherwise noted. Industrial (I): TA = -40°C to +85°C, VCC = +1.8V TO +5.5V

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V

Param.

No. Symbol Parameter Min Max Units Conditions

A1 FCLK Clock frequency — 3

MHz

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A2 TCKH Clock high time 200

250

450

—ns

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A3 TCKL Clock low time 100

200

450

—ns

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A4 TCSS Chip Sele ct setup time 50

100

250

—ns

4.5V ≤ VCC < 5.5V

2.5V ≤ VCC < 4.5V

1.8V ≤ VCC < 2.5V

A5 TCSH Chip Sele ct hold time 0 — ns 1.8V ≤ VCC < 5.5V

A6 TCSL Chip Sele ct low tim e 250 — ns 1.8V ≤ VCC < 5.5V

A7 TDIS Data input setup time 50

100

250

—ns

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A8 TDIH Data input hold time 50

100

250

—ns

4.5V ≤ VCC < 5.5V, 93XX56C only

2.5V ≤ VCC < 5.5V

1.8V ≤ VCC < 2.5V

A9 TPD Data output delay time — 200

250

400

4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ VCC < 4.5V, CL = 100 pF

1.8V ≤ VCC < 2.5V, CL = 100 pF

A10 TCZ Data output disable time — 100

200 ns

ns 4.5V ≤ VCC < 5.5V, (Note 1)

1.8V ≤ VCC < 4.5V, (Note 1)

A11 TSV Status valid time — 200

300

500

4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ VCC < 4.5V, CL = 100 pF

1.8V ≤ VCC < 2.5V, CL = 100 pF

A12 TWC P rogram cycle t ime — 6 ms Erase/Write mode (AA and LC

versions)

A13 TWC — 2 ms Erase/Write mode

(93C versions)

A14 TEC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V

A15 TWL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V

A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This application is not tested but ensured by characterization. For endurance estimates in a specific

applic ation, ple ase cons ult the Tot al Endura nce™ Model which may be obt ained from Microchi p’s w eb site

at www.microchip.com.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

FIGU RE 1-1 : SYN CH R ONO US DA TA TIMI NG

TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX56B OR 93XX56C WITH ORG = 1)

TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX56A OR 93XX56C WITH ORG = 0)

Instruct ion SB Opcode A dd ress Data In Dat a Ou t R eq. C LK C yc les

ERASE 1 11 X A6A5A4A3A2A1A0 — (RDY/BSY)11

ERAL 1 00 10XXXXXX — (RDY/BSY)11

EWDS 1 00 00XXXXXX —High-Z 11

EWEN 1 00 11XXXXXX —High-Z 11

READ 1 10 X A6 A5 A4 A 3 A2 A1 A0 — D15 – D0 27

WRITE 1 01 X A6A5A4A3A2A1A0 D15 – D0 (RDY/BSY

)27

WRAL 1 00 01XXXXXXD15 – D0 (RDY/BSY)27

Instruction SB Opcode Address Data In Data Out Req. CLK

Cycles

ERASE 1 11 XA7A6A5A4A3A2A1A0 — (RDY/BSY

)12

ERAL 1 00 10XXXXXXX — (RDY/BSY)12

EWDS 1 00 00XXXXXXX —High-Z 12

EWEN 1 00 11XXXXXXX —High-Z 12

READ 1 10 XA7A6A5A4A3A2A1A0 — D7 – D0 20

WRITE 1 01 XA7A6A5A4A3A2A1A0 D7 – D0 (RDY/BSY

)20

WRAL 1 00 01XXXXXXX D7 – D0 (RDY/BSY)20

CS VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

CLK

(Read)

(Program)

TCSS

TDIS

TCKH TCKL

TDIH

TPD

TCSH

TPD

TCZ

Status Valid

TSV

TCZ

Note: TSV is relative to CS.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.0 FUNCTIONAL DESCRIPTION

When the ORG pin (93XX56C) pin is connected to

VCC, the (x16) organization is selected. When it is

connected to ground, the (x8) organization is selected.

Instr uct ion s, a ddresses an d w rite da ta are cl oc ke d in to

the DI pin on the risi ng edge of the clock (CLK). The DO

pin is normally he ld in a High-Z state exce pt when read-

ing data from th e de vi ce, or when che ck in g the Re ady /

Busy status during a programming operation. The

Ready/Busy status can be verified during an Erase/

Wr ite operat ion by pol ling the DO pin; DO lo w indicate s

that programming is still in progress, while DO high

indicates the device is ready. DO will enter the High-Z

state on the falling edge of CS.

2.1 START Condition

The Start bit is detected by the device if CS and DI are

both high with respect to the positive edge of CLK for

the first time.

Before a Start condition is detected, CS, CLK and DI

may change in any combination (except to that of a

Start condition), without resulting in any device

operation (Read, Write, Erase, EWEN, EWDS, ERAL

or WRAL). As soon as CS is high, the device is no

longer in Standby mode.

An instruction following a Start condition will only be

execut ed if the requi r ed op co de, address and data bits

for any particular instruction are clocked in.

2.2 Data In/Data Out (DI/DO)

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero”

that precedes the read operation, if A0 is a logic high

level. Under such a condition the voltage level seen at

Dat a Out is undefined a nd will dep end upon the relativ e

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin. In order to

limit this current, a resistor should be connected

between DI and DO.

2.3 Data Protection

All modes of operation ar e inhibited when VCC is below

a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices

or 3.8V fo r ‘93C’ devices.

The EWEN and EWDS commands give additional

protection against accidentally programming during

normal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before the initial ERASE or WRITE instruction

can be execu ted .

Block Diagram

Note: When prepari ng to tran sm it an i ns truc tion,

either the CLK or DI signal levels must be

at a logic low as CS is toggled active high.

Note: For added protection, an EWDS command

should be performed after every write

operation and an external 10 kΩ pull-down

protectio n resistor sho uld be added to the

CS pin.

Memory

Array

Data Register

Mode

Decode

Logic

Clock

Address

Decoder

Address

Counter

Output

Buffer DO

ORG*

CLK

VCC VSS

*ORG input is not available on A/B devices

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.4 Erase

The ERASE instruction forces all data bits of the speci-

fied address to the logical ‘1’ state. CS is brought low

follow ing the l oading o f the las t address b it. This f alling

edge of the CS pin initiates the self-timed program-

ming cycle, except on ‘93C’ devices where the rising

edge of CLK before the last address bit initiates the

write cycle.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logi cal ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the device is ready for another instruction.

FIGU RE 2-1 : ERAS E TIMI NG FO R 93AA AN D 93L C D EVI CE S

FIGURE 2-2: ERASE TIMING FOR 93C DEVICES

Note: After the Erase cycle is complete, issuing

a S t art bit and t hen ta king CS low wil l clear

the Ready/Busy status from DO.

CLK

TCSL

Check Status

111ANAN-1 AN-2 ••• A0

TSV TCZ

Busy Ready High-Z

TWC

High-Z

CLK

TCSL

Check Status

111ANAN-1 AN-2 ••• A0

TSV TCZ

Busy Ready High-Z

TWC

High-Z

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.5 Erase All (ERAL)

The Erase All (ERAL) instruction will erase the entire

memory array to the logical ‘1’ state. The ERAL cycle

is identical to the erase cycle, except for the different

opcode. The ERAL cycle is completely self-timed and

commences at the falling edge of the CS, except on

‘93C’ devices where the rising edge of CLK before the

last data bit initiates the write cycle. Clocking of the

CLK pin is not necessary after the device has entered

the ERAL cycle.

The DO pin indicates the Ready/Busy status of the

device , if CS is brough t high a fter a mi nimum of 250 n s

low ( TCSL).

VCC must be ≥ 4.5V for proper operation of ERAL.

FIGU RE 2- 3 : ER AL TIM IN G F O R 93 AA AND 9 3 LC DE VI C ES

FIGU RE 2-4: ERAL T IM ING FOR 93 C DEVICE S

Note: After the ERAL command is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

TCSL

Check Status

100 10x

••• x

TSV TCZ

Busy Ready High-Z

TEC

High-Z

VCC must be ≥ 4.5V for proper operation of ERAL.

CLK

TCSL

Check Status

100 10x

••• x

TSV TCZ

Busy Ready High-Z

TEC

High-Z

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.6 Erase/Write Disabl e and Enable

(EWDS/EWEN)

The 93XX56A/B/C powers up in the Erase/Write

Disable (EWDS) state. All programming modes must be

precede d by an Erase/W rite Ena ble (EWEN) ins tructio n.

Once the EWEN instruction is executed, programming

remains enabled until an EWDS instruction is executed

or Vcc is removed from the device.

To protect against accidental data disturbance, the

EWDS instruction can be used to disable all erase/write

functions and should follow all programming opera-

tions. Exe cution of a READ instr uction is indep endent of

both the EWEN and EWDS instructions.

FIGURE 2-5: EWDS T IMING

FIGURE 2-6: EWEN TIMING

2.7 Read

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 8-bit (if ORG pin is low or A-Version

devices) or 16-bit (if ORG pin is high or B-version

devic es) ou tput st ring. The ou tput dat a bi ts will toggle on

the rising edge of the CLK and are stable after the spec-

ified time dela y (TPD). S equ entia l read is po ssibl e when

CS is held high. The memory data will automatically cycle

to t he ne xt re gi ster an d o utput s eq ue nt ia ll y.

FIGU RE 2- 7 : RE AD TIMING

CLK

DI 10

000x ••• x

TCSL

CLK

DI 00 1 1x

TCSL

•••

CLK

110

An ••• A0

High-Z 0Dx ••• D0 Dx ••• D0 •••

Dx D0

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.8 Write

The WRITE instruction is followed by 8 bits (if ORG is

low or A-versio n devices) or 16 bits (if ORG pin is high

or B-versi on devices) of data whi ch are writt en into th e

specified address. For 93AA56A/B/C and 93LC56A/B/C

devices, after the last data bit is clocked into DI, the

falling edge of CS initiates the self-timed auto-erase and

programmin g c ycle. F or 93 C56A/ B/C d evices , the se lf-

timed auto-erase and programming cycle is initiated by

the rising edge of CLK on the last data bit.

The DO pin indicates the Ready/Busy status of the

device , if CS is brough t high a fter a mi nimum of 250 n s

low (TCSL). DO at logi cal ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the data specified and the device is ready for another

instruction.

FIGU RE 2- 8 : WRIT E TIM IN G FO R 93 AA A ND 93LC DEVICE S

FIGU RE 2-9: WRITE TIM IN G FOR 93 C DEVICE S

Note: Aft er the W rite cy cle is c omplete, issuing a

Start bit and then taking CS low will clear

the Ready/Busy status from DO.

CLK

101An ••• A0 Dx ••• D0

Busy Ready High-Z

High-Z

TWC

TCSL

TCZ

TSV

CLK

101An ••• A0 Dx ••• D0

Busy Ready High-Z

High-Z

TWC

TCSL

TCZ

TSV

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.9 Write All (WRAL)

The Write All (WRAL) instruction will write the entire

memory array with the data specified in the command.

For 93AA56A/ B/C and 93LC56 A/B/C de vices, after th e

last data bit is clocked into DI, the falling edge of CS

initiates the self-timed auto-erase and programming

cycle. For 93C56A/B/C devices, the self-timed auto-

erase and programming cycle is initiated by the rising

edge of CLK on the last data bit. Clocking of the CLK

pin is not necessary after the device has entered the

WRAL cycle. The WRAL command does include an

automatic ERAL cycle for the device. Therefore, the

WRAL instruction does not require an ERAL instruct i on,

but the chip must be in the EWEN status.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low ( TCSL).

VCC must be ≥ 4.5V for proper operation of WRAL.

FIGURE 2-10: WRAL T IMING FOR 93AA AND 93LC DEVICES

FIGURE 2-1 1: WRAL TIMING FOR 93C DEVICES

Note: After the Write All cycle is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

DO High-Z

10001 x

••• xDx ••• D0

High-Z Busy Ready

TWL

VCC must be ≥ 4.5V for proper operation of WRAL.

TCSL

TSV TCZ

CLK

DO High-Z

10001 x

••• xDx ••• D0

High-Z Busy Ready

TWL

TCSL

TSV TCZ

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN DESCRIPTIONS

3.1 Chip Select (CS)

A high level selects the device; a low level deselects

the dev ice and fo rces it i nto S t andby mode. H owever , a

progra mmin g c yc le which is al read y i n pro gres s wi ll be

completed, regardless of the Chip Select (CS) input

signal . I f C S is brou gh t low duri ng a p r ogra m cyc le, th e

device will go into Standby mode as soon as the

programming cycle is completed.

CS must be low for 250 ns minimum (TCSL) between

consecutive instructions. If CS is low, the internal

control logic is held in a Reset status.

3.2 Serial Clock (CLK)

The Serial Clock is used to synchronize the communi-

cation between a master device and the 93XX series

device. Opcodes, address and data bits are clocked in

on the pos itive edge of CL K. Dat a bit s are also c locke d

out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to Clock High Time (TCKH) and

Clock Low Time (TCKL). This gives the controlling

master freedom in preparing opcode, address and

data.

CLK is a “don’t c are” if CS is low (de vice deselec ted). If

CS is high, but the Start condition has not been

detected (DI = 0), any number of clock cycles can be

received by the device without changing its status (i.e.,

waiting for a Start condition).

CLK cycles are not required during the self-timed write

(i.e., auto erase/write) cycle.

After detec tion of a S tart condition t he specified nu mber

of clock cycles (respectively low-to-high transitions of

CLK) must be provided. These clock cycles are

required to clock in all required opcode, address and

data bit s b efo re an in stru ction is ex ec ute d. CL K and D I

then bec om e “d on ’t c are ” in puts waiting for a new Start

condition to be detected.

3.3 Data In (DI)

Data In (DI) is used to clock in a Start bit, opcode,

address and data synchronously with the CLK input.

3.4 Data Out (DO)

Dat a Out (DO) is used in the Re ad mode to ou tput dat a

synchronously with the CLK input (TPD after the

positive edge of CLK).

This pin also provides Ready/Busy status information

during era se and write cyc les. Ready/Busy st atus inf or-

mation is available on the DO pin if CS is brought high

after being low for minimum Chip Select low time (TCSL)

and an erase or write operation has been initiated.

The Status signal is not available on DO, if CS is held

low during the entire erase or write cycle. In this case,

DO is in the High -Z mode. If sta tus is check ed after th e

erase/write cycle, the data line will be high to indicate

the device is ready.

3.5 Organization (ORG)

When the ORG pin i s connected to VCC or Logic HI, the

(x16) mem ory organi zation is selected . When the ORG

pin is tied to VSS or Logic LO, the (x8) memory

organization is selected. For proper operation, ORG

must be tied to a valid logic level.

93XX56A devices are always x8 organization and

93XX56B devices are always x16 organization.

Name SOIC/PDIP/

MSOP/TSSOP/

DFN SOT-23 Rotated SOIC Function

CS 1 5 3 Chip Select

CLK 2 4 4 Serial Clock

DI 3 3 5 Data In

DO 4 1 6 Data Out

VSS 527Ground

ORG/NC 6 — 8 Or ganization / 93XX56C

No Internal Connection / 93XX56A/B

NC 7 — 1 No Internal Connection

VCC 8 6 2 Power Supply

Note: After a programming cycle is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Example:

6-Lead SOT-23

8-Lead MSOP (150 mil) Example:

XXXXXXT

YWWNNN 3L56BI

5281L7

XXNN 2EL7

T/XXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

8-Lead SOIC

XXXXYYWW

XXXXXXXT

NNN

XXXX

TYWW

8-Lead TSSOP

NNN

I/P 1L7

93LC56B

0528

Example:

SN 0528

93LC56BI

1L7

L56B

I528

Example:

8-Lead 2x3 DFN Example:

374

528

XXX

YWW

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

Note: T = Temperature grade (I, E)

NN = Alphanumeric traceability code

Part Number 1st Line Marking Codes

TSSOP MSOP SOT-23 DFN

I Temp. E Temp. I Temp. E Temp.

93AA56A A56A 3A56AT 2BNN — 331 —

93AA56B A56B 3A56BT 2LNN — 341 —

93AA56C A56C 3A56CT — — 351 —

93LC56A L56A 3L56AT 2ENN 2FNN 334 335

93LC56B L56B 3L56BT 2PNN 2RNN 344 345

93LC56C L56C 3L56CT — — 354 355

93C56A C56A 3C56AT 2HNN 2JNN 337 338

93C56B C56B 3C56BT 2TNN 2UNN 347 348

93C56C C56C 3C56CT — — 357 358

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the fu ll Microc hip p art num ber cann ot be marked on one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

(F)

n 1

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037 REFFFootprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.009

.006

.012

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch

.016 .024

.118 BSC

.000

.030

.193 TYP.

.033

MIN

Units

.026 BSC

NOM

INCHES

0.95 REF

.009

.016

0.08

0.22

0°

0.23

0.40

8°

MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX NOM

1.10

0.80

0.15

0.95

MAX

15°5° -

JEDEC Equivalent: MO-187

0° - 8°

5°

5° -

15°

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

6-Lead Plastic Small Outline Transistor (OT) (SOT-23)

10501050

Mold Draft Angle Bottom

10501050

Mold Draft Angle Top

0.500.430.35.020.017.014BLead Width

0.200.150.09.008.006.004

Lead Thickness

10501050

Foot Angle

0.550.450.35.022.018.014LFoot Length

3.102.952.80.122.116.110DOverall Length

1.751.631.50.069.064.059

Molded Package Width

3.002.802.60.118.110.102EOverall Width

0.150.080.00.006.003.000

Standoff

1.301.100.90.051.043.035

Molded Package Thickness

1.451.180.90.057.046.035AOverall Height

1.90.075

Outside lead pitch (basic)

0.95.038

Pitch

Number of Pins

MAX

NOM

MINMAX

NOM

MINDimension Limits

MILLIMETERSINCHES*Units

exceed .005" (0.127mm) per side.

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

Notes:

JEITA (formerly EIAJ) equivalent: SC-74A

Drawing No. C04-120

*Controlling Parameter

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder W idt h E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004

Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1M old ed Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002

Standoff § 0.950.900.85.037.035.033A2M old ed Pa ckag e Thick ness 1.10.043AOverall Height 0.65.026

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERS*INCHES

Units

Foot A ngle φ048048

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

§ Significant Characteristic

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulat ed

Exposed Pad Width

Exposed Pad Length

Contact Length

*Controlling Parameter

Contact Width

Drawing No. C04-123

Notes:

Exposed pad dimensions vary with paddle size.

Overall Width

.016

.012

.008

.047

.055

.010

.118 BSC

Number of Pins

Standoff

Contact Thickness

Overall Length

Overall Height

Pitch p

Units

Dimension Limits

.000 .001

.008 REF.

.079 BSC

.031

.020 BSC

MIN

INCHES

NOM

0.40

0.25

3.00 BSC

0.30

.020

.071

.012

.064

0.20

1.20

1.39

0.50

0.30

1.80

1.62

0.02

0.80

2.00 BSC

0.20 REF.

0.50 BSC

MILLIMETERS*

.002

.039

0.00

MINMAX NOM

0.05

1.00

MAX

Package may have one or more exposed tie bars at ends.1.

Pin 1 visual index feature may vary, but must be located within the hatched area.2.

0.90.035

(Note 3)

4. JEDEC equivalent: MO-229

A3 A1

TOP VIEW

EXPOSED

PAD

METAL

BOTTOM VIEW

(NOTE 1)

EXPOSED

TIE BAR

PIN 1

(NOTE 2)

ID INDEX

AREA

Revised 05/24/04

-- --

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

APPENDIX A: REVISION HISTORY

Revision B

Corrections to Section 1.0, Electrical Characteristics.

Section 4.1, 6-Lead SOT-23 package to OT.

Revision C

Added DFN package.

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

NOTES:

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

docume nts , latest softw are releas es and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Micro chi p con sul tant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is a vailable through the web site

at: http://support.microchip.com

In addition, there is a Development Systems

Information Line which lists the latest versions of

Microchip’s development systems software products.

This line also provides information on how customers

can receive currently available upgrade kits.

The Development Systems Information Line

numbers a re:

1-800-755-2345 – United States and most of Canada

1-480-792-7302 – Other International Locations

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

READER RESPONSE

It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21794C93AA56A/B/C, 93L C56A /B/C, 93C56A/B/C

1. What are the be st features of this docu ment?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured

before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).

Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences

and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of

the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Device: 93AA56A: 2K 1.8V Microwire S erial EEPROM

93AA56B: 2K 1.8V Microwire Serial EEPROM

93AA56C: 2K 1.8V Microwire Serial EEPRO M w/ORG

93LC56A: 2K 2.5V Microwire Serial EEPROM

93LC56B: 2K 2.5V Microwire Serial EEPROM

93LC56C: 2K 2.5V Microwire Serial EEPROM w/ORG

93C56A: 2K 5.0V Microwire Serial EEPROM

93C56B: 2K 5.0V Microwire Serial EEPROM

93C56C: 2K 5.0V Microwire Serial EEPROM w/ORG

Pinout: Blank = Standard pinout

X = Ro tated pi no ut

Tape & Reel: Blank = Standard packaging

T=Tape & Reel

Temperature Range: I = -40°C to +85°C

E = -40°C to +125°C

Package: MS = Plastic MSOP (Micro Small outline, 8-lead)

OT = SOT-23, 6-lead (Tape & Reel only)

P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body), 8-lead

ST = TSSOP, 8-lead

MC = 2x3 DFN, 8-lead

Lead Finish: Blank = Pb-free – Matte Tin (see Note 1)

G = Pb-free – Matte Tin only

Examples:

a) 93AA56C-I/MS: 2K, 256x8 or 128x16 Serial

EEPROM, MSOP package, 1.8V

b) 93AA56B-I/MS: 2K, 128x16 Serial EEPROM,

MSOP package, 1.8V

c) 93AA56AT-I/OT: 2K, 256x8 Serial EEPROM,

SOT-23 package, tape and reel, 1.8V

d) 93AA56CT-I/MS: 2K, 256x8 or 128x16 Serial

EEPROM, MSOP package, tape and reel, 1.8V

a) 93LC56A-I/MS: 2K, 256x8 Serial EEPROM,

MSOP package, 2.5V

b) 93LC56BT-I/OT: 2K, 128x16 Serial EEPROM,

SOT-23 package, tape and reel, 2.5V

c) 93LC56B-I/MS: 2K, 128x16 Serial EEPROM,

MSOP package, 2.5V

a) 93C56B-I/MS: 2K, 128x16 Serial EEPROM,

MSOP package, 5.0V

b) 93C56C-I/MS: 2K, 256x8 or 128x16 Serial

EEPROM, MSOP package, 5.0V

c) 93C56AT-I/OT: 2K, 256x8 Serial EEPROM,

SOT-23 package, tape and reel, 5.0V

PART NO. X/XX

Package

Temperature

Range

Device

Lea d Fi nish

Tape & Reel

Pinout

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. U se of Microc hip’s products as critical com ponents in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, M XDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Prog ra mming, IC SP, ICEPIC, MPASM, MPLI B, M PL I N K,

MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICt ail,

PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance and WiperLock are trademarks of Microchip

Tec hnology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure famili es of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving the c ode prot ecti on features of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

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WORLDWIDE SALES AND SERVICE

03/01/05