X28HC256 (R) 256k, 32k x 8-Bit Data Sheet May 7, 2007 5V, Byte Alterable EEPROM Features The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil's proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. * Access time: 70ns The X28HC256 supports a 128-byte page write operation, effectively providing a 24s/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years. FN8108.2 * Simple byte and page write - Single 5V supply - No external high voltages or VP-P control circuits - Self-timed - No erase before write - No complex programming algorithms - No overerase problem * Low power CMOS - Active: 60mA - Standby: 500A * Software data protection - Protects data against system level inadvertent writes * High speed page write capability * Highly reliable Direct WriteTM cell - Endurance: 1,000,000 cycles - Data retention: 100 years * Early end of write detection - DATA polling - Toggle bit polling * Pb-free plus anneal available (RoHS compliant) Block Diagram X BUFFERS LATCHES AND DECODER 256kBIT EEPROM ARRAY A0 TO A14 ADDRESS INPUTS Y BUFFERS LATCHES AND DECODER I/O BUFFERS AND LATCHES I/O0 TO I/O7 CE OE WE DATA INPUTS/OUTPUTS CONTROL LOGIC AND TIMING VCC VSS 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X28HC256 Ordering Information PART MARKING ACCESS TIME (ns) TEMP. RANGE (C) X28HC256DI-15 X28HC256DI-15 RR 150 -40 to +85 28 Ld CERDIP F28.6 X28HC256DM-15 X28HC256DM-15 RR -55 to +125 28 Ld CERDIP F28.6 X28HC256DMB-15 C X28HC256DMB-15 MIL-STD-883 28 Ld CERDIP F28.6 X28HC256EMB-15 C X28HC256EMB-15 MIL-STD-883 32 Ld LCC (458 mils) X28HC256FMB-15 C X28HC256FMB-15 MIL-STD-883 X28HC256J-15*, ** X28HC256J-15 RR 0 to +70 32 Ld PLCC N32.45x55 X28HC256JZ-15* (Note) X28HC256J-15 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JI-15*, ** X28HC256JI-15 RR -40 to +85 32 Ld PLCC N32.45x55 X28HC256JIZ-15* (Note) X28HC256JI-15 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JM-15* X28HC256JM-15 RR -55 to +125 32 Ld PLCC N32.45x55 X28HC256KI-15 X28HC256KI-15 RR -40 to +85 28 Ld PGA G28.550x650A X28HC256KM-15 X28HC256KM-15 RR -55 to +125 28 Ld PGA G28.550x650A X28HC256KMB-15 C X28HC256KMB-15 MIL-STD-883 28 Ld PGA G28.550x650A X28HC256P-15 X28HC256P-15 RR 0 to +70 28 Ld PDIP E28.6 X28HC256PZ-15 (Note) X28HC256P-15 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6 X28HC256PI-15 X28HC256PI-15 RR -40 to +85 28 Ld PDIP E28.6 X28HC256PIZ-15 (Note) X28HC256PI-15 RRZ -40 to +85 28 Ld PDIP (Pb-free)*** E28.6 X28HC256PM-15 X28HC256PM-15 RR -55 to +125 28 Ld PDIP E28.6 X28HC256SI-15* X28HC256SI-15 RR -40 to +85 28 Ld SOIC (300 mil) MDP0027 X28HC256SIZ-15* (Note) X28HC256SI-15 RRZ -40 to +85 28 Ld SOIC (300 mil) (Pb-free) MDP0027 X28HC256SM-15 X28HC256SM-15 RR -55 to +125 X28HC256D-12 X28HC256D-12 RR X28HC256DI-12 PART NUMBER PACKAGE PKG. DWG. # 28 Ld FLATPACK (440 mils) 28 Ld SOIC (300 mil) MDP0027 0 to +70 28 Ld CERDIP (520 mils) F28.6 X28HC256DI-12 RR -40 to +85 28 Ld CERDIP (520 mils) F28.6 X28HC256DM-12 X28HC256DM-12 RR -55 to +125 28 Ld CERDIP (520 mils) F28.6 X28HC256DMB-12 C X28HC256DMB-12 MIL-STD-883 28 Ld CERDIP (520 mils) F28.6 X28HC256EI-12 X28HC256EI-12 RR -40 to +85 32 Ld LCC (458 mils) X28HC256EM-12 X28HC256EM-12 RR -55 to +125 32 Ld LCC (458 mils) X28HC256EMB-12 C X28HC256EMB-12 MIL-STD-883 32 Ld LCC (458 mils) X28HC256FMB-12 C X28HC256FMB-12 MIL-STD-883 28 Ld FLATPACK (440 mils) X28HC256J-12* X28HC256J-12 RR 0 to +70 32 Ld PLCC N32.45x55 X28HC256JZ-12* (Note) X28HC256J-12 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JI-12* X28HC256JI-12 RR -40 to +85 32 Ld PLCC N32.45x55 X28HC256JIZ-12* (Note) X28HC256JI-12 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC256KI-12 X28HC256KI-12 RR -40 to +85 28 Ld PGA G28.550x650A X28HC256KM-12 X28HC256KM-12 RR -55 to +125 28 Ld PGA G28.550x650A X28HC256KMB-12 C X28HC256KMB-12 MIL-STD-883 28 Ld PGA G28.550x650A X28HC256P-12 X28HC256P-12 RR 0 to +70 28 Ld PDIP E28.6 X28HC256PZ-12 (Note) X28HC256P-12 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6 X28HC256PI-12 X28HC256PI-12 RR -40 to +85 28 Ld PDIP E28.6 2 120 FN8108.2 May 7, 2007 X28HC256 Ordering Information (Continued) PART NUMBER PART MARKING X28HC256PIZ-12 (Note) X28HC256PI-12 RRZ X28HC256S-12* X28HC256S-12 RR X28HC256SZ-12 (Note) ACCESS TIME (ns) TEMP. RANGE (C) -40 to +85 PACKAGE PKG. DWG. # 28 Ld PDIP (Pb-free)*** E28.6 0 to +70 28 Ld SOIC (300 mils) MDP0027 X28HC256S-12 RRZ 0 to +70 28 Ld SOIC (300 mils) (Pb-free) MDP0027 X28HC256SI-12* X28HC256SI-12 RR -40 to +85 28 Ld SOIC (300 mils) MDP0027 X28HC256SIZ-12 (Note) X28HC256SI-12 RRZ -40 to +85 28 Ld SOIC (300 mils) (Pb-free) MDP0027 X28HC256SM-12*, ** X28HC256SM-12 RR -55 to +125 28 Ld SOIC (300 mils) MDP0027 X28HC256D-90 X28HC256D-90 RR 0 to +70 28 Ld CERDIP (520 mils) F28.6 X28HC256DI-90 X28HC256DI-90 RR -40 to +85 28 Ld CERDIP (520 mils) F28.6 X28HC256DM-90 X28HC256DM-90 RR -55 to +125 28 Ld CERDIP (520 mils) F28.6 X28HC256DMB-90 C X28HC256DMB-90 MIL-STD-883 28 Ld CERDIP (520 mils) F28.6 X28HC256EM-90 X28HC256EM-90 RR -55 to +125 32 Ld LCC (458 mils) X28HC256EMB-90 C X28HC256EMB-90 MIL-STD-883 32 Ld LCC (458 mils) 120 90 X28HC256FI-90 X28HC256FI-90 RR -40 to +85 28 Ld FLATPACK (440 mils) X28HC256FM-90 X28HC256FM-90 RR -55 to +125 28 Ld FLATPACK (440 mils) X28HC256FMB-90 C X28HC256FMB-90 MIL-STD-883 28 Ld FLATPACK (440 mils) X28HC256J-90* X28HC256J-90 RR 0 to +70 32 Ld PLCC N32.45x55 X28HC256JZ-90* (Note) X28HC256J-90 ZRR 0 to +70 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JI-90* X28HC256JI-90 RR -40 to +85 32 Ld PLCC N32.45x55 X28HC256JIZ-90* (Note) X28HC256JI-90 ZRR -40 to +85 32 Ld PLCC (Pb-free) N32.45x55 X28HC256JM-90* X28HC256JM-90 RR -55 to +125 32 Ld PLCC N32.45x55 X28HC256KM-90 X28HC256KM-90 RR -55 to +125 28 Ld PGA G28.550x650A X28HC256KMB-90 C X28HC256KMB-90 MIL-STD-883 28 Ld PGA G28.550x650A X28HC256P-90 X28HC256P-90 RR 0 to +70 28 Ld PDIP E28.6 X28HC256PZ-90 (Note) X28HC256P-90 RRZ 0 to +70 28 Ld PDIP (Pb-free)*** E28.6 X28HC256PI-90 X28HC256PI-90 RR -40 to +85 28 Ld PDIP E28.6 X28HC256PIZ-90 (Note) X28HC256PI-90 RRZ -40 to +85 28 Ld PDIP (Pb-free)** E28.6 X28HC256S-90* X28HC256S-90 RR 0 to +70 28 Ld SOIC (300 mils) MDP0027 X28HC256SI-90* X28HC256SI-90 RR -40 to +85 28 Ld SOIC (300 mils) MDP0027 X28HC256SIZ-90 (Note) X28HC256SI-90 RRZ -40 to +85 28 Ld SOIC (300 mils) (Pb-free) MDP0027 -40 to +85 28 Ld SOIC (300 mils) Tape and Reel MDP0027 X28HC256SI-20T1 90 200 *Add "T1" suffix for tape and reel. **Add "T2" suffix for tape and reel. ***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3 FN8108.2 May 7, 2007 X28HC256 Pinouts A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 A2 22 X28HC256 8 21 OE A10 A1 9 20 A0 10 19 CE I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 VSS 13 16 I/O4 14 15 I/O3 4 3 A13 WE A13 I/O1 I/O2 I/O3 I/O5 I/O6 12 13 15 17 18 2 1 32 31 30 A6 5 29 A8 A5 6 7 28 27 A9 8 9 26 25 A4 A3 A2 A1 A0 NC I/O0 X28HC256 10 11 24 23 12 22 13 21 14 15 16 17 18 19 20 I/O0 A0 10 11 VSS I/O4 I/O7 14 16 19 A3 7 A2 CE A10 8 20 21 X28HC256 A4 OE A11 6 23 22 A10 A5 5 A12 VCC A9 2 28 24 CE I/O7 A6 4 A7 3 A11 NC OE A1 9 1 A14 A8 25 WE A13 27 26 I/O6 I/O5 26 VCC WE 27 3 I/O4 2 A7 A14 NC A12 A7 VCC A12 28 I/O2 VSS NC I/O3 1 I/O1 A14 X28HC256 (28 LD PGA) BOTTOM VIEW X28HC256 (32 LD PLCC, LCC) TOP VIEW X28HC256 (28 LD CERDIP, FLATPACK, PDIP, SOIC) TOP VIEW Pin Descriptions Addresses (A0 to A14) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers, and is used to initiate read operations. Data In/Data Out (I/O0 to I/O7) Data is written to or read from the X28HC256 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28HC256. 4 FN8108.2 May 7, 2007 X28HC256 Pin Names SYMBOL DESCRIPTION A0 to A14 Address Inputs I/O0 to I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect Device Operation Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. Write Operation Status Bits The X28HC256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. I/O DP TB 5 4 3 2 TOGGLE BIT Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3ms. DATA POLLING The page write feature of the X28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the X28HC256, prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. 5 0 RESERVED Write Page Write Operation 1 FIGURE 1. STATUS BIT ASSIGNMENT DATA Polling (I/O7) The X28HC256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28HC256. This eliminates additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Toggle Bit (I/O6) The X28HC256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease, and the device will be accessible for additional read and write operations. FN8108.2 May 7, 2007 X28HC256 DATA Polling I/O7 WE LAST WRITE CE OE VIH VOH HIGH Z I/O7 VOL A0 TO A14 An An An X28HC256 READY An An An An FIGURE 2. DATA POLLING BUS SEQUENCE DATA Polling can effectively halve the time for writing to the X28HC256. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine. WRITE DATA NO WRITES COMPLETE? YES SAVE LAST DATA AND ADDRESS READ LAST ADDRESS IO7 COMPARE? NO YES X28HC256 READY FIGURE 3. DATA POLLING SOFTWARE FLOW 6 FN8108.2 May 7, 2007 X28HC256 The Toggle Bit I/O6 WE LAST WRITE CE OE I/O6 * VOH HIGH Z VOL * X28C512, X28C513 READY * I/O6 Beginning and ending state of I/O6 will vary. FIGURE 4. TOGGLE BIT BUS SEQUENCE Hardware Data Protection The X28HC256 provides two hardware features that protect nonvolatile data from inadvertent writes. LAST WRITE * Default VCC Sense--All write functions are inhibited when VCC is 3.5V typically. YES * Write Inhibit--Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity. LOAD ACCUM FROM ADDR n Software Data Protection COMPARE ACCUM WITH ADDR n NO COMPARE OK? YES X28C256 READY FIGURE 5. TOGGLE BIT SOFTWARE FLOW The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. 7 The X28HC256 offers a software-controlled data protection feature. The X28HC256 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28HC256 can be automatically protected during power-up and power-down (without the need for external circuits) by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation, utilizing the software algorithm. This circuit is nonvolatile, and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28HC256 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. FN8108.2 May 7, 2007 X28HC256 Software Algorithm opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence Software Data Protection VCC (VCC) 0V DATA ADDRESS AAA 5555 55 2AAA A0 5555 WRITES OK tWC WRITE PROTECTED CE tBLC MAX WE BYTE OR AGE FIGURE 6. TIMING SEQUENCE--BYTE OR PAGE WRITE Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28HC256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28HC256 will be write protected during power-down and after any subsequent power-up. WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA A0 TO ADDRESS 5555 BYTE/PAGE LOAD ENABLED WRITE DATA XX TO ANY ADDRESS OPTIONAL BYTE/PAGE LOAD OPERATION WRITE LAST BYTE TO LAST ADDRESS AFTER tWC RE-ENTERS DATA PROTECTED STATE FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA 8 FN8108.2 May 7, 2007 X28HC256 Resetting Software Data Protection VCC DATA ADDRESS AAA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 tWC STANDARD OPERATING MODE CE WE FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 20 TO ADDRESS 5555 AFTER tWC, RE-ENTERS UNPROTECTED STATE FIGURE 9. WRITE SEQUENCE FOR RESETTING SOFTWARE In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC256 will be in standard operating mode. 9 Note: Once initiated, the sequence of write operations should not be interrupted. SYSTEM CONSIDERATIONS Because the X28HC256 is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. Because the X28HC256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1F high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7F electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. FN8108.2 May 7, 2007 X28HC256 Absolute Maximum Ratings Thermal Information Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-10C to +85C X28HC256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +135C X28HC256I, X28HC256M . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on any Pin with Respect to VSS . . . . . . . . . . . . . -1V to +7V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commerical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to +125C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified. LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP (Note 7) MAX UNIT VCC Active Current (TTL Inputs) ICC CE = OE = VIL, WE = VIH, All I/O's = open, address inputs = .4V/2.4V levels @ f = 10MHz 30 60 mA VCC Standby Current (TTL Inputs) ISB1 CE = VIH, OE = VIL, All I/O's = open, other inputs = VIH 1 2 mA VCC Standby Current (CMOS Inputs) ISB2 CE = VCC - 0.3V, OE = GND, All I/Os = open, other inputs = VCC - 0.3V 200 500 A Input Leakage Current ILI VIN = VSS to VCC 10 A Output Leakage Current ILO VOUT = VSS to VCC, CE = VIH 10 A Input LOW Voltage VlL (Note 2) -1 0.8 V Input HIGH Voltage VIH (Note 2) 2 VCC + 1 V Output LOW Voltage VOL IOL = 6mA 0.4 V Output HIGH Voltage VOH IOH = -4mA 2.4 V NOTES: 1. Typical values are for TA = +25C and nominal supply voltage. 2. VIL min. and VIH max. are for reference only and are not tested. Power-up Timing PARAMETER SYMBOL MAX UNIT Power-up to read tPUR, Note 3 100 s Power-up to write tPUW, Note 3 5 ms NOTE: 3. This parameter is periodically sampled and not 100% tested. 10 FN8108.2 May 7, 2007 X28HC256 Capacitance TA = +25C, f = 1MHz, VCC = 5V. SYMBOL TEST CONDITIONS MAX UNIT CI/O (Note 9) Input/output capacitance VI/O = 0V 10 pF CIN (Note 9) Input capacitance VIN = 0V 6 pF Endurance and Data Retention PARAMETER MIN Endurance Data retention AC Conditions of Test MAX UNIT 1,000,000 Cycles 100 Years Symbol Table Input pulse levels 0V to 3V Input rise and fall times 5ns Input and output timing levels 1.5V WAVEFORM Mode Selection CE OE WE MODE I/O POWER L L H Read DOUT active L H L Write DIN active H X X Standby and write inhibit High Z standby X L X Write inhibit -- -- X X H Write inhibit -- -- INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Equivalent AC Load Circuit 5V 1.92k OUTPUT 1.37k 30pF 11 FN8108.2 May 7, 2007 X28HC256 AC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified. X28HC256-70 X28HC256-90 X28HC256-12 X28HC256-15 SYMBOL MIN MIN MIN MIN Read Cycle Time tRC (Note 5) 70 Chip Enable Access Time tCE (Note 5) 70 90 120 150 ns Address Access Time tAA (Note 5) 70 90 120 150 ns tOE 35 40 50 50 ns PARAMETER Output Enable Access Time MAX MAX 90 MAX 120 MAX 150 UNIT ns CE LOW to Active Output tLZ (Note 4) 0 0 0 0 ns OE LOW to Active Output tOLZ (Note 4) 0 0 0 0 ns CE HIGH to High Z Output tHZ (Note 4) 35 40 50 50 ns OE HIGH to High Z Output tOHZ (Note 4) 35 40 50 50 ns Output Hold from Address Change tOH 0 0 0 0 ns Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tOLZ tOHZ tLZ DATA I/O HIGH Z tOH DATA VALID tHZ DATA VALID tAA NOTES: 4. tLZ min., tHZ, tOLZ min. and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured with CL = 5pF, from the point when CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. 5. For faster 256k products, refer to X28VC256 product line. 12 FN8108.2 May 7, 2007 X28HC256 Write Cycle Limits PARAMETER SYMBOL MIN tWC (Note 7) Write Cycle Time TYP (Note 6) MAX UNIT 3 5 ms Address Setup Time tAS 0 ns Address Hold Time tAH 50 ns Write Setup Time tCS 0 ns Write Hold Time tCH 0 ns CE Pulse Width tCW 50 ns OE HIGH Setup Time tOES 0 ns OE HIGH Hold Time tOEH 0 ns WE Pulse Width tWP 50 ns tWPH (Note 8) 50 ns WE HIGH Recovery (page write only) Data Valid tDV Data Setup tDS 50 ns Data Hold tDH 0 ns tDW (Note 8) 10 s tBLC 0.15 Delay to Next Write After Polling is True Byte Load Cycle 1 100 s s NOTES: 6. Typical values are for TA = +25C and nominal supply voltage. 7. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 8. tWPH and tDW are periodically sampled and not 100% tested. WE Controlled Write Cycle tWC ADDRESS tAS tAH tCS tCH CE OE tOES tOEH tWP WE DATA IN DATA VALID tDS tDH HIGH Z DATA OUT 13 FN8108.2 May 7, 2007 X28HC256 CE Controlled Write Cycle tWC ADDRESS tAS tAH tCW CE tOES OE tOEH tCS tCH WE DATA VALID DATA IN tDS tDH HIGH Z DATA OUT Page Write Cycle OE (NOTE 9) CE tBLC tWP WE tWPH ADDRESS (NOTE 10) LAST BYTE I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n + 1 BYTE n + 2 tWC *For each successive write within the page write operation, A7 to A15 should be the same or writes to an unknown address could occur. NOTES: 9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 14 FN8108.2 May 7, 2007 X28HC256 DATA Polling Timing Diagram (Note 11) ADDRESS An An An CE WE tOEH tOES OE tDW I/O7 DIN = X DOUT = X DOUT = X tWC Toggle Bit Timing Diagram (Note 11) CE WE tOES tOEH OE tDW I/O6 HIGH Z * * tWC * I/O6 beginning and ending state will vary, depending upon actual tWC. NOTE: 11. Polling operations are by definition read cycles and are therefore subject to read cycle timings. 15 FN8108.2 May 7, 2007 X28HC256 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE METAL E M -Bbbb S C A-B S (c) Q -C- SEATING PLANE S1 b2 b C A-B S eA/2 NOTES - 0.232 - 5.92 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 - 37.85 5 E 0.500 0.610 15.49 5 c aaa M C A - B S D S D S MAX 0.014 eA e MIN b A A MILLIMETERS MAX A A L MIN M (b) SECTION A-A D S INCHES SYMBOL b1 D BASE PLANE ccc M F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE LEAD FINISH c1 -D- -A- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. e 12.70 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 90o aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. N 28 28 8 Rev. 0 4/94 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 16 FN8108.2 May 7, 2007 X28HC256 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) 0.050 (1.27) TP 0.025 (0.64) R 0.045 (1.14) ND CL C N32.45x55 (JEDEC MS-016AE ISSUE A) 32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL D2/E2 C L E1 E D2/E2 NE VIEW "A" A1 A D1 D 0.015 (0.38) MIN SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.050 (1.27) MIN MIN MAX MILLIMETERS MIN MAX NOTES A 0.125 0.140 3.18 3.55 - A1 0.060 0.095 1.53 2.41 - D 0.485 0.495 12.32 12.57 - D1 0.447 0.453 11.36 11.50 3 D2 0.188 0.223 4.78 5.66 4, 5 E 0.585 0.595 14.86 15.11 - E1 0.547 0.553 13.90 14.04 3 E2 0.238 0.273 6.05 6.93 4, 5 N 28 28 6 ND 7 7 7 NE 9 9 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN (0.12) M A S -B S D S 0.005 VIEW "A" TYP. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions. 7. ND denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. NE denotes the number of leads on the two long sides of the package. 17 FN8108.2 May 7, 2007 X28HC256 Ceramic Pin Grid Array Package (CPGA) G28.550x650A 28 LEAD CERAMIC PIN GRID ARRAY PACKAGE 12 13 15 17 18 11 10 14 16 19 A 0.008 (0.20) 9 8 20 21 7 6 22 23 0.050 (1.27) A 5 2 28 24 25 4 3 1 27 26 Typ. 0.100 (2.54) All Leads 0.080 (2.03) 0.070 (1.78) NOTE: Leads 4, 12, 18, and 26 0.080 (2.03) 4 Corners 0.070 (1.78) 0.110 (2.79) 0.090 (2.29) 0.072 (1.83) Pin 1 Index 0.062 (1.57) 0.020 (0.51) 0.016 (0.41) 0.660 (16.76) 0.640 (16.26) A A 0.561 (14.25) 0.185 (4.70) 0.541 (13.75) 0.175 (4.44) NOTE: All dimensions in inches (in parentheses in millimeters). Rev. 0 12/05 18 FN8108.2 May 7, 2007 X28HC256 Small Outline Package Family (SO) A D h X 45 (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL "X" 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4 4 DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300") (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150") 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 19 FN8108.2 May 7, 2007 X28HC256 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-011-AB ISSUE B) N 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.380 1.565 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 35.1 39.7 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. N 28 28 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 9 Rev. 1 12/00 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8108.2 May 7, 2007