DRV102F/500 - Texas Instruments

DRV102

PWM SOLENOID/VALVE DRIVER

FEATURES

●HIGH OUTPUT DRIVE: 2.7A

●WIDE SUPPLY RANGE: +8V to +60V

●COMPLETE FUNCTION

PWM Output

Internal 24kHz Oscillator

Digital Control Input

Adjustable Delay and Duty Cycle

Over/Under Current Indicator

●FULLY PROTECTED

Thermal Shutdown with Indicator

Internal Current Limit

●POWER PACKAGES: 7-Lead TO-220 and

7-Lead Surface-Mount DDPAK

APPLICATIONS

●ELECTROMECHANICAL DRIVERS:

Solenoids Positioners

Actuators

High Power Relays/Contactors

Valves Clutches/Brakes

●SOLENOID OVERHEAT PROTECTORS

●FLUID AND GAS FLOW CONTROLLERS

●PART HANDLERS

●ELECTRICAL HEATERS/COOLERS

●MOTOR SPEED CONTROLLERS

●INDUSTRIAL CONTROL

●FACTORY AUTOMATION

●MEDICAL ANALYSIS

●PHOTOGRAPHIC PROCESSING

DESCRIPTION

The DRV102 is a high-side power switch employing a

pulse-width modulated (PWM) output. Its rugged de-

sign is optimized for driving electromechanical devices

such as valves, solenoids, relays, actuators, and

positioners. The DRV102 is also ideal for driving

thermal devices such as heaters and lamps. PWM

operation conserves power and reduces heat rise in

the device, resulting in higher reliability. In addition,

adjustable PWM allows fine control of the power

delivered to the load. Time from dc output to PWM

output is externally adjustable.

DRV102

Delay

Adjust

Input

(TTL-Compatible)

Off

Thermal Shutdown

Over/Under Current

Flag

Duty Cycle

Adjust

Load

DRV102

24kHz

Oscillator

PWM

5(+8V to +60V)

(Gnd electrically

connected to tab)

Out

Gnd(1) 4

Delay

The DRV102 can be set to provide a strong initial

closure, automatically switching to a soft hold mode for

power savings. Duty cycle can be controlled by a

resistor, analog voltage, or digital-to-analog converter

for versatility. A flag output indicates thermal shutdown

and over/under current limit. A wide supply range

allows use with a variety of actuators.

The DRV102 is available in a 7-lead staggered TO-220

package and a 7-lead surface-mount DDPAK plastic

power package. It operates from –55°C to +125°C.

SBVS009B – JANUARY 1998 – REVISED MAY 2009

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PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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DRV102

2SBVS009B

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SPECIFICATIONS

At TC = +25°C, VS = +24V, load = series diode MUR415 and 100Ω, and 4.99kΩ Flag pull-up to +5V, unless otherwise noted.

DRV102T, F

PARAMETER CONDITIONS MIN TYP MAX UNITS

OUTPUT

Output Saturation Voltage, Source IO = 1A +1.7 +2.2 V

IO = 0.1A +1.3 +1.7 V

Current Limit 2 2.7 3.4 A

Under-Scale Current 16 mA

Leakage Current Output Transistor Off, VS = +60V, VO = 0V ±0.01 ±2mA

DIGITAL CONTROL INPUT(1)

VCTR Low (output disabled) 0 +1.2 V

VCTR High (output enabled) +2.2 VSV

ICTR Low (output disabled) VCTR = 0V –80(2) µA

ICTR High (output enabled) VCTR = +5V 20(2) µA

Propagation Delay: On-to-Off 0.9 µs

Off-to-On 1.8 µs

DELAY TO PWM(3) dc to PWM Mode

Delay Equation(4) Delay to PWM ≈ CD • 106 (CD in F) s

Delay Time CD = 0.1µF 80 97 110 ms

Minimum Delay Time(5) CD = 0 15 µs

DUTY CYCLE ADJUST

Duty Cycle Range 10 to 90 %

Duty Cycle Accuracy 49% Duty Cycle, RPWM = 25.5kΩ±1±7%

vs Supply Voltage 49% Duty Cycle, VS = 8V to 60V ±1±5%

Nonlinearity(6) 20% to 80% Duty Cycle ±2 % FSR

DYNAMIC RESPONSE

Output Voltage Rise Time VO = 10% to 90% of VS0.25 2.5 µs

Output Voltage Fall Time VO = 90% to 10% of VS0.25 2.5 µs

Oscillator Frequency 19 24 29 kHz

FLAG

Normal Operation 20kΩ Pull-Up to +5V, IO < 1.5A +4 +4.9 V

Fault(7) Sinking 1mA +0.2 +0.4 V

Sink Current VFLAG = 0.4V 2 mA

Under-Current Flag: Set 5.2 µs

Reset 11 µs

Over-Current Flag: Set 5.2 µs

Reset 11.5 µs

THERMAL SHUTDOWN

Junction Temperature

Shutdown +165 °C

Reset from Shutdown +150 °C

POWER SUPPLY

Specified Operating Voltage +24 V

Operating Voltage Range +8 +60 V

Quiescent Current IO = 0 6.5 9 mA

TEMPERATURE RANGE

Specified Range –55 +125 °C

Storage Range –55 +125 °C

Thermal Resistance,

7-Lead DDPAK, 7-Lead TO-220 3°C/W

Thermal Resistance,

7-Lead DDPAK, 7-Lead TO-220 No Heat Sink 65 °C/W

NOTES: (1) Logic high enables output (normal operation). (2) Negative conventional current flows out of the terminals. (3) Constant dc output to PWM (pulse-width

modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust pin low corresponds to an infinite (continuous) delay.

(5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 3 to percent of duty cycle at pin 6. (7) A fault results from over-temperature,

over-current, or under-current conditions.

DRV102 3

SBVS009B www.ti.com

CONNECTION DIAGRAMS

Top Front View TO-220, DDPAK Supply Voltage, VS.............................................................................. 60V

Input Voltage .......................................................................... –0.2V to VS

PWM Adjust Input ................................................ –0.2V to VS (24V max)

Delay Adjust Input ................................................ –0.2V to VS (24V max)

Operating Temperature Range ......................................–55°C to +125°C

Storage Temperature Range .........................................–55°C to +125°C

Junction Temperature.................................................................... +150°C

Lead Temperature (soldering, 10s)(2) ........................................... +300°C

NOTES: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may de-

grade device reliability. (2) Vapor-phase or IR reflow techniques are recom-

mended for soldering the DRV102F surface-mount package. Wave soldering

is not recommended due to excessive thermal shock and “shadowing” of

nearby devices.

ABSOLUTE MAXIMUM RATINGS(1)

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and

installation procedures can cause damage.

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes

could cause the device not to meet its published specifications.

7-Lead

Stagger-Formed

TO-220

NOTE: Tabs are electrically connected to ground (pin 4).

123456 7

7-Lead

DDPAK

Surface-Mount

PWM

Gnd Out

Delay

123456

Flag Gnd Out

Delay

In Flag

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.

DRV102

4SBVS009B

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PIN # NAME DESCRIPTION

Pin 1 Input The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above

the typical switching threshold, 1.7V. Below this level, the output is disabled. With no connection to the pin, the input level rises

to 3.4V. Input current is 20µA when driven high and 80µA with the input low. The input may be driven to the power supply (VS)

without damage.

Pin 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results

in a delay of approximately 15µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less

than 3µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 3V threshold comparator.

When the pin voltage is below 3V, the output device is 100% on. The PWM oscillator is not synchronized to the Input (pin 1),

so the first pulse may be extended by any portion of the programmed duty cycle.

Pin 3 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a 19kΩ resistor to ground. It is driven by a 200µA current source

(PWM) from VS. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage,

or output of a D/A converter. The active voltage range is from 0.55V to 3.7V to facilitate the use of single-supply control

electronics. At 0.56V (or RPWM = 4.4kΩ), duty cycle is near 90%. Swing to ground should be limited to no lower than 0.1V. PWM

frequency is a constant 24kHz.

Pin 4 Ground This pin is electrically connected to the package tab. It must be connected to system ground for the DRV102 to function. It

carries the 6.5mA quiescent current.

Pin 5 VSThis is the power supply pin. Operating range is +8V to +60V.

Pin 6 Out The output is the emitter of a power npn with the collector connected to VS. Low power dissipation in the DRV102 is obtained

by low saturation voltage and fast switching transitions. Rise time is less than 250ns, fall time depends on load impedance.

A flyback diode is (D1) needed with inductive loads to conduct the load current during the off cycle. The external diode should

be selected for low forward voltage. The internal clamp diode provides protection but should not be used to conduct load

currents. An additional diode (D2), located in series with Out pin, is required for inductive loads.

Pin 7 Flag Normally high (active low), the Flag signals either an over-temperature, over-current, or under-current fault. The over/under-

current flags are true only when the output is on (constant dc output or the “on” portion of PWM mode). A thermal fault (thermal

shutdown) occurs when the die surface reaches approximately 165°C and latches until the die cools to 150°C. Its output

requires a pull-up resistor. It can typically sink two milliamps, sufficient to drive a low-current LED.

PIN DESCRIPTIONS

LOGIC BLOCK DIAGRAM

PWM

Input

Off

Over/Under Current

DRV102

Flag

Thermal

Shutdown

PWM

(2)

Delay

Load

NOTES: (1) Schottky Power Rectifier for low

power dissipation. (2) Schottky or appropriately

rated silicon diode.

(+8V to +60V)

Gnd 4

Out

1(1)

DRV102 5

SBVS009B www.ti.com

TYPICAL PERFORMANCE CURVES

At TC = +25°C and VS = +24V, unless otherwise noted.

OUTPUT SATURATION VOLTAGE vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Saturation Voltage (V)

2.25

1.75

1.5

1.25

0.75

= 2A

= 1.5A

= 1A

= 0.1A

QUIESCENT CURRENT vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Quiescent Current (mA)

7.5

6.5

5.5

= +60V

= +8V

= +24V

DUTY CYCLE and DUTY CYCLE ERROR vs VOLTAGE

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

PWM

(V)

Duty Cycle (%)

Duty Cycle Error (%)

–2

–4

–6

–8

Duty Cycle

Error

= 0.1A

= 1A

= 0.1A to 1A

DUTY CYCLE vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Duty Cycle (%)

VS = +8V

RPWM = 25.5kΩ

VS = +24V

VS = +60V

CURRENT LIMIT vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Current Limit (mA)

3.25

2.75

2.5

2.25

= +60V, Load = 5Ω

= +24V, Load = 5Ω

= +8V, Load = 1Ω

UNDER-SCALE CURRENT vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Under-Scale Current (mA)

= +8V to +60V

DRV102

6SBVS009B

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TYPICAL PERFORMANCE CURVES (CONT)

At TC = +25°C and VS = +24V, unless otherwise noted.

OUT

FLAG OPERATION

OVER-CURRENT LIMIT

(VS = +60V, CD = 220pF, RPWM = 25.5kΩ, Load = 350mH || 47Ω)

FLAG OPERATION

UNDER-CURRENT

(VS = +60V, CD = 120pF, RPWM = 25.5kΩ, No Load)

0.5A

OUT

DC TO PWM MODE

DRIVING INDUCTIVE LOAD

(VS = +60V, CD = 120pF, RPWM = 30.1kΩ, Load = 350mH) TYPICAL SOLENOID CURRENT WAVEFORM

(VS = +60V, CD = 0.1µF, RPWM = 30.1kΩ, Load = 350mH)

50µs/div

Inductive load ramp current

50µs/div

60V

40V

20V

SUPPLY

PWM Mode

Constant Output

Flag only on during constant output

or “ON” portion of PWM mode

60V

40V

20V

FLAG

50µs/div

25ms/div

PWM Mode

60V

40V

20V

FLAG

Onset of current limit where

VOUT begins to drop

Flag only set during

constant output mode

or “ON” portion of

PWM mode

Solenoid Closure

{

Solenoid

Motion

Period

Solenoid Current

0.5A

10µs/div

CURRENT LIMIT REPSONSE

(Load = 1Ω, 2kΩ pull-up to +5V on Flag pin)

OSCILLATOR FREQUENCY vs TEMPERATURE

–75 –55 –35 –15 5 25 45 65 85 105 125

Temperature (°C)

Oscillator Frequency (kHz)

24.2

24.0

23.8

23.6

23.4

VS = +8V

VS = +60V

FLAG

2.5V

OUT

DRV102 7

SBVS009B www.ti.com

TYPICAL PERFORMANCE CURVES (CONT)

At TC = +25°C and VS = +24V, unless otherwise noted.

OUTPUT LEAKAGE CURRENT vs TEMPERATURE

–75 –55 –35 –15 5 25 45 65 85 105 125

Temperature (°C)

Leakage Current (µA)

–200

–175

–150

–125

–100

–75

Output Transistor Off

VO = 0V

VS = +60V

VS = +8V

VS = +24V

NOMINAL DELAY TIME TO PWM vs TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

Delay (ms)

103

101

CD = 0.1µF

VS = +8V

VS = +24V

VS = +60V

CURRENT LIMIT

PRODUCTION DISTRIBUTION

Percent of Units (%)

Current Limit (A)

Typical distribution

of packaged units.

DRV102F and

DRV102T included.

2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4

DELAY TIME TO PWM

PRODUCTION DISTRIBUTION

Percent of Units (%)

Delay Time to PWM (ms)

Typical distribution

of packaged units.

DRV102F and

DRV102T included.

CD = 0.1µF

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110

DUTY CYCLE ACCURACY

PRODUCTION DISTRIBUTION

Percent of Units (%)

Duty Cycle Accuracy (%)

Typical distribution

of packaged units.

DRV102F and

DRV102T included.

Nominal Duty Cycle = 49%

PWM

= 25.5kΩ

–7–6–5–4–3–2–101234567

DRV102

8SBVS009B

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BASIC OPERATION

The DRV102 is a high-side, bipolar power switch employ-

ing a pulse-width modulated (PWM) output for driving

electromechanical and thermal devices. Its design is opti-

mized for two types of applications: a two-state driver

(open/close) for loads such as solenoids and actuators, and

a linear driver for valves, positioners, heaters, and lamps. Its

wide supply range, adjustable delay to PWM mode, and

adjustable duty cycle make it suitable for a wide range of

applications. Figure 1 shows the basic circuit connections to

operate the DRV102. A 0.1µF bypass capacitor is shown

connected to the power supply pin.

The Input (pin 1) is compatible with standard TTL levels.

Input voltages between +2.2V and +5.5V turn the device

output on, while pulling the pin low (0V to +1.2V), shuts the

DRV102 output off. Input current is typically 80µA.

Delay Adjust (pin 2) and Duty Cycle Adjust (pin 3) allow

external adjustment of the PWM output signal. The Delay

Adjust pin can be left floating for minimum delay to PWM

mode (typically 15µs) or a capacitor can be used to set the

delay time. Duty cycle of the PWM output can be controlled

by a resistor, analog voltage, or D/A converter. Figure 1b

provides an example timing diagram with the Delay Adjust

FIGURE 1. Basic Circuit Connections and Timing Diagram.

pin connected to 0.1µF and duty cycle set for 25%. See the

“Delay Adjust” and “Duty Cycle Adjust” text for equations

and further explanation.

Ground (pin 4) is electrically connected to the package tab.

This pin must be connected to system ground for the

DRV102 to function. This serves as the DRV102 reference

ground.

The load (solenoid, valve, etc.) is connected between the

output (pin 6) and ground. For an inductive load, an external

flyback diode (D1 in Figure 1a) across the output is required.

The diode serves to maintain the hold force during PWM

operation. Depending on the application, the flyback diode

should be placed near the DRV102 or close to the solenoid

(see “Flyback Diode” text). The device’s internal clamp

diode, connected between the output and ground, should not

be used to carry load current. When driving inductive loads,

an additional diode in series with the out pin, D2, is required

(see “Series Diode” text).

The Flag (pin 7) provides fault status for under-current,

over-current, and thermal shutdown conditions. This pin is

active low with pin voltage typically +0.2V during a fault

condition. A small value capacitor may be needed between

Flag and ground for noisy applications.

RPWM

CDDelay

Adjust

Input

(TTL-Compatible)

Off

Thermal Shutdown

Over/Under Current

Flag

DRV102

Load

Duty

Cycle

Adjust

24kHz

Oscillator

PWM

Out

Gnd (Gnd electrically

connected to tab)

Delay

OUTPUT V

INPUT +2.2V to +5.5V

0V to +1.2V

Duty Cycle = = 25%

PWM

= 90.9kΩ

≈ 10.4µs

≈ 41.6µs (1/24kHz)

1a). Basic Circuit Connections

= 0.1µF (92ms constant dc output before PWM)

PWM

= 90.9kΩ

1b). Simplified Timing Diagram

(1)

= 0.1µF

92ms • • •

• • •

Initial dc Output

(set by value

of CD)

PWM Mode

(resistor or voltage

controlled)

NOTE: (1) External flyback diode required for inductive loads to conduct load current during the off cycle.

Flyback diode shown near DRV102. For some applications with remotely located load, it may be desirable

to place the diode near the solenoid—see “Flyback Diode” text. Motorola MSRS1100T3 (1A, 100V) or

MBRS360T3 (3A, 60V).

0.1µF

(+8V to +60V)

DRV102 9

SBVS009B www.ti.com

CONSTANT OUTPUT DURATION

(Delay Time to PWM Mode) CD

3µs Pin Connected to 5V

15µs Pin Open

97µs 100pF

0.97ms 1nF

97ms 0.1µF

APPLICATIONS INFORMATION

POWER SUPPLY

The DRV102 operates from a single +8V to +60V supply

with excellent performance. Most behavior remains un-

changed throughout the full operating voltage range. Param-

eters which vary significantly with operating voltage are

shown in the Typical Performance Curves.

CONNECTIONS TO LOAD

The PWM switching voltage and currents can cause electro-

magnetic radiation. Proper physical layout of the load cur-

rent will help minimize radiation. Load current flows from

the DRV102 output terminal to the load and returns through

the ground return path. This current path forms a loop. To

minimize radiation, make the area of the enclosed loop as

small as possible. Twisted pair leading to the load is excel-

lent. If the ground return current must flow through a chassis

ground, route the output current line directly over the chassis

surface in the most direct path to the load.

FLYBACK DIODE LOCATION

Physical location of the flyback diode may affect electro-

magnetic radiation. With most solenoid loads, inductance is

large enough that load current is virtually constant during

PWM operation. When the switching transistor is off, load

current flows though the flyback diode. If the flyback diode

is located near the DRV102 (Figure 2a), the current flowing

in long lines to the load is virtually constant. If the flyback

diode is, instead, located directly across the load (Figure 2b),

pulses of current must flow from the DRV102 to the distant

load. While theory seems to favor placing the diode at the

DRV102 output (constant current in the long lines), indi-

TABLE I. Delay Adjust Pin Connections.

vidual situations may defy logic; if one location seems to

create noise problems, try the other.

SERIES DIODE FOR INDUCTIVE LOADS

An additional bias diode, located in series with the output, is

required when driving inductive loads. Any silicon diode,

such as the 1N4002, appropriately rated for current will

work. The diode biases the emitter of the internal power

device such that it can be fully shut off during the “off”

portion of the PWM cycle. Note that the voltage at the load

drops below ground due to the flyback diode. If it is not used,

apparent leakage current can rise to hundreds of milliamps,

resulting in unpredictable operation and thermal shutdown.

ADJUSTABLE INITIAL 100% DUTY CYCLE

A unique feature of the DRV102 is its ability to provide an

initial constant dc output (100% duty cycle) and then switch

to PWM mode to save power. This function is particularly

useful when driving solenoids which have a much higher

pull-in current requirement than hold current requirement.

The duration of this constant dc output (before PWM output

begins) can be externally and independently controlled with

a capacitor connected from Delay Adjust (pin 2) to ground

according to the following equation:

Delay Time ≈ CD • 106

(time in seconds, CD in Farads)

Leaving the Delay Adjust pin open results in a constant

output time of approximately 15µs. The duration of this

initial output can be reduced to less than 3µs by connecting

the pin to 5V. Table I provides examples of desired “delay”

times (constant output before PWM mode) and the appropri-

ate capacitor values or pin connection.

FIGURE 2. Location of External Flyback Diode.

The internal Delay Adjust circuitry is composed of a 3µA

current source and a 3V comparator as shown in Figure 3.

Thus, when the pin voltage is less than 3V, the output device

is 100% on (dc output mode).

FIGURE 3. Simplified Circuit Model of the Delay Adjust Pin.

DRV102

Load

Out

2a) Flyback Diode Near DRV102

DRV102

Load

Out

2b) Flyback Diode Near Load

3µA

3V Reference

Comparator

Delay Adjust

DRV102

10 SBVS009B

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FIGURE 6. Simplified Circuit Model of the Duty Cycle

Adjust Pin.

FIGURE 5. Using a Voltage Source to Program Duty Cycle.

DRV102

D/A

Converter

(or analog

voltage)

1kΩ

(1)

PWM

3 Gnd 4

Out

NOTE: (1) Required if voltage source can go below 0.1V.

200µA

Comparator

Duty Cycle

Adjust

DRV102

19kΩ

Resistor or

Voltage Source

(1)

NOTE: (1) Do not drive pin below 0.1V.

3.8V

0.7V

f = 24kHz

ADJUSTABLE DUTY CYCLE

The DRV102’s externally adjustable duty cycle provides an

accurate means of controlling power delivered to the load.

Duty cycle can be set from 10% to 90% with an external

resistor, analog voltage, or the output of a D/A converter.

Reduced duty cycle results in reduced power dissipation.

This keeps the DRV102 and load cooler, resulting in in-

creased reliability for both devices. PWM frequency is a

constant 24kHz.

Resistor-Controlled Duty Cycle

Duty cycle is independently programmed with a resistor

(RPWM) connected between the Duty Cycle Adjust pin and

ground. Increased resistor values correspond to decreased

duty cycles. Table II provides resistor values for typical duty

cycles. Resistor values for additional duty cycles can be

obtained from Figure 4. For reference purposes, the equation

for calculating RPWM is included in Figure 4.

FIGURE 4. RPWM versus Duty Cycle.

RESISTOR(1) VOLTAGE(2)

DUTY CYCLE RPWM (kΩ)V

PWM (V)

10 536 3.67

20 137 3.31

30 66.5 2.91

40 39.2 2.49

50 24.9 2.07

60 16.2 1.66

70 10.5 1.26

80 6.65 0.88

90 4.42 0.56

NOTES: (1) Resistor values listed are nearest 1% standard values. (2) Do not

drive pin below 0.1V. For additional values, see “Duty Cycle vs Voltage” typical

performance curve.

TABLE II. Duty Cycle Adjust. TA= +25°C, VS = +24V.

Voltage-Controlled Duty Cycle

Duty cycle can also be programmed with an analog voltage,

VPWM. With VPWM ≈ 0.5V, duty cycle is 100%. Increasing

this voltage results in decreased duty cycles. For 0% duty

cycle, VPWM is approximately 4V. Table II provides VPWM

values for typical duty cycles. See the “Duty Cycle vs

Voltage” typical performance curve for additional duty cycle

values.

The Duty Cycle Adjust pin should not be driven below 0.1V.

If the voltage source used can go between 0.1V and ground,

a 1kΩ series resistor between the voltage source and the Duty

Cycle Adjust pin (Figure 5) is required to limit swing. If the

pin is driven below 0.1V, the output will be unpredictable.

The DRV102’s internal 24kHz oscillator sets the PWM

period. This frequency is not externally adjustable. Duty

Cycle Adjust (pin 3) is internally driven by a 200µA current

source and connects to the input of a comparator and a 19kΩ

resistor as shown in Figure 6. The DRV102’s PWM control

design is inherently monotonic. That is, a decreased voltage

(or resistor value) always produces an increased duty cycle.

10 20 40 60 10080

Duty Cycle (%)

RPWM (kΩ)

1000

100

RPWM = [ a + b (DC) + c (DC)2 + d (DC)3 + e (DC)4]–1

where: a = –4.9686 x 10–8

b = –5.9717 x 10–8

c = 2.9889 x 10–8

d = –5.4837 x 10–10

e = 5.9361 x 10–12

RPWM = [–4.9686 x 10–8 + (–5.9717 x 10–8) (50) + (2.9889 x 10–8) (50)2

+ (–5.4837 x 10–10) (50)3 + (5.9361 x 10–12) (50)4]–1

DC = duty cycle in %

For 50% duty cycle:

= 24.9kΩ

DRV102 11

SBVS009B www.ti.com

STATUS FLAG

Flag (pin 7) provides fault indication for under-current,

over-current, and thermal shutdown conditions. During a

fault condition, Flag output is driven low (pin voltage

typically drops to 0.2V). A pull-up resistor, as shown in

Figure 7, is required to interface with standard logic. A small

value capacitor may be needed between Flag and ground in

noisy applications.

Figure 7 gives an example of a non-latching fault monitoring

circuit, while Figure 8 provides a latching version. The Flag

pin can sink several milliamps, sufficient to drive external

logic circuitry or an LED (Figure 9) to indicate when a fault

has occurred. In addition, the Flag pin can be used to turn off

other DRV102’s in a system for chain fault protection.

Over/Under Current Fault

An over-current fault occurs when the output current ex-

ceeds the current limit. All units are guaranteed to drive 2A

without current limiting. Typically, units will limit at 2.7A.

The status flag is not latched. Since current during PWM

mode is switched on and off, the flag output will be modu-

lated with PWM timing (see flag waveforms in the Typical

Performance Curves).

An under-current fault occurs when the output current is

below the under-scale current threshold (typically 16mA).

For example, this function indicates when the load is discon-

nected. Again, the flag output is not latched, so an under-

current condition during PWM mode will produce a flag

output that is modulated by the PWM waveform. An initial,

brief under-current flag normally appears driving inductive

loads and may be avoided by adding a parallel resistor

sufficient to move the initial current above the under-current

threshold. Avoid adding capacitance to pin 6 (Out) as it may

cause momentary current limiting.

Over-Temperature Fault

A thermal fault occurs when the die reaches approximately

165°C, producing a similar effect as pulling the input low.

Internal shutdown circuitry disables the output and resets the

Delay Adjust pin. The Flag is latched in the low state (fault

condition) until the die has cooled to approximately 150°C.

A thermal fault can occur in any mode of operation. Recov-

ery from thermal fault will start in delay mode (constant dc

output).

FIGURE 8. Latching Fault Monitoring Circuit.

FIGURE 7. Non-Latching Fault Monitoring Circuit.

DRV102

Thermal Shutdown

Over/Under Current

Out

4Gnd

5kΩ

Pull-Up

+5V

Flag

TTL or HCT

DRV102

Thermal Shutdown

Over/Under Current 5

20kΩ

+5V

Flag

CLR

Flag

Flag Reset

CLK

GND K

74XX76A

(1)

NOTE: (1) Small capacitor (10pF) may be required in noisy environments.

4Gnd

Out

FIGURE 9. LED to Indicate Fault Condition.

DRV102

Thermal Shutdown

Over/Under Current

5kΩ

+5V

Flag

(LED)

HLMP-Q156

4Gnd

Out

DRV102

12 SBVS009B

www.ti.com

FIGURE 11. TO-220 Thermal Resistance versus Aluminum Plate Area.

For best thermal performance, the tab of the DDPAK sur-

face-mount version should be soldered directly to a circuit

board copper area. Increasing the copper area improves heat

dissipation. Figure 12 shows typical thermal resistance from

junction-to-ambient as a function of the copper area.

POWER DISSIPATION

Power dissipation depends on power supply, signal, and load

conditions. Power dissipation is equal to the product of

FIGURE 10. TO-220 and DDPAK Solder Footprints.

PACKAGE MOUNTING

Figure 10 provides recommended PCB layouts for both the

TO-220 and DDPAK power packages. The tab of both

packages is electrically connected to ground (pin 4). It may

be desirable to isolate the tab of TO-220 package from its

mounting surface with a mica (or other film) insulator (see

Figure 11). For lowest overall thermal resistance, it is best to

isolate the entire heat sink/DRV102 structure from the

mounting surface rather than to use an insulator between the

semiconductor and heat sink.

7-Lead DDPAK

(1)

KTW Package

(2)

7-Lead TO-220

KVT Package

(2)

0.335

0.15

0.05

0.45

0.51

0.105 0.05 0.035

0.04

0.2

0.085

Mean dimensions given in inches. Refer to the end of

this data sheet for tolerances and detailed package

drawings. For further information on solder pads for

surface-mount devices, consult Application Bulletin

AB-132 (SBFA015), available for download at

www.ti.com.

For improved thermal performance increase footprint area.

See Figure 11,

Thermal Resistance vs Circuit Board Copper Area

Refer to the mechanical drawings at the end of this document.

NOTES:(1)

(2)

012345678

Thermal Resistance

(°C/W)

Aluminum Plate Area (inches

)

THERMAL RESISTANCE

vs ALUMINUM PLATE AREA Aluminum Plate Area

Flat, Rectangular

Aluminum Plate

DRV102

TO-220 Package

0.030

0.062

0.050

Vertically Mounted

in Free Air

Optional mica or film insulator

for electrical isolation. Adds

approximately 1°C/W.

Aluminum Plate

Thickness (inches)

DRV102 13

SBVS009B www.ti.com

low as possible for increased reliability. Junction tempera-

ture can be determined according to the equation:

TJ = TA + PD

JA (1)

where,

JA =

JC +

CH +

HA (2)

TJ= Junction Temperature (°C)

TA= Ambient Temperature (°C)

PD= Power Dissipated (W)

JC = Junction-to-Case Thermal Resistance (°C/W)

CH = Case-to-Heat Sink Thermal Resistance (°C/W)

HA =

Heat Sink-to-Ambient Thermal Resistance (°C/W)

JA = Junction-to-Air Thermal Resistance (°C/W)

Figure 13 shows maximum power dissipation versus ambi-

ent temperature with and without the use of a heat sink.

Using a heat sink significantly increases the maximum

power dissipation at a given ambient temperature as shown.

FIGURE 12. DDPAK Thermal Resistance versus Circuit Board Copper Area.

THERMAL RESISTANCE vs

CIRCUIT BOARD COPPER AREA

Thermal Resistance, θJA (°C/W)

012345

Copper Area (inches2)

DRV102

DDPAK

Surface-Mount Package

1oz. copper

Circuit Board Copper Area

DRV102

DDPAK

Surface-Mount Package

output current times the voltage across the conducting out-

put transistor times the duty cycle. Power dissipation can be

minimized by using the lowest possible duty cycle necessary

to assure the required hold force.

THERMAL PROTECTION

Power dissipated in the DRV102 will cause the junction

temperature to rise. The DRV102 has thermal shutdown

circuitry that protects the device from damage. The thermal

protection circuitry disables the output when the junction

temperature reaches approximately +165°C, allowing the de-

vice to cool. When the junction temperature cools to approxi-

mately +150°C, the output circuitry is again enabled. Depend-

ing on load and signal conditions, the thermal protection

circuit may cycle on and off. This limits the dissipation of the

driver but may have an undesirable effect on the load.

Any tendency to activate the thermal protection circuit

indicates excessive power dissipation or an inadequate heat

sink. For reliable operation, junction temperature should be

limited to +125°C, maximum. To estimate the margin of

safety in a complete design (including heat sink), increase

the ambient temperature until the thermal protection is

triggered. Use worst-case load and signal conditions. For

good reliability, thermal protection should trigger more than

40°C above the maximum expected ambient condition of

your application. This produces a junction temperature of

125°C at the maximum expected ambient condition.

The internal protection circuitry of the DRV102 was designed

to protect against overload conditions. It was not intended to

replace proper heat sinking. Continuously running the

DRV102 into thermal shutdown will degrade reliability.

HEAT SINKING

Most applications will not require a heat sink to assure that

the maximum operating junction temperature (125°C) is not

exceeded. However, junction temperature should be kept as FIGURE 13. Maximum Power Dissipation versus Ambient

Temperature.

Power Dissipation (Watts)

0 255075100125

Ambient Temperature (°C)

MAXIMUM POWER DISSIPATION

vs AMBIENT TEMPERATURE

TO-220 with Thermalloy

6030B Heat Sink

= 16.5°C/W

PD = (TJ (max) – TA) /

TJ (max) = 125°C

With infinite heat sink

( JA = 3°C/W),

max PD = 33W

at TA = 25°C

DDPAK

= 26°C/W (3 in

1 oz.

copper mounting pad)

DDPAK or TO-220

= 65°C/W (no heat sink)

DRV102

14 SBVS009B

www.ti.com

The difficulty in selecting the heat sink required lies in

determining the power dissipated by the DRV102. For dc

output into a purely resistive load, power dissipation is simply

the load current times the voltage developed across the

conducting output transistor times the duty cycle. Other loads

are not as simple. Once power dissipation for an application

is known, the proper heat sink can be selected.

Heat Sink Selection Example

A TO-220 package’s maximum dissipation is 2 Watts. The

maximum expected ambient temperature is 80°C. Find the

proper heat sink to keep the junction temperature below

125°C.

Combining Equations 1 and 2 gives:

TJ = TA + PD(

JC +

CH +

HA)(3)

TJ, TA, and PD are given.

JC is provided in the Specifica-

tions table, 3°C/W.

CH can be obtained from the heat sink

manufacturer. Its value depends on heat sink size, area, and

material used. Semiconductor package type, mounting screw

torque, insulating material used (if any), and thermal

joint compound used (if any) also affect

CH. A typical

for a TO-220 mounted package is 1°C/W. Now we can solve

for

HA:

(4)

To maintain junction temperature below 125°C, the heat

sink selected must have a

HA less than 18.5°C/W. In other

words, the heat sink temperature rise above ambient must be

less than 37°C (18.5°C/W • 2W). For example, at 2 Watts

Thermalloy model number 6030B has a heat sink

temperature rise of about 33°C above ambient, which is

below the 37°C required in this example. Figure 13 shows

power dissipation versus ambient temperature for a TO-220

package with a 6030B heat sink.

Another variable to consider is natural convection versus

forced convection air flow. Forced-air cooling by a small fan

can lower

CA (

CH +

HA) dramatically. Heat sink manufac-

turers provide thermal data for both of these cases. For

additional information on determining heat sink require-

ments, consult Application Bulletin AB-038.

As mentioned earlier, once a heat sink has been selected, the

complete design should be tested under worst-case load and

signal conditions to ensure proper thermal protection.

θθθ

HA JA

DJC CH

()

=°°°+°

()

=°

––

125 C – 80 C

2W – 3 C/W 1 C/W 18.5 C/W

DRV102 15

SBVS009B www.ti.com

APPLICATION CIRCUITS

FIGURE 14. Fluid Flow Control System.

FIGURE 15. Instrument Light Dimmer Circuit. FIGURE 16. 4-20mA Input to PWM Output.

DRV102

Duty Cycle Adjust

Input

(On/Off)

Twisted Pair

Out

4-20mA

NOTE: (1) Rectifier diode required for inductive

loads to conduct load current during the off cycle.

100Ω

187Ω

Coil

(1)

Delay

Adjust

DRV102

Thermal Shutdown

Over/Under Current

24kHz

Oscillator

PWM

Delay

TTL Control Input

Off

Flexible Tube

Plunger

Pinch Valve

Solenoid Coil

Out

CDRPWM

34Gnd

Flag

Delay

Adjust

Duty Cycle

Adjust(1)

(10% to 90%)

Can drive most types

of solenoid-actuated

valves and actuators

NOTE: (1) Duty cycle can be programmed by

a resistor, analog voltage, or D/A converter.

Do not drive below 0.1V.

Microprocessor

+5V

5kΩ

DRV102

Lamp

Cadmium Sulfide

Optical Detector

(Clairex CL70SHL

or CLSP5M)

Aimed at

ambient

light

On/Off

Brighter light results in

increased duty cycle

Delay

Adjust

10kΩ

Out

DRV102

16 SBVS009B

www.ti.com

FIGURE 17. Improved Switching Time When Driving Multiple Loads.

DRV102

PWM

150kΩ

0.047µF

5+40V (max for TPIC6273)

(25% Duty Cycle)

Reduced mechanical actuation delay with high voltage pull-in followed by low duty cycle

Out

On/Off

Full power pulse width is control

plus interval set by CD.

+5V

5 6

TI TPIC6273

(Octal Power Switch)

TTL/CMOS Solenoid Selection Inputs

714 15 16 17

74LS05

Control

238912131819

• • •• • •

DRV102 17

SBVS009B www.ti.com

FIGURE 18. (a) Constant Temperature Controller. (b) Improved Accuracy Constant Temperature Controller.

On/Off

Thermistor

DRV102

REF200

Heating

Element

Duty Cycle

Adjust

Delay

Adjust 2

Gnd43

Out

0.1µF

2µF Film

100µA100µA

1kΩ

10kΩ

10MΩ

OPA134

IN4148

(1)

Thermistor

5kΩ at +25°C

20kΩ

4.7V

Integrator improves accuracy

NOTE: (1) Or any common silicon diode suited

to the mechanical mounting requirements.

Temperature

Control

Higher temperature results

in lower duty cycle.

Higher temperature results

in lower duty cycle.

7, 8

0.1µF

On/Off

DRV102

Heating

Element

Duty

Cycle

Adjust

Delay

Adjust

Gnd43

Out

10µF

DRV102

18 SBVS009B

www.ti.com

FIGURE 19. Constant Speed Motor Control.

FIGURE 20. DC Motor Speed Control Using AC Tachometer.

One-Shot

–15V 5nF

NP0

VFC32

0V to +10V

1kΩ

40kΩ

DRV102

100kΩ

470kΩ

Frequency In

22kΩ

47kΩ10kΩ

TAC

Tachometer

Coupled to Motor

+15V

0.5µF

1nF

2N2222

Speed Control Input

OUT

Delay Adjust

Open circuit will

provide 3.4V

“on” signal

+40V

DRV102

dc Tachometer

Coupled to Motor

R1R2

Speed Control(1)

NOTE: (1) Select R1/R2 ratio based on tachometer output voltage.

Input

(On/Off) 1

5+12V

Out

Delay

Adjust

DRV102 19

SBVS009B www.ti.com

FIGURE 22. Three-Phase Stepper Motor Driver Provides High-Stepping Torque.

FIGURE 23. Soft-Start Circuit for Incandescent Lamps and Other Sensitive Loads.

FIGURE 21. Constant Current Output Drive.

DRV102

VS = +8V to +60V

4.87kΩ

20µF

+4.3V

DIN5229

Duty Cycle Adjust

after soft start

Select R1 and R2 to divide

down VS to 5.5V max.

For example: with VS = 60V

R1 = 11kΩ, R2 = 1kΩ

VIN = • 60V = 5V

Sets start-up

duty cycle

1kΩ

1kΩ + 11kΩ

5VS

Out

Delay Adjust

DRV102 Phase 3

Stepper

Logic In

DRV102

Phase 2

Stepper

Logic In 6

5VS

DRV102

Phase 1

Stepper

Logic In 6

Motor

Only one DRV102 is

turned on at sequence time.

+24V

Off

Duty Cycle

Adjust

Delay

Adjust

Load

RSHUNT

0.1Ω

DRV102

Current Set

0.6V gives ~ 90% Duty Cycle

3.7V gives ~ 10% Duty Cycle

Out

2kΩ

100kΩ

25kΩ

5.1V

Zener

1kΩ

100kΩ

5kΩ

OPA237

0.1µF

DRV102

20 SBVS009B

www.ti.com

Revision History

DATE REVISION PAGE SECTION DESCRIPTION

1 Front Page Updated front page appearance.

12 Package Mounting Changed Figure 10 to show TI package designator.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

5/09 B

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

DRV102F OBSOLETE DDPAK KTW 7 TBD Call TI Call TI

DRV102F/500 ACTIVE DDPAK KTW 7 500 Green (RoHS &

no Sb/Br) CU SN Level-2-260C-1 YEAR

DRV102FKTWT ACTIVE DDPAK KTW 7 50 Green (RoHS &

no Sb/Br) CU SN Level-3-245C-168 HR

DRV102FKTWTG3 ACTIVE DDPAK KTW 7 50 Green (RoHS &

no Sb/Br) CU SN Level-3-245C-168 HR

DRV102T ACTIVE TO-220 KVT 7 50 Green (RoHS &

no Sb/Br) CU SN N / A for Pkg Type

DRV102TG3 ACTIVE TO-220 KVT 7 50 Green (RoHS &

no Sb/Br) CU SN N / A for Pkg Type

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Aug-2009

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DRV102FKTWT DDPAK KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DRV102FKTWT DDPAK KTW 7 50 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MPSF015 – AUGUST 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT

0.010 (0,25) AM

4201284/A 08/01

0.385 (9,78)

0.410 (10,41)

–A– 0.006

–B–

0.170 (4,32)

0.183 (4,65)

0.000 (0,00)

0.012 (0,305)

0.104 (2,64)

0.096 (2,44)

0.034 (0,86)

0.022 (0,57)

0.050 (1,27)

0.055 (1,40)

0.045 (1,14)

0.014 (0,36)

0.026 (0,66)

0.330 (8,38)

0.370 (9,40)

0.297 (7,54)

0.303 (7,70)

0.0585 (1,485)

0.0625 (1,587)

0.595 (15,1 1)

0.605 (15,37)

0.019 (0,48)

0.017 (0,43)

0°~3°

0.179 (4,55)

0.187 (4,75)

0.056 (1,42)

0.064 (1,63)

0.296 (7,52)

0.304 (7,72)

0.300 (7,62)

0.252 (6,40)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Lead width and height dimensions apply to the

plated lead.

D. Leads are not allowed above the Datum B.

E. Stand–off height is measured from lead tip

with reference to Datum B.

F. Lead width dimension does not include dambar

protrusion. Allowable dambar protrusion shall not

cause the lead width to exceed the maximum

dimension by more than 0.003”.

G. Cross–hatch indicates exposed metal surface.

H. Falls within JEDEC MO–169 with the exception

of the dimensions indicated.

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