1
Single and Dual Single Supply Ultra-Low Noise, Low
Distortion Rail-to-Rail Output, Op Amp
ISL28191, ISL28291
The ISL28191 and ISL28291 are tiny single and dual ultra-low
noise, ultra-low distortion operational amplifiers. They are fully
specified to operate down to +3V single supply. These
amplifiers have outputs that swing rail-to-rail and an input
common mode voltage that extends to ground (ground
sensing).
The ISL28191 and ISL28291 are unity gain stable with an
input referred voltage noise of 1.7nV/Hz. Both parts feature
0.00018% THD+N at 1kHz.
The ISL28191 is available in the space-saving 6 Ld UTDFN
(1.6mmx1.6mm) and 6 Ld SOT-23 packages. The ISL28291 is
available in the 8 Ld SOIC, 10 Ld 1.8mmx1.4mm UTQFN and
10 Ld MSOP packages. All devices are guaranteed over -40°C
to +125°C.
Features
•1.7nV/Hz input voltage noise at 1kHz
1kHz THD+N typical 0.00018% at 2VP-P VOUT
Harmonic Distortion -76dBc, -70dBc, fo = 1MHz
61MHz -3dB bandwidth
630µV maximum offset voltage
3µA input bias current
100dB typical CMRR
3V to 5.5V single supply voltage range
Rail-to-rail output
•Ground Sensing
Enable pin (not available in the 8 Ld SOIC package option)
Pb-free (RoHS compliant)
Applications
Low noise signal processing
Low noise microphones/preamplifiers
•ADC buffers
DAC output amplifiers
Digital scales
Strain gauges/sensor amplifiers
Radio systems
Portable equipment
Infrared detectors
Related Literature
AN1343: ISL2829xEVAL1Z, ISL5529xEVAL1Z Evaluation
Board User’s Guide
Ordering Information
PART NUMBER
(Note 5)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL28191FHZ-T7 (Notes 1, 2) GABJ 6 Ld SOT-23
(Note 4)
P6.064A
ISL28191FRUZ-T7 (Notes 1, 3) M8 6 Ld UTDFN L6.1.6x1.6A
ISL28291FUZ (Note 2) 8291Z 10 Ld MSOP M10.118A
ISL28291FUZ-T7 (Notes 1, 2) 8291Z 10 Ld MSOP M10.118A
ISL28291FBZ (Note 2) 28291 FBZ 8 Ld SOIC M8.15E
ISL28291FBZ-T7 (Notes 1, 2) 28291 FBZ 8 Ld SOIC M8.15E
ISL28291FRUZ-T7 (Notes 1, 3) F 10 Ld UTQFN L10.1.8x1.4A
ISL28191EVAL1Z Evaluation Board
ISL28291EVAL1Z Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-
free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
4. The part marking is located on the bottom of the part.
5. For Moisture Sensitivity Level (MSL), please see device information
page for ISL28191, ISL28291. For more information on MSL please
see techbrief TB363.
January 26, 2012
FN6156.9
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2006-2008, 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28191, ISL28291
2FN6156.9
January 26, 2012
Pin Configurations
ISL28191
(6 LD SOT-23)
TOP VIEW
ISL28191
(6 LD 1.6X1.6X0.5 UTDFN)
TOP VIEW
ISL28291
(8 LD SOIC)
TOP VIEW
ISL28291
(10 LD MSOP)
TOP VIEW
ISL28291
(10 LD UTQFN)
TOP VIEW
1
2
3
6
4
5
-+
OUT
V-
IN+
V +
IN-
EN
1
2
3
6
4
5
OUT
IN-
IN+
V+
EN
V-
-+
1
2
3
4
8
7
6
5
OUT_A
IN-_A
IN+_A
V-
V+
OUT_B
IN-_B
IN+_B
-
+
-
+
1
2
3
4
10
9
8
7
5 6
OUT_A
IN-_A
IN+_A
V-
V+
OUT_B
IN-_B
IN+_B
EN_A EN_B
-
+
7
-
+
IN+_B
IN-_B
OUT_B
V+
OUT_A
V-
EN_A
EN_B
IN+_A
IN-_A
6
7
8
9
10
543
2
1
-
+
-
+
ISL28191, ISL28291
3FN6156.9
January 26, 2012
Pin Descriptions
ISL28191
(6 Ld SOT-23)
ISL28191
(6 Ld UTDFN)
ISL28291
(8 Ld SOIC)
ISL28291
(10 Ld MSOP)
ISL28291
(10 Ld UTQFN)
PIN
NAME FUNCTION EQUIVALENT CIRCUIT
42
2 (A)
6 (B)
2 (A)
8 (B)
1 (A)
7 (B)
IN-
IN-_A
IN-_B
Inverting input
Circuit 1
33
3 (A)
5 (B)
3 (A)
7 (B)
2 (A)
6 (B)
IN+
IN+_B
IN+_B
Non-inverting
input
(See circuit 1)
2 4 4 4 3 V- Negative supply
11
1 (A)
7 (B)
1 (A)
9 (B)
10 (A)
8 (B)
OUT
OUT_A
OUT_B
Output
Circuit 2
6 6 8 10 9 V+ Positive supply
55N/A
5 (A)
6 (B)
4 (A)
5 (B)
EN
EN_A
EN_B
Enable BAR
pin internal
pull-down; Logic
“1” selects the
disabled state;
Logic “0” selects
the enabled
state. Circuit 3
IN+IN-
V+
V-
V+
V-
OUT
EN
V+
V-
ISL28191, ISL28291
4FN6156.9
January 26, 2012
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200V
Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V
Thermal Resistance (Typical, Note 6) θJA (°C/W)
6 Ld SOT-23 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
6 Ld UTDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10 Ld UTQFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications V+ = 5.0V, V- = GND, RL = Open, RF = 1kΩ, AV = -1 unless otherwise specified. Parameters are per
amplifier. Typical values are at V+= 5V, TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 7) TYP
MAX
(Note 7) UNIT
DC SPECIFICATIONS
VOS Input Offset Voltage 270 630
840
µV
Input Offset Drift vs Temperature Figure 21 3.1 µV/°C
IIO Input Offset Current 35 500
900
nA
IBInput Bias Current 36
7
µA
CMIR Common-Mode Input Range 03.8V
CMRR Common-Mode Rejection Ratio VCM = 0V to 3.8V 78 100 dB
PSRR Power Supply Rejection Ratio VS = 3V to 5V 74 80 dB
AVOL Large Signal Voltage Gain VO = 0.5V to 4V, RL = 1kΩ90
86
98 dB
VOUT Maximum Output Voltage Swing Output low, RL = 1kΩ20 50
80
mV
Output high, RL = 1kΩ, V+ = 5V 4.95
4.92
4.97 V
IS,ON Supply Current per Amplifier, Enabled 2.6 3.5
3.9
mA
IS,OFF Supply Current per Amplifier, Disabled 26 35
48
µA
IO+ Short-Circuit Output Current RL = 10Ω95
90
130 mA
IO- Short-Circuit Output Current RL = 10Ω95
90
130 mA
VSUPPLY Supply Operating Range V+ to V- 3 5.5 V
ΔVOS
ΔT
--------------
ISL28191, ISL28291
5FN6156.9
January 26, 2012
VENHEN High Level Referred to V- 2 V
VENLEN Low Level Referred to V- 0.8 V
IENHEN Pin Input High Current VEN = V+ 0.8 1.1
1.3
µA
IENLEN Pin Input Low Current VEN = V- 20 80
100
nA
AC SPECIFICATIONS
GBW -3dB Unity Gain Bandwidth RF = 0Ω, CL = 20pF, AV = 1, RL = 10kΩ61 MHz
THD+N Total Harmonic Distortion + Noise f = 1kHz. VOUT + 2VP-P, AV = +1, RL = 10kΩ0.0001
8
%
HD
(1MHz)
2nd Harmonic Distortion 2VP-P output voltage, AV = 1 -76 dBc
3rd Harmonic Distortion -70 dBc
ISO Off-state Isolation
fO = 100kHz
AV = +1, VIN = 100mVP-P
, RF = 0Ω
CL = 20pF, AV = 1, RL = 10kΩ
-38 dB
X-TALK
ISL28291
Channel-to-Channel Crosstalk
fO = 100kHz
VS = ±2.5V, AV = +1, VIN = 1VP-P,
RF = 0Ω, CL = 20pF, AV = 1, RL = 10kΩ
-105 dB
PSRR Power Supply Rejection Ratio
fO = 100kHz
VS = ±2.5V, AV = +1, VSOURCE = 1VP-P
,
RF = 0Ω, CL = 20pF, AV = 1, RL = 10kΩ
-70 dB
CMRR Common Mode Rejection Ratio
fO = 100kHz
VS = ±2.5V, AV = +1, VCM = 1VP-P,
RF = 0Ω, CL = 20pF, AV = 1, RL = 10kΩ
-65 dB
enInput Referred Voltage Noise fO = 1kHz 1.7 nV/Hz
inInput Referred Current Noise fO = 1kHz 1.8 pA/Hz
TRANSIENT RESPONSE
SR Slew Rate 12
12
17 V/µs
tr, tf, Small
Signal
Rise Time, tr 10% to 90% AV = 1, VOUT = 0.1VP-P, RL = 10kΩ, CL = 1.2pF 7ns
Fall Time, tf 90% to 10% 12 ns
tr, tf Large Signal Rise Time, tr 10% to 90% AV = 2, VOUT = 1VP-P; RL = 10kΩ,
RF /RG = 499Ω/499Ω, CL = 1.2pF
44 ns
Fall Time, tf 90% to 10% 50 ns
Rise Time, tr 10% to 90% AV = 2, VOUT = 4.7VP-P; RL = 10kΩ,
RF /RG = 499Ω/499Ω, CL = 1.2pF
190 ns
Fall Time, tf 90% to 10% 190 ns
tEN ENABLE to Output Turn-on Delay Time;
10% EN - 10% VOUT
AV = 1, VOUT = 1VDC, RL = 10kΩ, CL = 1.2pF 330 ns
ENABLE to Output Turn-off Delay
Time; 10% EN - 10% VOUT
AV = 1, VOUT = 0VDC, RL = 10kΩ, CL = 1.2pF 50 ns
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications V+ = 5.0V, V- = GND, RL = Open, RF = 1kΩ, AV = -1 unless otherwise specified. Parameters are per
amplifier. Typical values are at V+= 5V, TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 7) TYP
MAX
(Note 7) UNIT
ISL28191, ISL28291
6FN6156.9
January 26, 2012
Typical Performance Curves
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD
FIGURE 3. -3dB BANDWIDTH vs VOUT FIGURE 4. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FIGURE 5. INPUT IMPEDANCE vs FREQUENCY FIGURE 6. DISABLED OUTPUT IMPEDANCE vs FREQUENCY
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
10k 100k 1M 10M 100M
FREQUENCY (Hz)
CLOSED LOOP GAIN (dB)
RL = 100k
V+ = 5V
AV = +1
CL = 10pF
VOUT = 10mVP-P
RL = 10k
RL = 1k
RL = 100
-10
-8
-6
-4
-2
0
2
4
6
8
10
10k 100k 1M 10M 100M
CL = 20pF
CL = 10pF
CL = 32pF
CL = 57pF
CL = 57pF
CL = 110pF
CLOSED LOOP GAIN (dB)
V+ = 5V
AV = +1
RL = 10kΩ
VOUT = 10mVP-P
FREQUENCY (Hz)
-7
-6
-5
-4
-3
0
-2
-1
1
2
10k 100k 1M 10M 100M
FREQUENCY (Hz)
CLOSED LOOP GAIN (dB)
V+ = 5V
AV = +1
RL = 10kΩ
CL = 10pF
-8
VOUT = 10mVP-P
VOUT = 100mVP-P
V
OUT
= 1V
P-P
VOUT = 1mVP-P
-10
0
10
20
30
40
50
60
70
10k 100k 1M 10M 100M
FREQUENCY (Hz)
GAIN (dB)
V+ = 5V
RL = 10k
VOUT = 100mVP-P
AV = 10, RF = 4.42k, RG = 499
AV = 100, RF = 49.9k,
AV = 1, RF = 0, RG = INF
AV = 1000, RF = 499k, RG = 499
RG = 499
100
1k
10k
100k
1M
10k 100k 1M 10M 100M
V+ = 5V, 3V
INPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
ENABLED AND
DISABLED
VSOURCE = 1VP-P
100
1k
10k
100k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
V+ = 5V, 3V
VSOURCE = 1VP-P
ISL28191, ISL28291
7FN6156.9
January 26, 2012
FIGURE 7. ENABLED OUTPUT IMPEDANCE vs FREQUENCY FIGURE 8. CMRR vs FREQUENCY
FIGURE 9. PSRR vs FREQUENCY FIGURE 10. OFF ISOLATION vs FREQUENCY
FIGURE 11. CHANNEL TO CHANNEL CROSSTALK vs FREQUENCY FIGURE 12. THD+N vs FREQUENCY
Typical Performance Curves (Continued)
FREQUENCY (Hz)
0.10
1
10
100
10k 100k 1M 10M 100M
OUTPUT IMPEDANCE (Ω)
V+ = 5V, 3V
VSOURCE = 1V
VSOURCE = 0.1V
CMRR (dB)
-20
-40
-60
-80
-100
-10
-30
-50
-70
-90
1k 10k 1M
FREQUENCY (Hz)
100k 100M10M
0
10
V+ = 5V
AV = +1
RL = 10kΩ
CL = 10pF
VOUT = 100mVP-P
PSRR (dB)
FREQUENCY (Hz)
-20
-40
-60
-80
-100
-10
-30
-50
-70
-90
1k 10k 1M100k 100M10M
0
10
PSRR+
PSRR+
PSRR-
V+ = 5V
AV = +1
RL = 10kΩ
CL = 10pF
VOUT = 100mVP-P
-80
-70
-60
-50
-40
-30
-20
-10
0
10k 100k 1M 10M 100M 1G
VP-P = 10mV
VP-P = 1V
VP-P = 100mV
OFF ISOLATI ON (d B)
V+ = 5V
AV = +1
RL = 10kΩ
CL = 10pF
FREQUENCY (Hz)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
10k 100k 1M 10M 100M 1G
VP-P = 1V
CROSSTALK (dB)
FREQUENCY (Hz)
0.0001
0.001
0.01
0.1
0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
FREQUENCY (Hz)
THD + NOISE (%)
V+ = 5V
RL = 10k
RF = 0, AV = 1
400Hz TO 22kHz FILTER
VOUT = 2VP-P
ISL28191, ISL28291
8FN6156.9
January 26, 2012
FIGURE 13. THD+N @ 1kHz vs VOUT FIGURE 14. INPUT REFERRED NOISE VOLTAGE vs FREQUENCY
FIGURE 15. INPUT REFERRED NOISE CURRENT vs FREQUENCY FIGURE 16. ENABLE/DISABLE TIMING
FIGURE 17. SMALL SIGNAL STEP RESPONSE FIGURE 18. LARGE SIGNAL (1V) STEP RESPONSE
Typical Performance Curves (Continued)
0.0001
0.001
0.01
0.1
1
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOUT (VP-P)
THD +NOISE (%)
V+ = 5V
AV = +1
RL = 10kΩ
FREQUENCY = 1kHz
FILTER = 400Hz TO 22kHz
1 10 100 1k 10k
FREQUENCY (Hz)
INPUT VOLTAGE NOISE (nV/
Hz)
10
100k
0.1
1
CURRENT NOISE (pA/Hz)
1 10 100 1k 10k
FREQUENCY (Hz)
100k0.1
1
10
100
0
1
2
3
4
5
-1 0 1 2 3 4
EN INPUT
OUTPUT
VOLTS (V)
TIME (µs)
V+ = 5V
AV = +1
RL = 10kΩ
CL = 10pF
VIN = 1VDC
ENABLEDISABLEENABLE
SMALL SIGNAL (V)
TIME (ns)
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0 20 40 60 80 100 120 140 160 180 200
VIN
VOUT
V+ = ±2.5V
AV = +1
RL = 10kΩ
VOUT = 100mVP-P
LARGE SIGNAL (V)
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
TIME (ns)
0 100 200 300 400 500 600 700 800
VIN
VOUT
V+ = ±2.5V
AV = +2
RF = RG = 499Ω
RL = 10kΩ
VOUT = 1VP-P
ISL28191, ISL28291
9FN6156.9
January 26, 2012
FIGURE 19. LARGE SIGNAL (4.7V) STEP RESPONSE FIGURE 20. SUPPLY CURRENT vs TEMPERATURE,
VS = ±2.5V ENABLED, RL = INF
FIGURE 21. VOS vs TEMPERATURE, VS = ±2.5V FIGURE 22. IBIAS+ vs TEMPERATURE, VS = ±2.5V
FIGURE 23. IBIAS- vs TEMPERATURE, VS = ±2.5V FIGURE 24. IIO vs TEMPERATURE, VS = ±2.5V
Typical Performance Curves (Continued)
LARGE SIGNAL (V)
-3
-2
-1
0
1
2
3
0 400 800 1200 1600 2000
VIN
VOUT
V+ = ±2.5V
AV = +2
RF = RG = 499Ω
RL = 10kΩ
VOUT = 4.7VP-P
TIME (ns)
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
CURRENT (mA)
n = 100
MEDIAN
MIN
MAX
-200
-100
0
100
200
300
400
500
600
700
800
-40-200 20406080100120
TEMPERATURE (°C)
VOS (µV)
n = 100
MEDIAN
MIN
MAX
-4.6
-4.4
-4.2
-4.0
-3.8
-3.6
-3.4
-3.2
-3.0
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
IBIAS+ (µA)
n = 100
MEDIAN
MIN
MAX
-5.0
-4.8
-4.6
-4.4
-4.2
-4.0
-3.8
-3.6
-3.4
-3.2
-3.0
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
IBIAS- (µA)
n = 100
MEDIAN
MIN
MAX
-400
-200
0
200
400
600
800
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
IIO (nA)
n = 100
MEDIAN
MIN
MAX
ISL28191, ISL28291
10 FN6156.9
January 26, 2012
FIGURE 25. CMRR vs TEMPERATURE, VCM = 3.8V,
VS = ±2.5V
FIGURE 26. PSRR vs TEMPERATURE ±1.5V TO ±2.5V
FIGURE 27. POSITIVE VOUT vs TEMPERATURE, RL = 1k
VS2.5V
FIGURE 28. NEGATIVE VOUT vs TEMPERATURE, RL = 1k
VS= ±2.5V
FIGURE 29. INPUT COMMON MODE VOLTAGE vs TEMPERATURE
Typical Performance Curves (Continued)
70
80
90
100
110
120
130
140
150
160
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
CMRR (dB)
n = 100
MEDIAN
MIN
MAX
70
72
74
76
78
80
82
-40-200 20406080100120
TEMPERATURE (°C)
PSRR (dB)
n = 100
MEDIAN
MIN
MAX
4.960
4.965
4.970
4.975
4.980
4.985
4.990
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
VOUT (V)
n = 100
MEDIAN
MIN
MAX
10
15
20
25
30
35
40
45
50
55
60
-40-200 20406080100120
TEMPERATURE (°C)
VOUT (mV)
n = 100
MEDIAN
MIN
MAX
0.2
0.4
0.6
0.8
1.0
1.2
-0.8
-0.6
-0.4
-0.2
0
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
INPUT VOLTAGE TO THE POSITIVE RAIL (V+ - VCM)
INPUT VOLTAGE TO THE NEGATIVE RAIL (V- + VCM)
VCM OVERHEAD TO SUPPLY RAILS (V)
ISL28191, ISL28291
11 FN6156.9
January 26, 2012
Applications Information
Product Description
The ISL28191 and ISL28291 are voltage feedback operational
amplifiers designed for communication and imaging applications
requiring low distortion, very low voltage and current noise. Both
parts feature high bandwidth while drawing moderately low supply
current. They use a classical voltage-feedback topology, which
allows them to be used in a variety of applications where current-
feedback amplifiers are not appropriate because of restrictions
placed upon the feedback element used with the amplifier.
Enable/Power-Down
The ISL28191 and ISL28291 amplifiers are disabled by applying
a voltage greater than 2V to the EN pin, with respect to the V- pin.
In this condition, the output(s) will be in a high impedance state
and the amplifier(s) current will be reduced to 13µA/Amp. By
disabling the part, multiple parts can be connected together as a
MUX. The outputs are tied together in parallel and a channel can
be selected by the EN pin. The EN pin also has an internal pull-
down. If left open, the EN pin will pull to the negative rail and the
device will be enabled by default.
Input Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. Both parts have
additional back-to-back diodes across the input terminals (as
shown in Figure 30). In pulse applications where the input Slew
Rate exceeds the Slew Rate of the amplifier, the possibility exists
for the input protection diodes to become forward biased. This can
cause excessive input current and distortion at the outputs. If
overdriving the inputs is necessary, the external input current must
never exceed 5mA. An external series resistor may be used to limit
the current, as shown in Figure 30.
Using Only One Channel
The ISL28291 is a dual channel op amp. If the application only
requires one channel when using the ISL28291, the user must
configure the unused channel to prevent it from oscillating.
Oscillation can occur if the input and output pins are floating. This
will result in higher than expected supply currents and possible
noise injection into the channel being used. The proper way to
prevent this oscillation is to short the output to the negative input
and ground the positive input (as shown in Figure 31).
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit board
layout is necessary for optimum performance. Low impedance
ground plane construction is essential. Surface mount
components are recommended, but if leaded components are
used, lead lengths should be as short as possible. The power
supply pins must be well bypassed to reduce the risk of
oscillation. The combination of a 4.7µF tantalum capacitor in
parallel with a 0.01µF capacitor has been shown to work well
when placed at each supply pin.
For good AC performance, parasitic capacitance should be kept
to a minimum, especially at the inverting input. When ground
plane construction is used, it should be removed from the area
near the inverting input to minimize any stray capacitance at that
node. Carbon or Metal-Film resistors are acceptable with the
Metal-Film resistors giving slightly less peaking and bandwidth
because of additional series inductance. Use of sockets,
particularly for the SOIC package, should be avoided if possible.
Sockets add parasitic inductance and capacitance, which will
result in additional peaking and overshoot.
Current Limiting
The ISL28191 and ISL28291 have no internal current-limiting
circuitry. If the output is shorted, it is possible to exceed the
Absolute Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device. This is why the
output short circuit current is specified and tested with RL = 10Ω.
FIGURE 30. LIMITING THE INPUT CURRENT TO LESS THAN 5mA
-
+
R
FIGURE 31. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
ISL28191, ISL28291
12
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6156.9
January 26, 2012
For additional products, see www.intersil.com/product_tree
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load and power-supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related in Equation 1:
where:
•P
DMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
•PD
MAX for each amplifier can be calculated in Equation 2:
where:
•T
MAX = Maximum ambient temperature
θJA = Thermal resistance of the package
•PD
MAX = Maximum power dissipation of 1 amplifier
•V
S = Supply voltage
•I
MAX = Maximum supply current of 1 amplifier
•V
OUTMAX = Maximum output voltage swing of the application
•R
L = Load resistance
TJMAX TMAX θJAxPDMAXTOTAL
()+= (EQ. 1)
PDMAX 2*VSISMAX VS
( - VOUTMAX )VOUTMAX
RL
------------------------
×+×=
(EQ. 2)
ISL28191, ISL28291
13 FN6156.9
January 26, 2012
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28191,ISL28291
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE REVISION CHANGE
January 18, 2012 FN6156.9 Page 1 - Ordering Information Update:
Added Eval Board ISL28191EVAL1Z
Changed micro TDFN and TQFN to Ultra matching POD Description
Added SOT-23 Note
Page 10 - Typical Performance Curves:
Added Figure 29 - INPUT COMMON MODE VOLTAGE vs TEMPERATURE
ISL28191, ISL28291
14 FN6156.9
January 26, 2012
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.60
0.08-0.20
SEE DETAIL X
(0.60)
0-3°
3 5
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW END VIEW
INDEX AREA
PIN 1
SEATING PLANE GAUGE
0.45±0.1
(2 PLCS)
10° TYP
4
1.90
0.40 ±0.05
2.90
0.95
2.80
0.05-0.15
1.14 ±0.15
0.20 CA-B DM
(1.20)
(0.60)
(0.95)
(2.40)
0.10 C
1.45 MAX
C
B
AD
3
3
0.20 C
(1.90)
2x
0.15 C
2x D
0.15 C
2x A-B
(0.25)
H
64
5
5
13
2
PLANE
Dimension is exclusive of mold flash, prot rusions or gate burrs.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
Foot length is measured at reference to guage plane.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
6.
3.
5.
4.
2.
Dimensions are in mill imeters.1.
NOTES:
ISL28191, ISL28291
15 FN6156.9
January 26, 2012
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
B
D
A
E
0.15 C
2X
PIN 1
TOP VIEW
0.15 C
2X
REFERENCE
DETAIL A
0.10 C
0.08 C
6X
A3 C
SEATING
PLANE
L
e
46
31
BOTT OM VIEW
SIDE VIEW
0.10 CAB
b6X
DETAIL A
0.127 +0.058
A1
A1
A
0.127±0.008
64
13
M
CO.2
1.00 REF
D2
DAP SIZE 1.30 x 0.76
E2
-0.008
TERMINAL THICKNESS
0.30
1.00 0.45
0.50
0.25
1.25
2.00
1.00
LAND PATTERN
6
L6.1.6x1.6A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A
0.45 0.50 0.55
-
A1
- - 0.05
-
A3
0.127 REF
-
b
0.15 0.20 0.25
-
D
1.55 1.60 1.65
4
D2 0.40 0.45 0.50 -
E
1.55 1.60 1.65
4
E2
0.95 1.00 1.05
-
e
0.50 BSC
-
L
0.25 0.30 0.35
-
Rev. 1 6/06
NOTES:
1. Dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.
3. Warpage shall no t exceed 0.10mm.
4. Package length/package width are considered as special
characteristics.
5. JEDEC Reference MO-229.
6. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
ISL28191, ISL28291
16 FN6156.9
January 26, 2012
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”
ISL28191, ISL28291
17 FN6156.9
January 26, 2012
Package Outline Drawing
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
JEDEC reference MO-255.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
0.08
SEATING PLANE
0.10 C
C
C
SEE DETAIL "X"
MAX. 0.55
0 .1 27 REF
0-0.05
C
2X
0.10
1.40
1.80
BA
67
1
5
6X 0.40
C
C
4
0.10 M
MAB
0.70
PIN #1 ID
2
10
INDEX AREA
PIN 1 0.50
10X 0.20
6
6
4X 0.30
0.05
1
3
8
9 X 0.40
67
1
5
(6X 0.40)
(0.70)
10 (0.70)
(10X 0.20)
(4X 0.30)
3
8
(9 X 0.60)
PACKAGE OUTLINE
ISL28191, ISL28291
18 FN6156.9
January 26, 2012
Package Outline Drawing
M10.118A (JEDEC MO-187-BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions “D” and “E1” are measured at Datum Plane “H”.
This replaces existing drawing # MDP0043 MSOP10L.
Plastic interlead protrusions of 0.25mm max per side are not
Dimensioning and tolerancing conform to AMSE Y14.5m-1 994.
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW 1
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
Gauge
Plane
3°±3°
0.25
0.25 CAB
A
B
0.10C
0.08 CAB
0.55 ± 0.1 5
0.95 BSC
0.18 ± 0.05
1.10 Max
C
H
5.80
3.00
4.40
0.50
0.30
1.40
PIN# 1 ID
1 2
10 DETAIL "X"
SEATING PLANE
0.5 BSC
0.23 +0.07/ -0.08
3.0 ± 0.1
4.9 ± 0.15
3.0 ± 0.1
0.10 ± 0.05
0.86 ± 0.09
SIDE VIEW 2
included.
included.