34 .80 7IRELESS IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. ) s t( Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of the last page "(c) STMicroelectronics 200x - All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". c u d e t le o r P Web site - http://www.st.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices is found at http://www.stnwireless.com under Contacts. o s b O - If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ) s ( ct ST-NXP Wireless u d o r P e t e l o s b O 34 .80 7IRELESS www.stnwireless.com 34 .80 7IRELESS E-STLC2416 BluetoothTM baseband with integrated flash Not For New Design Features Pin-to-pin compatible with the previous version STLC2415 Ericsson Technology Licensing Baseband Core (EBC) BluetoothTM specification compliance: V1.1 and V1.2 LFBGA120 (10x10x1.4mm) SW compatible with STLC2411-M28R400CT combination Low power architecture with 2 different low power levels: sleep mode and deep sleep mode HW support for packet types 2 layer class 4 PCB compatible Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (ACL) logical transport link Synchronous Connection Oriented (SCO) links: 2 simultaneous SCO channels Supports Pitch-period Error Concealment (PPEC) - Improves speech quality in the vicinity of interference - Improves coexistence with WLAN - Works at receiver, no Bluetooth implication Communication interfaces - Synchronous serial interface supporting up to 32 bit data and different industry standards - Two enhanced 16550 UARTs - 12 Mbps USB interface - Fast master I2C bus interface - Multi slot PCM interface - 16 programmable GPIOs - 2 external interrupts and various interrupt possibilities through other interfaces (s) t c u r P e Faster connection: interlaced scan for page and inquiry scan, first FHS without random backoff, RSSI used to limit range Extended SCO (eSCO) links Standard BlueRF bus interface QoS flush Clock support ARM7TDMI 32-bit CPU Memory organization - Integrated 4 Mbit flash - 64 KByte on-chip RAM - 4 KByte on-chip boot ROM t e l o s b O October 2008 e t le o r P o s b O - Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as master and as slave od c u d ) s t( Efficient support for WLAN coexistence in collocated scenario Ciphering support for up to 128-bit key Receiver Signal Strength Indication (RSSI) support for power-controlled links Separate control for external power amplifier (PA) for class1 power support. Software support Description The E-STLC2416 from STMicroelectronics is a BluetoothTM baseband controller with integrated 4 Mbit flash memory. Together with a BluetoothTM Radio this product offers a compact and complete solution for short-range wireless connectivity. It incorporates all the lower layer functions of the BluetoothTM protocol. Rev 2 This is information on a product still in production but not recommended for new designs. 1/37 www.stnwireless.com 37 Contents E-STLC2416 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 2.3.1 Specifications for 3.3V I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.2 Specifications for 1.8V I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ) s t( 3 Block diagram and electrical schematics . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 c u d 5 e t le Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 6 o s b O - 5.1.1 Baseband 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.2 Baseband 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Integrated Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 ) s ( ct Flash signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 u d o General specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 r P e 6.1 t e l o 6.2 s b O 2/37 o r P Pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1.1 Slow clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Boot procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 Clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 Interrupts/wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 V1.2 detailed functionality - Extended SCO . . . . . . . . . . . . . . . . . . . . . . . 21 6.7 V1.2 detailed functionality - Adaptive frequency hopping . . . . . . . . . . . . . 21 6.8 V1.2 detailed functionality - Faster connection . . . . . . . . . . . . . . . . . . . . . 22 6.9 V1.2 detailed functionality - Quality of service . . . . . . . . . . . . . . . . . . . . . 22 34 .80 7IRELESS E-STLC2416 Contents 6.10 7 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.10.1 Sniff or park . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.10.2 Inquiry/page scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.10.3 No connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.10.4 Active link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.11 SW initiated low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.12 Bluetooth - WLAN coexistence in collocated scenario . . . . . . . . . . . . . . . 24 6.12.1 Algorithm 1: PTA (Packet Traffic Arbitration) . . . . . . . . . . . . . . . . . . . . . 24 6.12.2 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.12.3 Algorithm 3: Bluetooth master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.12.4 Algorithm 4: two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.12.5 Algorithm 5: alternating wireless medium access (AWMA) . . . . . . . . . . 26 ) s t( Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 c u d 7.1 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 Synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 o r P 7.2.1 Feature description: Agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2.2 Feature description: 32-bit SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 e t le 7.3 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.4 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.6 RF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.7 PCM voice interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ) s ( ct o s b O - u d o HCI UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 r P e 8.1 UART settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 t e l o 9 HCI USB transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 bs 10 O Class1 power support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 34 .80 7IRELESS 3/37 Overview 1 E-STLC2416 Overview The E-STLC2416 from STMicroelectronics is a BluetoothTM baseband controller with integrated 4 Mbit flash memory. Together with a BluetoothTM Radio this product offers a compact and complete solution for short-range wireless connectivity. It incorporates all the lower layer functions of the BluetoothTM protocol. The microcontroller allows the support of all data packets of BluetoothTM in addition to voice. The embedded controller can be used to run the BluetoothTM protocol and application layers if required. The software is located in the integrated flash memory. Detailed list of features Pin-to-pin compatible with the previous version STLC2415 Ericsson Technology Licensing Baseband Core (EBC) BluetoothTM specification compliance: V1.1 and V1.2 SW compatible with STLC2411-M28R400CT combination 2 layer class 4 PCB compatible Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (ACL) logical transport link Synchronous Connection Oriented (SCO) links: 2 simultaneous SCO channels Supports Pitch-period Error Concealment (PPEC) e t le c u d ) s t( o r P - Improves speech quality in the vicinity of interference - Improves coexistence with WLAN - Works at receiver, no Bluetooth implication o s b O - Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as master and as slave Faster connection: interlaced scan for page and inquiry scan, first FHS without random backoff, RSSI used to limit range Extended SCO (eSCO) links ) s ( ct u d o r P e t e l o s b O 4/37 34 .80 7IRELESS E-STLC2416 Overview Standard BlueRF bus interface QoS flush Clock support - System clock input at 13 and 26 MHz - LPO clock input at 3.2 and 32 kHz ARM7TDMI 32-bit CPU Memory organization - Integrated 4 Mbit flash - 64KByte on-chip RAM - 4KByte on-chip boot ROM Low power architecture with 2 different low power levels: sleep mode and deep sleep mode HW support for packet types - ACL: DM1, 3, 5 and DH1, 3, 5 - SCO: HV1, 3 and DV - eSCO: EV3, 5 c u d Communication interfaces ) s t( - Synchronous serial interface, supporting up to 32 bit data and different industry standards - Two enhanced 16550 UARTs with 128 byte FIFO depth - 12 Mbps USB interface - Fast master I2C bus interface - Multi slot PCM interface - 16 programmable GPIOs - 2 external interrupts and various interrupt possibilities through other interfaces e t le o r P o s b O - Efficient support for WLAN coexistence in collocated scenario Ciphering support for up to 128-bit key Receiver Signal Strength Indication (RSSI) support for power-controlled links Separate control for external power amplifier (PA) for class1 power support. Software support ) s ( ct u d o r P e t e l o - Low level (up to HCI) stack or embedded stack with profiles - Support of UART and USB HCI transport layers. Typical applications bs O Cable replacement Portable computers PDA, modems Handheld data transfer devices Cameras, computer peripherals Other type of devices that require the wireless communication provided by BluetoothTM 34 .80 7IRELESS 5/37 Quick reference data E-STLC2416 2 Quick reference data 2.1 Absolute maximum ratings Operation of the device beyond these conditions is not guaranteed. Sustained exposure to these limits will adversely affect device reliability. Table 1. Absolute maximum ratings Symbol 2.2 Conditions Min Max Unit VDD Supply voltage baseband core VSS - 0.5 2.5 V VDDF Supply voltage flash VSS - 0.5 2.5 V VPP Fast Program Voltage VSS - 0.5 13 V 4 V V VDDIO Supply voltage baseband I/O VDDQ Supply voltage flash I/O VSS - 0.5 2.5 VIN Input voltage on any digital pin (excluding FLASH input pins) VSS - 0.5 VDDIO + 0.3 V Tstg Storage temperature +150 ) s t( C Tlead Lead temperature < 10s +240 C c u d -55 ro P e let Operating ranges o s b O - Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied. Table 2. Operating ranges Symbol (s) Conditions ct VDD Supply voltage baseband core and EMI pads VDDF Supply voltage flash o r P e du Min Typ Max Unit 1.55 1.8 1.95 V 1.55 1.8 1.95 V VDDIO Supply voltage digital I/O 2.7 3.3 3.6 V VDDQ Supply voltage flash I/O (VDDQ VDDF) 1.55 1.8 1.95 V Tamb Operating ambient temperature -40 +85 C t e l o s b O 6/37 34 .80 7IRELESS E-STLC2416 2.3 Quick reference data I/O specifications Depending on the interface, the I/O voltage is typical 1.8V (interface to the flash memory) or typical 3.3V (all the other interfaces). These I/Os comply with the EIA/JEDEC standard JESD8-B. 2.3.1 Specifications for 3.3V I/Os Table 3. LVTTL DC input specification (3V<VDDIO<3.6V ) Symbol Parameter Vil Low level input voltage Vih High level input voltage Vhyst Conditions Min Schmitt trigger hysteresis Table 4. Parameter Low level output voltage High level output voltage Voh Max Unit 0.8 V 2 V 0.4 V LVTTL DC output specification (3V<VDDIO<3.6V) Symbol Vol Typ Conditions Min Typ Iol = X mA(1) Max Ioh =-X 0.15 mA(1) c u d VDDIO-0.15 ) s t( Unit V V o r P 1. X is the source/sink current under worst-case conditions according to the drive capability. (See Table 8, pad information for value of X). 2.3.2 Specifications for 1.8V I/Os Table 5. DC input specification (1.55V<VDD<1.95V) Symbol Parameter Vil Low level input voltage Vih High level input voltage Vhyst Table 6. ) s ( ct u d o Parameter r P e Low level output voltage t e l o Voh Min Typ Max Unit 0.35*VDD V 0.65*VDD V 0.2 0.3 0.5 V Min Typ Max Unit 0.15 V DC Output Specification (1.55V<VDD<1.95V) Symbol Vol o s b O - Conditions Schmitt trigger hysteresis e t le High level output voltage Conditions Iol = X mA(1) Ioh =-X mA(1) VDD-0.15 V 1. X is the source/sink current under worst-case conditions according to the drive capability. (See Table 8, pad information for value of X) s b O 34 .80 7IRELESS 7/37 Quick reference data 2.4 E-STLC2416 Current consumption Table 7. Typical power consumption of the E-STLC2416 (VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V) Core E-STLC2416 state IO Unit 5.10 0.13 mA 0.94 0.94 0.13 mA ACL connection (no transmission) 7.60 6.99 0.13 mA ACL connection (data transmission) 7.90 7.20 0.13 mA SCO connection (no codec connected) 8.70 7.90 0.14 mA Inquiry and Page scan (low power mode enabled) 127 n.a. 5 A Low Power mode (32 kHz crystal) 20 20 0 Slave Master Standby (no low power mode) 5.10 Standby (low power mode enabled) c u d e t le ) s ( ct ) s t( A o r P o s b O - u d o r P e t e l o s b O 8/37 34 .80 7IRELESS E-STLC2416 3 Block diagram and electrical schematics Block diagram and electrical schematics Figure 1. Block diagram and electrical schematic JTAG 5 4 PCM VDD 2 INTERRUPT CONTROLLER 100nF 2 USB VDDIO 100nF 2 I2C VDDIO 100nF ARM7 TDMI RF BUS 13 RADIO I/F BLUETOOTH CORE D M A RAM APB BRIDGE SPI TIMER GPIO START DETECT UART 4 16 8 PCM EXT._INT1/2 USB I2C SPI GPIO(O..15) 22pF LPOCLKP LPO Y2 32KHz UART FIFO BOOT ROM SYSTEM CONTROL VDD ADDR(0..17) EMI 100nF r P e t le 16 DATA(0..15) VDDPLL 18 18 WRN RDN 1 1 BOOT 2 CSN(1..2) 2 so 5 16 RDN/NG ADDR DATA(0..15) (0,2,17,18,19) b O - NRESET SYS_CLK_REQ DATA(0..15) 4Mbit FLASH 1 CSN(0) VDD 100nF NE 1 UART1 ADDR(1..18) NG CSN(0) XIN 16 od NW 1 uc UART 22pF LPOCLKN 2 ) s t( UART2 (*) 1 NE NRP NWP D03TL582A (**) (*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal (**) For device testing only (should not be connected in the application. ) s ( ct u d o r P e t e l o s b O 34 .80 7IRELESS 9/37 Pinout 4 E-STLC2416 Pinout Figure 2. Pin out (bottom view) 18 17 nreset nrp 16 15 13 14 uart1_ uart1_ i2c_ rxd txd dat i2c_ clk 12 11 10 9 7 8 6 5 pcm_ pcm_ usb_ uart2_ uart2_ uart2_ uart2_ dn rxd txd i1 o2 vddio sync a 4 3 2 1 vdd vss spi_ frm spi_ clk A spi_txd xin B pcm_ pcm- usb_ uart2_ uart2_ uart2_ uart2_ clk b dp i2 o1 io1 io2 vssio rdn/ng sys_cl k_req n.c. tck vssio ne csn1 tdo tms csn0 csn2 ntrst tdi addr0 vdd btxen vddio n.c. vss brxen ant_sw nwp addr2 bpktcl bpaen vpp vdd btxd bdclk vddf vss brclk bmosi vssf addr17 int2 int1 vddio vssio spi_rxd C D E F G H J K L brxd bmiso vddq bsen bnden n.c. gpio12 gpio14 n.c. gpio10 gpio15 data3 gpio11 gpio13 vsspll vssio vddio gpio3 gpio1 boot addr18 c u d M addr19 ) s t( N vss vdd P e let ro data8 data7 data6 data5 data4 gpio9 4.1 b O Pin description and assignment ) s ( t c u d o r P e t e ol P data1 R data2 T vdd U lpo_ lpo_ gpio8 gpio7 gpio6 vddpll gpio5 gpio4 gpio2 gpio0 clk_n clk_p data15 data14 data13 data12 data11 data10 data9 so data0 vss V D03TL583 Table 8 shows the pin list of the E-STLC2416. There are 91 functional pins of which 25 are used for device testing only (should not be connected in the application) and 24 supply pins. The column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This cannot replace an external pull-up/down. The pads are grouped according to two different power supply values, as shown in column "VDD": s b O 10/37 - V1 for 3.3 V typical 2.7 - 3.6 V range - V2 for 1.8 V typical 1.55 - 1.95 V range Finally the column "DIR" describes the pin directions: - I for Inputs - O for Outputs - I/O for Input/Outputs - O/t for tri-state outputs 34 .80 7IRELESS E-STLC2416 Table 8. Pinout E-STLC2416 pin list Name Pin # Description DIR PU/PD VDD PAD Clock and test pins xin B18 System clock I nreset A18 Reset I nrp A17 Flash reset I V2 nwp H3 Flash Write Protect I V2 CMOS 1.8V I/O V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control V1 sys_clk_req C18 System clock request lpo_clk_p V9 Low power oscillator + / Slow clock input I lpo_clk_n V10 Low power oscillator - O int1 C14 External Interrupt used also as external wake up I CMOS, 3.3V TTL compatible schmitt trigger (1) V2 int2 C15 Second external interrupt I (1) boot T10 Select external boot from EMI or internal from ROM I (1) I/O SPI interface e t le spi_frm A2 Synchronous Serial Interface frame sync spi_clk A1 Synchronous Serial Interface clock I/O spi_txd B1 Synchronous Serial Interface transmit data O/t spi_rxd C1 Synchronous Serial Interface receive data UART interface ) s ( ct uart1_txd A15 s b O I CMOS, 3.3V TTL compatible schmitt trigger V2 CMOS 1.8V V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control schmitt trigger V1 CMOS, 3.3V TTL compatible, 2mA slew rate control (1) V1 CMOS, 3.3V TTL compatible schmitt trigger Uart1 transmit data O/t V1 CMOS, 3.3V TTL compatible, 2mA slew rate control (2) V1 CMOS, 3.3V TTL compatible schmitt trigger c u d o r P u d o r P e t e l o o s b O - ) s t( V1 (1) uart1_rxd A16 Uart1 receive data I uart2_o1 C7 Uart2 modem output O V1 CMOS, 3.3V TTL compatible, 2mA slew rate control uart2_o2 A6 Uart2 modem output O/t V1 CMOS, 3.3V TTL compatible, 2mA slew rate control 34 .80 7IRELESS 11/37 Pinout E-STLC2416 Table 8. E-STLC2416 pin list (continued) Name uart2_i1 Pin # A7 Description DIR Uart2 modem input PU/PD VDD I (2) I (2) V1 V1 uart2_i2 C8 Uart2 modem input uart2_io1 C6 Uart2 modem input/output I/O (2) V1 uart2_io2 C5 Uart2 modem input/output I/O (2) V1 uart2_txd A8 Uart2 transmit data O/t uart2_rxd A9 Uart2 receive data I PAD CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, 2mA tristate slew rate control V1 CMOS, 3.3V TTL compatible, 2mA slew rate control (2) V1 CMOS, 3.3V TTL compatible I/O (3) V1 I2C clock pin I/O (3) V1 (1) I2C interface i2c_dat i2c_clk A14 A13 I2C data pin USB interface usb_dn A10 USB - pin (Needs a series resistor of 27 5%) I/O usb_dp C9 USB + pin (Needs a series resistor of 27 5%) I/O I/O PU I/O PU I/O PU GPIO interface gpio0 V11 Gpio port 0 gpio1 T11 Gpio port 1 gpio2 V12 Gpio port 2 gpio3 T12 gpio4 V13 gpio6 bs gpio7 Gpio port 3 o s b O - (1) I/O PU Gpio port 4 I/O PU Gpio port 5 I/O PU V16 Gpio port 6 I/O PU V17 Gpio port 7 I/O PU r P e t e l o gpio5 u d o ) s ( ct e t le V14 ) s t( CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control c u d o r P V1 V1 V1 CMOS, 3.3V TTL compatible, 4mA tri-state slew rate control V1 CMOS, 3.3V TTL compatible, 4mA tristate slew rate control schmitt trigger V1 CMOS, 3.3V TTL compatible, 4mA tri-state slew rate control O 12/37 34 .80 7IRELESS E-STLC2416 Table 8. Name Pinout E-STLC2416 pin list (continued) Pin # Description DIR PU/PD VDD gpio8 V18 Gpio port 8 I/O PU gpio9 U18 Gpio port 9 I/O PU gpio10 R18 Gpio port 10 I/O PU gpio11 T18 Gpio port 11 I/O PU gpio12 P18 Gpio port 12 I/O PU gpio13 T16 Gpio port 13 I/O PU gpio14 P16 Gpio port 14 I/O PU gpio15 R16 Gpio port 15 I/O PU PAD V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control JTAG interface ntrst F18 JTAG pin I PD V1 CMOS, 3.3V TTL compatible tck D18 JTAG pin I (1) V1 CMOS, 3.3V TTL compatible schmitt trigger tms E16 JTAG pin I PU tdi F16 JTAG pin I tdo E18 JTAG pin (should be left open) PCM interface pcm_a A11 PCM data pcm_b C10 PCM data pcm_sync A12 PCM 8kHz sync pcm_clk C11 r P e t e l o brclk brxd s b O bmiso L18 od PCM clock Radio interface uc (t s) Transmit clock e t le O/t o s b O - I/O PD I/O PD I/O PD I/O PD I (1) M18 Receive data I M16 RF serial interface input data I 34 .80 7IRELESS PU (1) c u d ) s t( o r P V1 CMOS, 3.3V TTL compatible V1 CMOS, 3.3V TTL compatible, 2mA slew rate control V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control schmitt trigger V1 CMOS, 3.3V TTL compatible schmitt trigger V1 CMOS, 3.3V TTL compatible 13/37 Pinout E-STLC2416 Table 8. Name E-STLC2416 pin list (continued) Pin # Description DIR bnden N16 RF serial interface control O bmosi L16 RF serial interface output data O bdclk K16 RF serial interface clock O btxd K18 Transmit data O bsen N18 Synthesizer ON O bpaen J16 Open PLL O brxen H18 Receive ON O btxen G18 Transmit ON O bpktctl J18 Packet ON O ant_sw H16 Antenna switch O PU/PD VDD PAD V1 CMOS, 3.3V TTL compatible, 2mA slew rate control V1 CMOS, 3.3V TTL compatible, 8mA slew rate control 1. Should be strapped to vssio if not used. c u d 2. Should be strapped to vddio if not used. 3. Must have a 10 kohm pull-up. Table 9. E-STLC2416 pin list - Power supply Name Pin# vsspll T15 PLL ground vddpll V15 1.8V supply for PLL vdd A4 1.8V Digital supply vdd F1 1.8V Digital supply vdd J1 1.8V Digital supply vdd U1 1.8V Digital supply vdd T8 1.8V Digital supply vddf K3 1.8V Digital supply Flash vddq M3 1.8V I/O's supply Flash vpp J3 12V fast program supply Flash vddio C13 3.3V I/O's supply vddio A5 3.3V I/O's supply vddio T13 3.3V I/O's supply vddio G16 3.3V I/O's supply vss A3 Digital ground vss G1 Digital ground vss K1 Digital ground vss V1 Digital ground 14/37 ) s ( ct o r P o s b O - u d o r P e t e l o s b O e t le Description ) s t( 34 .80 7IRELESS E-STLC2416 Table 9. Pinout E-STLC2416 pin list - Power supply (continued) Name Pin# vss T9 Digital ground vssf L3 Digital ground Flash vssio C12 I/O's ground vssio C4 I/O's ground vssio T14 I/O's ground vssio D16 I/O's ground Table 10. Name Description E-STLC2416 pin list (continued) Pin # Description DIR PU/PD VDD PAD To be connected together on the PCB ne D3 Flash chip enable I csn0 E3 External chip select bank 0 O c u d Test only (do not connect) rdn/ng C3 External read O csn1 D1 External chip select bank 1 O csn2 E1 External chip select bank 2 O addr0 F3 External address bit 0 O addr2 H1 External address bit 2 addr17 L1 External address bit 17 addr18 M1 External address bit 18 addr19 N1 External address bit 19 data0 P1 External data bit 0 data1 R1 data2 data3 c u d (t s) V2 e t le O b O - O CMOS 1.8V 4 mA slew rate control O O PD External data bit 1 I/O PD T1 External data bit 2 I/O PD R3 External data bit 3 I/O PD t e l o data4 T3 External data bit 4 I/O PD data5 T4 External data bit 5 I/O PD s b O 34 .80 7IRELESS o r P so I/O o r P e ) s t( 15/37 Pinout E-STLC2416 Table 10. E-STLC2416 pin list (continued) Name Pin # Description DIR PU/PD VDD data6 T5 External data bit 6 I/O PD data7 T6 External data bit 7 I/O PD data8 T7 External data bit 8 I/O PD data9 V2 External data bit 9 I/O PD data10 V3 External data bit 10 I/O PD V2 data11 V4 External data bit 11 I/O PD data12 V5 External data bit 12 I/O PD data13 V6 External data bit 13 I/O PD data14 V7 External data bit 14 I/O PD data15 V8 External data bit 15 I/O PD PAD CMOS 1.8 V 4 mA slew rate control Not connected n.c. C16, G3, N3, P3 c u d Not connected e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 16/37 34 .80 7IRELESS E-STLC2416 Functional description 5 Functional description 5.1 Baseband WLAN coexistence. See also Section 6.12: Bluetooth - WLAN coexistence in collocated scenario. 5.1.1 Baseband 1.1 features The baseband is based on Ericsson Technology Licensing Baseband Core (EBC) and it is compliant with the Bluetooth specification 1.1: 5.1.2 - Point to multipoint (up to 7 slaves) - Asynchronous Connection Less (ACL) link support giving data rates up to 721 kbps - Synchronous Connection Oriented (SCO) link with support for 2 voice channels over the air interface. - Flexible voice format to host and over the air (CVSD, PCM 13/16 bits, A-law, law) c u d ) s t( - HW support for packet types: DM1, 3, 5; DH1, 3, 5; HV1, 3; DV - Scatternet capabilities (master in one piconet and slave in the other one; slave in two piconets). All scatternet v.1.1 errata supported. - Ciphering support up to 128 bits key - Paging modes R0, R1, R2 - Channel quality driven data rate - Full Bluetooth software stack available - Low level link controller Baseband 1.2 features ) s ( ct e t le o r P o s b O - The baseband part is also compliant with the Bluetooth specification 1.2: - Extended SCO (eSCO) links: supports EV3 and EV5 packets. See also Section 6.6: V1.2 detailed functionality - Extended SCO. - Adaptive frequency hopping (AFH): hopping kernel, channel assessment as Master and as Slave. See also Section 6.7: V1.2 detailed functionality - Adaptive frequency hopping. - Faster connection: Interlaced scan for Page and Inquiry scan, answer FHS at first reception, RSSI used to limit range. See also Section 6.8: V1.2 detailed functionality - Faster connection. - QoS Flush. See also Section 6.9: V1.2 detailed functionality - Quality of service. - Synchronization: the local and the master BT clock are available via HCI commands for synchronization of parallel applications on different slaves - L2CAP flow and error control - LMP Improvements - LMP SCO handling - Parameter Ranges update u d o r P e t e l o s b O 34 .80 7IRELESS 17/37 Functional description 5.2 E-STLC2416 Note: Integrated Flash memory - 4 Mbit size - 8 parameter blocks of 4 Kword (top configuration) - 7 main blocks of 32 Kword - 120 ns access time See the datasheet of the standalone product M28R400CT for more detailed information. Figure 3. Block addresses M28R400CT Top Boot Block Addresses 3FFFF 4 KWords 3F000 Total of 8 4 KWord Blocks 38FFF c u d 4 KWords 38000 37FFF 32 KWords 30000 e t le 0FFFF ) s ( ct 00000 5.2.1 32 KWords u d o r P e t e l o bs 18/37 Total of 7 32 KWord Blocks Flash signal descriptions O o r P b O - 32 KWords 08000 07FFF so ) s t( Write Protect (nwp) Write protect is an input that gives an additional hardware protection for each block. When Write Protect is 0.4V the Lock-Down is enabled and the protection status of the flash blocks cannot be changed. When Write Protect is (vddq - 0.4V), the Lock-Down is disabled and the flash memory blocks can be locked or unlocked. Reset (nrp) The Reset input provides a hardware reset of the memory. When reset is 0.4V, the memory is in reset mode: the outputs are high impedant and the current consumption is minimized. After Reset all blocks are in Locked state. When Reset is (vddq - 0.4V), the device is in normal operation. Exiting reset mode the device enters read array 34 .80 7IRELESS E-STLC2416 Functional description mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs. Vdd Supply Voltage (vddf) Vdd provides the power supply to the internal core of the flash memory device. It is the main power supply for all operations (Read, Program and Erase) Vddq Supply Voltage (vddq) Vddq provides the power supply to the I/O pins and enables all Outputs to be powered independently from Vddf. Vddq can be tied to Vddf or can use separate supply. Vpp Program Supply Voltage (vpp) Vpp is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The supply voltage Vddf and the program supply voltage Vpp can be applied in any order. If Vpp is kept in a low voltage range (0V to 3.6V) Vpp is seen as a control input. In this case a voltage lower than 1V gives protection against program or block erase, while 1.65V<Vpp<3.6V enables these functions. Vpp is only sampled at the beginning of a program or block erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If Vpp is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition Vpp must be stable until the Program/Erase algorithm is completed. c u d ) s t( Vssf Flash Ground (vssf) Vssf is the reference for all voltage measurements. Address Inputs (Addr0-Addr17), Data Input/Output (Data0-Data15), Chip Enable (csn0), Output Enable (rdn/ng), Write Enable (wrn) are connected to and controlled by the BluetoothTM baseband controller. e t le ) s ( ct o r P o s b O - u d o r P e t e l o s b O 34 .80 7IRELESS 19/37 General specification E-STLC2416 6 General specification 6.1 System clock The E-STLC2416 works with a single clock provided on the XIN pin. The value of this external clock should be any integer value from 12 ... 33 MHz 20ppm (overall). 6.1.1 Slow clock The slow clock is used by the baseband as reference clock during the low power modes. The slow clock requires an accuracy of 250ppm (overall). Several options are foreseen in order to adjust the E-STLC2416 behavior according to the features of the radio used: 6.2 If the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and no slow clock is provided by the system, a 32 kHz crystal must be used by the E-STLC2416 (default mode). If the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and the system provides a slow clock at 32kHz or 3.2kHz, this signal is simply connected to the E-STLC2416 (lpo_clk_p). If the system clock (e.g. 13MHz) is provided at all times, the E-STLC2416 generates from the reference clock an internal 32kHz clock. This mode is not an optimized mode for power consumption. c u d Boot procedure e t le ) s t( o r P o s b O - The boot code instructions are the first that ARM7TDMI executes after a HW reset. All the internal device's registers are set to their default value. There are 2 types of boot: ) s ( ct Flash boot. When boot pin is set to 1 (connected to VDD), the E-STLC2416 boots on its flash u d o UART download boot from ROM. When boot pin is set to 0 (connected to GND), the E-STLC2416 boots on its internal ROM (needed to download the new firmware in the flash). When booting on the internal ROM, the E-STLC2416 will monitor the UART interface for approximately 1.4 second. If there is no request for code downloading during this period, the ROM jumps to flash. r P e s b O t e l o Clock detection 6.3 20/37 The E-STLC2416 has an automatic slow clock frequency detection (32kHz, 3.2kHz or none). 34 .80 7IRELESS E-STLC2416 6.4 General specification Master reset When the device's reset is held active (nreset is low), uart1_txd and uart2_txd are set to input state. When the nreset returns high, the device starts to boot. Note: The device should be held in active reset for minimum 20ms in order to guarantee a complete reset of the device. 6.5 Interrupts/wake-up All GPIOs can be used both as external interrupt source and as wake-up source. In addition the device can be woken-up by USB, uart1_rxd, uart2_rxd, int1, int2. 6.6 V1.2 detailed functionality - Extended SCO User Perspective - Extended SCO ) s t( This function gives improved voice quality since it enables the possibility to retransmit lost or corrupted voice packets in both directions. c u d Technical perspective - Extended SCO eSCO incorporates CRC, negotiable data rate, negotiable retransmission window and multislot packets. Retransmission of lost or corrupted packets during the retransmission window guarantees on-time delivery. Figure 4. e t le Extended eSCO SCO SCO SCO o s b O SCO ACL ACL SCO o r P SCO t eSCO retransmission window 6.7 ) s ( ct u d o V1.2 detailed functionality - Adaptive frequency hopping r P e In the Bluetooth spec 1.1 the Bluetooth devices hop in the 2.4 GHz band over 79-channels. Since WLAN 802.11 has become popular, there are specification improvements in the 1.2SIG spec for Bluetooth where the Bluetooth units can avoid the jammed bands and thereby provide an improved co-existence with WLAN. t e l o s b O User perspective - Adaptive frequency hopping 34 .80 7IRELESS Technical perspective - Adaptive frequency hopping 21/37 General specification Figure 5. E-STLC2416 AFH AFH(79) f WLAN used frequency t f AFH(19<N<79) WLAN used frequency t ) s t( First the Master and/or the Slaves identify the jammed channels. The Master decides on the channel distribution and informs the involved slaves. The Master and the Slaves, at a predefined instant, switch to the new channel distribution scheme. c u d No longer jammed channels are re-inserted into the channel distribution scheme. AFH uses the same hop frequency for transmission as for reception 6.8 e t le o r P V1.2 detailed functionality - Faster connection User perspective - Faster connection o s b O - This feature gives the User about 65% faster connection on average when enabled compared to Bluetooth spec 1.1 connection procedure. Technical perspective - Faster connection ) s ( ct The faster Inquiry functionality is based on a removed/shortened random back off and also a new Interlaced Inquiry scan scheme. u d o The faster Page functionality is based on Interlaced Page Scan. 6.9 r P e V1.2 detailed functionality - Quality of service t e l o User perspective - Quality of service s b O 22/37 Small changes to the BT1.1 spec regarding Quality of Service makes a large difference by allowing all QoS parameters to be communicated over HCI to the link manager that enables efficient BW management. Here after a short list of user perspectives: 1. Flush time-out: enables time-bounded traffic such as video streaming to become more robust when the channel degrades. It sets the maximum delay of an L2CAP frame. It does not enable multiple streams in one piconet, or heavy data transfer at the same time. 2. Simple latency control: allows the host to set the poll interval. Provides enough support for HID devices mixed with other traffic in the piconet. 34 .80 7IRELESS E-STLC2416 6.10 General specification Low power modes To save power, two low power modes are supported. Depending of the Bluetooth and of the Host's activity, the E-STLC2416 autonomously decides to use Sleep Mode or Deep Sleep Mode. Table 11. Low power modes Low power mode Description Sleep mode The E-STLC2416: - Accepts HCI commands from the Host. - Supports page- and inquiry scans. - Supports Bluetooth links that are in Sniff, Hold or Park. - Can transfer data over Bluetooth links. - The system clock is still active in part of the design. Deep sleep mode The E-STLC2416: - Does not accept HCI commands from the Host. - Keeps track of page- and inquiry scan activities. - Switches between sleep and active mode when it is time to scan. - Supports Bluetooth links that are in Sniff, Hold or Park. - Does not transfer data over Bluetooth links. - The system clock is not active in any part of the design. Note: Deep Sleep mode is not compatible with a USB transport layer. c u d e t le Some examples of the low power modes usage: 6.10.1 Sniff or park ) s t( o r P o s b O - The E-STLC2416 is in active mode with a Bluetooth connection, once the connection is concluded the SNIFF or the PARK is programmed. Once one of these two states is entered the E-STLC2416 goes in Sleep Mode. After that, the Host may decide to place the ESTLC2416 in Deep Sleep Mode by putting the UART LINK in low power mode. The Deep Sleep Mode allows smaller power consumption. When the E-STLC2416 needs to send or receive a packet (e.g. at TSNIFF or at the beacon instant) it will require the clock and it will go in active mode for the needed transmission/reception. Immediately afterwards it will go back to the Deep Sleep Mode. If some HCI transmission is needed, the UART link will be reactivated, using one of the two ways explained in 7.5, and the E-STLC2416 will move from the Deep Sleep Mode to the Sleep Mode. ) s ( ct u d o r P e t e l o 6.10.2 bs O 6.10.3 Inquiry/page scan When only inquiry scan or page scan is enabled, the E-STLC2416 will go in Sleep Mode or Deep Sleep Mode outside the receiver activity. The selection between Sleep Mode and Deep Sleep Mode depend on the UART activity like in SNIFF or PARK. No connection If the Host places the UART in low power and there is no activity, then the E-STLC2416 can be placed in Deep Sleep Mode. 34 .80 7IRELESS 23/37 General specification 6.10.4 E-STLC2416 Active link When there is an active link (SCO or ACL), the E-STLC2416 cannot go in Deep Sleep Mode whatever the UART state is. But the E-STLC2416 baseband is made such that whenever it is possible, depending on the scheduled activity (number of link, type of link, amount of data exchanged), it goes in Sleep Mode. 6.11 SW initiated low power mode A wide set of wake up mechanisms are supported. 6.12 Bluetooth - WLAN coexistence in collocated scenario The coexistence interface uses 4 GPIO pins, when enabled. Bluetooth and WLAN 802.11 b/g technologies occupy the same 2.4 GHz ISM band. ESTLC2416 implements a set of mechanisms to avoid interference in a collocated scenario. ) s t( The E-STLC2416 supports 5 different algorithms in order to provide efficient and flexible simultaneous functionality between the two technologies in collocated scenarios: c u d Algorithm 1: PTA (Packet Traffic Arbitration) based coexistence algorithm defined in accordance with the IEEE 802.15.2 recommended practice. Algorithm 2: the WLAN is the master and it indicates to the E-STLC2416 when not to operate in case of simultaneous use of the air interface. Algorithm 3: the E-STLC2416 is the master and it indicates to the WLAN device when not to operate in case of simultaneous use of the air interface. Algorithm 4: Two-wire mechanism Algorithm 5: Alternating Wireless Medium Access (AWMA), defined in accordance with the WLAN 802.11 b/g technologies. ) s ( ct e t le o r P o s b O - The algorithm is selected via HCI command. The default algorithm is algorithm 1. 6.12.1 Algorithm 1: PTA (Packet Traffic Arbitration) u d o The Algorithm is based on a bus connection between the E-STLC2416 and the WLAN device. r P e Figure 6. t e l o bs Bus connection between the E-STLC2416 and the WLAN device STLC2416 WLAN O By using this coexistence interface it's possible to dynamically allocate bandwidth to the two devices when simultaneous operations are required while the full bandwidth can be allocated to one of them in case the other one does not require activity. The algorithm involves a priority mechanism, which allows preserving the quality of certain types of link. A typical application would be to guarantee optimal quality to the Bluetooth voice communication while an intensive WLAN communication is ongoing. 24/37 34 .80 7IRELESS E-STLC2416 General specification Several algorithms have been implemented in order to provide a maximum of flexibility and efficiency for the priority handling. Those algorithms can be activated via specific HCI commands. The combination of a time division multiplexing techniques to share the bandwidth in case of simultaneous operations and of the priority mechanism avoid the interference due to packet collision and it allows the maximization of the 2.4 GHz ISM bandwidth usage for both devices while preserving the quality of some critical types of link. 6.12.2 Algorithm 2: WLAN master In case the E-STLC2416 has to cooperate, in a collocated scenario, with a WLAN device not supporting a PTA based algorithm, it is possible to put in place a simpler mechanism. The interface is reduced to 1 line: Figure 7. Algorithm 2 - WLAN master RF_NOT_ALLOWED STLC2416 WLAN c u d ) s t( When the WLAN has to operate, it alerts RF_NOT_ALLOWED signal and the E-STLC2416 does not operate while this signal remains HIGH. o r P This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth but cannot provide guaranteed quality over the Bluetooth links. 6.12.3 e t le o s b O - Algorithm 3: Bluetooth master This algorithm represents the symmetrical case of Section 6.12.2. Also in this case the interface is reduced to 1 line. Figure 8. ) s ( ct Algorithm 3 - Bluetooth master o r P e du RF_NOT_ALLOWED STLC2416 WLAN When the E-STLC2416 has to operate it alerts HIGH the RF_NOT_ALLOWED signal and the WLAN will not operate while this signals stays HIGH. t e l o s b O 6.12.4 This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth, it provides high quality for all Bluetooth links but cannot provide guaranteed quality over the WLAN links. Algorithm 4: two-wire mechanism Based on algorithm 2 and 3, the Host decides, on a case-by-case basis, whether WLAN or Bluetooth is master. 34 .80 7IRELESS 25/37 General specification 6.12.5 E-STLC2416 Algorithm 5: alternating wireless medium access (AWMA) AWMA utilizes a portion of the WLAN beacon interval for Bluetooth operations. From a timing perspective, the medium assignment alternates between usage following WLAN procedures and usage following Bluetooth procedures. The timing synchronization between the WLAN and the E-STLC2416 is done by the HW signal MEDIUM_FREE. Table 12. WLAN HW signal assignment WLAN Scenario 1: PTA Scenario 2: WLAN master Scenario 3: BT master Scenario 4: 2wire Scenario 5: AWMA WLAN 1 TX_ CONFIRM BT_RF_NOT_ ALLOWED Not used BT_RF_NOT_ ALLOWED MEDIUM_FREE WLAN 2 TX_ REQUEST Not used WLAN 3 STATUS Not used Not used Not used Not used WLAN 4 OPTIONAL_ SIGNAL Not used Not used Not used Not used WLAN_RF_ NOT_ WLAN_RF_ NOT_ ALLOWED ALLOWED Not used c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 26/37 34 .80 7IRELESS E-STLC2416 Interfaces 7 Interfaces 7.1 UART Interface The device contains two enhanced (128 byte transmit FIFO and 128 byte receive FIFO, sleep mode, 127 Rx and 128 Tx interrupt thresholds) UARTs named UART1 and UART2 compatible with the standard M16550 UART. For UART1, only Rx and Tx signals are available (used for debug purposes). UART2 features: standard HCI UART transport layer: - all HCI commands as described in the BluetoothTM specification 1.1 - ST specific HCI command (check E-STLC2416 Software Interface document for more information) RXD, TXD, CTS, RTS on permanent external pins 128-byte FIFOs, for transmit and for receive Default configuration: 57.600 kbps Specific HCI command to change to the following baud rates: Table 13. List of supported baud rates Baud rate 57.600 kbps (default) 921.6k 38.4 k 460.8 k 153.6 k 115.2 k c u d 76.8 k o r P e o s b O 28.8 k 230.4 k 7.2 e t le - (t s) o r P c u d ) s t( 4800 2400 1800 19.2 k 1200 14.4 k 900 9600 600 7200 300 Synchronous serial interface The Synchronous Serial Interface (SSI) (or the Synchronous Peripheral Interface (SPI)) is a flexible module supporting full-duplex and half-duplex synchronous communications with external devices in Master and Slave mode. It enables a microcontroller unit to communicate with peripheral devices or allows inter-processor communications in a multiple-master environment. This Interface is compatible with the Motorola SPI standard, with the Texas Instruments Synchronous Serial frame format and with National Semiconductor Microwire standard. t e l o s b O Special extensions are implemented to support the Agilent SPI interface for optical mouse applications and the 32 bit data SPI for stereo codec applications. 34 .80 7IRELESS 27/37 Interfaces 7.2.1 E-STLC2416 Feature description: Agilent mode One application is a combination of a Bluetooth device with an AGILENT optical mouse sensor to build a Bluetooth Mouse. The AGILENT device has an SPI interface with one bidirectional data port. When spi_io from ADNS_2030 is driving, spi_rxd should be active, while spi_txd is set as a tri-state high impedance input. For a read operation, the Bluetooth spi_txd is put in high impedance state after the reception of the address. Note that this feature works independently of the SPI mode, supporting other combinations. In this case, the devices are connected as described in the figure below. Figure 9. Agilent mode Agilent ADNS-2030 STLC2416 spi_clk spi_clk spi_frm c u d spi_txd spi_io spi_rxd 7.2.2 e t le Feature description: 32-bit SPI ) s t( o r P o s b O - One application is a Bluetooth stereo headset. In this application, the audio samples are received from the emitter through the air using the Bluetooth baseband with ACL packets. The samples are decoded by the embedded ARM CPU (the samples were encoded, for compression, in SBC or MP3 format) and then sent to a stereo codec though the SPI interface. The application is described in the figure below. ) s ( ct Figure 10. 32-bit SPI r P e u d o t e l o bs Bluetooth reception STLC2416 SPI slave mode 32 bits spi_txd spi_r xd spi_frm spi_clk STw5094A CODEC SPI master mode 32 bits stereo headset 32 spi_clk 16 spi_clk O To support this application, the data size is 32 bits. The 32 bits support is implemented for both transmit and receive. 28/37 34 .80 7IRELESS E-STLC2416 7.3 Interfaces I2C interface Used to access I2C peripherals. The interface is a fast master I2C; it has full control of the interface at all times. I2C slave functionality is not supported. 7.4 USB interface The USB interface is compliant with the USB 2.0 full speed specification. Max throughput on the USB interface is 12 Mbit/s. Figure 11 gives an overview of the main components needed for supporting the USB interface, as specified in the BluetoothTM Core Specification. For clarity, the serial interface (including the UART Transport Layer) is also shown. Figure 11. USB interface HCI USB TRANSPORT LAYER USB DRIVER e t le SERIAL DRIVER o s b O - t c u UART DEVICE REGISTERS FIFOs RTOS IRQ (s) o r P IRQ STLC2416 HW D04TL624 USB DEVICE REGISTERS FIFOs c u d UART TRANSPORT LAYER ) s t( The USB device registers and FIFOs are memory mapped. The USB Driver will use these registers to access the USB interface. The equivalent exists for the HCI communication over UART. d o r P e For transmission to the host, the USB and Serial Drivers interface with the HW via a set of registers and FIFOs, while in the other direction, the hardware may trigger the Drivers through a set of interrupts (identified by the RTOS, and directed to the appropriate Driver routines). t e l o s b O7.5 JTAG Interface The JTAG interface is compliant with the JTAG IEEE Std 1149.1. Its allows both the boundary scan of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 development tools. 34 .80 7IRELESS 29/37 Interfaces 7.6 E-STLC2416 RF Interface The E-STLC2416 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirectional serial interface for control). 7.7 PCM voice interface The voice interface is a direct PCM interface to connect to a standard CODEC (e.g. STw5093 or STw5094) including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), -Law (8bit) or A-Law (8bit). By default the codec interface is configured as master. The encoding on the air interface is programmable to be CVSD, ALaw or -Law. The PCM block is able to manage the PCM bus with up to 3 time slots. In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of standard codecs. The four signals of the PCM interface are: PCM_CLK: PCM clock PCM_SYNC: PCM 8kHz sync PCM_A: PCM data PCM_B: PCM data c u d Directions of PCM_A and PCM_B are software configurable. e t le ) s t( o r P Three additional PCM_SYNC signals can be provided via the GPIOs. See Chapter 7: Interfaces for more details. o s b O - Figure 12. PCM (A-law, -law) standard mode 0 1 2 3 4 5 PCM_CLK ) s ( ct PCM_SYNC PCM_A 6 7 8 9 10 11 12 13 14 15 B PCM_B o r P e du B B B 125s D02TL558 Figure 13. Linear mode t e l o s b O 30/37 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PCM_CLK PCM_SYNC PCM_A PCM_B 125s D02TL559 34 .80 7IRELESS E-STLC2416 Interfaces Table 14. PCM interface timing Symbol Description Fpcm_clk Min Typ Frequency of PCM_CLK (master) Max Unit 2048 kHz 8 kHz Fpcm_sync Frequency of PCM_SYNC tWCH High period of PCM_CLK 200 ns tWCL Low period of PCM_CLK 200 ns tWSH High period of PCM_SYNC 200 ns tSSC Setup time, PCM_SYNC high to PCM_CLK low 100 ns tSDC Setup time, PCM_A/B input valid to PCM_CLK low 100 ns tHCD Hold time, PCM_CLK low to PCM_A/B input invalid 100 ns tDCD Delay time, PCM_CLK high to PCM_A/B output valid 150 c u d Figure 14. PCM interface timing tWCL o r P PCM_CLK tWCH PCM_SYNC tSDC so tWSH PCM_A/B in PCM_B/A out ) s ( ct e t le tSSC b O MSB MSB MSB-1 ) s t( ns tHCD MSB-2 MSB-3 MSB-4 tDCD MSB-1 MSB-2 MSB-3 MSB-4 D02TL557 u d o r P e t e l o s b O 34 .80 7IRELESS 31/37 HCI UART transport layer 8 E-STLC2416 HCI UART transport layer The UART Transport Layer has been specified by the BluetoothTM SIG, and allows HCI level communication between a host controller (E-STLC2416) and a host (e.g. PC), via a serial line. The objective of this HCI UART Transport Layer is to make it possible to use the BluetoothTM HCI over a serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the UART communication is free from line errors. 8.1 UART settings The HCI UART Transport Layer uses the following settings for RS232: Baud rate: configurable (default baud rate: 57.600 kbps) Number of data bits: 8 Parity bit: no parity Stop bit: 1 stop bit Flow control: RTS/CTS Flow-off response time: 3 ms c u d ) s t( o r P Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for HCI flow control, since HCI has its own flow control mechanisms for HCI commands, HCI events and HCI data. e t le If CTS equals 1, then the Host/Host Controller is allowed to send. o s b O - If CTS equals 0, then the Host/Host Controller is not allowed to send. The flow-off response time defines the maximum time from setting RTS low until the byte flow actually stops. The signals should be connected in a null-modem fashion; i.e. the local TXD should be connected to the remote RXD and the local RTS should be connected to the remote CTS and vice versa. ) s ( ct Figure 15. UART transport layer u d o r P e t e l o BLUETHOOTH HOST BLUETHOOTH HCI HCI UART TRANSPORT LAYER BLUETHOOTH HOST CONTROLLER D02TL556 s b O 32/37 34 .80 7IRELESS E-STLC2416 9 HCI USB transport layer HCI USB transport layer The USB Transport Layer has been specified by the BluetoothTM SIG, and allows HCI level communication between a host controller (E-STLC2416) and a host (e.g. PC), via a USB interface. The USB Transport Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for transmission over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from USB data received from the USB Driver, and sends these messages to the HCI Layer. The Transport Layer does not interpret the contents (payload) of the HCI messages; it only examines the header. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 34 .80 7IRELESS 33/37 Class1 power support 10 E-STLC2416 Class1 power support The device can control an external power amplifier (PA). Several signals are duplicated on GPIOs for this purpose in order to avoid digital/analogue noise loops in the radio. A software controlled register enables the alternate functions of GPIO[15:6] to generate the signals for driving an external PA in a BluetoothTM class1 power application. Every bit enables a dedicated signal on a GPIO pin, as described in Table 15. Table 15. GPIOs Involved GPIO Description gpio0 No dedicated function gpio1 WLAN 1 gpio2 WLAN 2 gpio3 WLAN 3 gpio4 WLAN 4 gpio5 (Used for USB reset pull.) gpio6 Power Class 1 rxon gpio7 Power Class 1 not_rxon gpio8 Power Class 1 PA0 or PCM sync 1 gpio9 Power Class 1 PA1 or PCM sync 2 gpio10 Power Class 1 PA2 or PCM sync 3 gpio11 Power Class 1 PA3 gpio12 Power Class 1 PA4 gpio13 Power Class 1 PA5 gpio14 Power Class 1 PA6 gpio15 o r P e ) s ( ct c u d e t le ) s t( o r P o s b O - du Power Class 1 PA7 rx_on is the same as the rx_on output pin. Not rx_on is the inverted signal, in order to save components on the application board. PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis, by the baseband core. The Power Level programmed for a certain BluetoothTM connection is managed by the firmware, as specified in the BluetoothTM SIG spec. t e l o s b O 34/37 34 .80 7IRELESS E-STLC2416 11 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 16. LFBGA120 mechanical data and package dimensions DIM. A A1 A2 b D D1 D2 E E1 E2 eD eE FD FE mD mE n SE SD MIN. mm TYP. MAX. 1.40 MIN. inch TYP. MAX. 0.055 0.20 aaa bbb ddd eee fff 0.008 1 0.039 0.25 0.30 0.35 0.010 0.012 0.014 9.90 10.00 10.10 0.390 0.394 0.398 8.50 0.335 6.50 0.256 9.90 10.00 10.10 0.390 0.394 0.398 8.50 0.335 6.50 0.256 0.50 basic 0.020 basic 0.50 basic 0.020 basic 0.75 0.029 0.75 0.029 18 18 120 balls 0.25 basic 0.0098 basic 0.25 basic 0.0098 basic Tolerance 0.15 0.006 0.10 0.0039 0.08 0.0031 0.15 0.006 0.05 0.002 OUTLINE AND MECHANICAL DATA ) s ( ct c u d e t le ) s t( o r P Body: 10 x 10 x 1.4mm o s b O - LFBGA120 Low Fine Ball Grid Array u d o r P e t e l o s b O 7513355 A 34 .80 7IRELESS 35/37 Ordering information 12 E-STLC2416 Ordering information Table 16. 13 Order codes Part Number Package Temp. Range E-STLC2416 LFBGA120 (lead free) -40 to +85 C Revision history Table 17. Document revision history Date Revision 20-Nov-2006 1 Initial release. 2 Updated the document status to `Nor recommended for new design'. Applied ST-NXP Wireless template. No change in the content. 03-Oct-2008 Changes c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 36/37 34 .80 7IRELESS E-STLC2416 Please Read Carefully: Information in this document is provided solely in connection with ST-NXP products. ST-NXP Wireless NV and its subsidiaries ("ST-NXP") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST-NXP products are sold pursuant to ST-NXP's terms and conditions of sale. c u d ) s t( Purchasers are solely responsible for the choice, selection and use of the ST-NXP products and services described herein, and ST-NXP assumes no liability whatsoever relating to the choice, selection or use of the ST-NXP products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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