CD40174BKMSR - Intersil Corporation

7-1384

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Pinout

CD40174BMS

TOP VIEW

Functional Diagram

CLEAR

VSS

VDD

CLOCK

F/F1

F/F2

D1 3

D2 4Q2

F/F3

D3 6Q3

F/F4

D4 11 Q4

F/F5

D5 13 Q5

F/F6

D5 14 Q6

CLOCK 9

CLEAR 1

VSS = 8

VDD = 16

Features

• High Voltage Type (20V Rating)

• 5V, 10V and 15V Parametric Ratings

• Standardized, Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range, 100nA at 18V and +25oC

• Noise Margin (Over full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13A, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Applications

• Shift Registers

• Buffer/Storage Registers

• Pattern Generators

Description

CD40174BMS consists of six identical ‘D’-Type ﬂip-ﬂops

having independent DATA inputs. The CLOCK and CLEAR

inputs are common to all six units. Data is transferred to the

Q outputs on the positive going transition of the clock pulse.

All six ﬂip-ﬂops are simultaneously reset by a low level on the

CLEAR input.

The CD40174BMS is supplied in these 16 lead outline pack-

ages:

Braze Seal DIP H4T

Frit Seal DIP H1E

Ceramic Flatpack H6W

File Number 3359

December 1992

CD40174BMS

CMOS Hex ‘D’-Type Flip-Flop

7-1385

Speciﬁcations CD40174BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

Thermal Resistance . . . . . . . . . . . . . . . . θja θjc

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55oC to +100oC (Package Type D, F, K). . . . . .500mW

For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-2µA

2 +125oC - 200 µA

VDD = 18V, VIN = VDD or GND 3 -55oC-2µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA

2 +125oC -1000 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

2 +125oC - 1000 nA

VDD = 18V 3 -55oC - 100 nA

Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV

Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA

Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA

N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V

P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V

Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD/2 VOL <

VDD/2 V

VDD = 20V, VIN = VDD or GND 7 +25oC

VDD = 18V, VIN = VDD or GND 8A +125oC

VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

(Note 2) VIL5 VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

Input Voltage High

(Note 2) VIH5 VDD = 5V, VOH > 4.5V,

VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

Input Voltage Low

(Note 2) VIL15 VDD = 15V, VOH > 13.5V,

VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V

Input Voltage High

(Note 2) VIH15 VDD = 15V, VOH > 13.5V,

VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

3. For accuracy, voltage is measured differentially to VDD. Limit

is 0.050V max.

7-1386

Speciﬁcations CD40174BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (Note 1, 2) GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Propagation Delay

Clock to Output TPHL1

TPLH1 VDD = 5V, VIN = VDD or GND 9 +25oC - 300 ns

10, 11 +125oC, -55oC - 405 ns

Propagation Delay

CLEAR to Output TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

10, 11 +125oC, -55oC - 270 ns

Transition Time TTHL

TTLH VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

10, 11 +125oC, -55oC - 270 ns

Maximum Clock Input

Frequency FCL VDD = 5V, VIN = VDD or GND 9 +25oC 3.5 - MHz

10, 11 +125oC, -55oC 3.5/1.35 - MHz

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 1 µA

+125oC-30µA

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

+125oC-60µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

+125oC - 120 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC-50mV

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC-50mV

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

-55oC4.95 - V

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

-55oC9.95 - V

Output Current (Sink) IOL5B VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

7-1387

Speciﬁcations CD40174BMS

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V,

VOL < 1V 1, 2 +25oC, +125oC,

-55oC-3V

Input Voltage High VIH VDD = 10V, VOH > 9V,

VOL < 1V 1, 2 +25oC, +125oC,

-55oC+7 - V

Propagation Delay

Clock to Output TPHL1

TPLH1 VDD = 10V 1, 2, 3 +25oC - 140 ns

VDD = 15V 1, 2, 3 +25oC - 100 ns

Propagation Delay

CLEAR to Output TPHL2 VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

Transition Time TTHL

TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

Maximum Clock Input

Frequency FCL VDD = 10V 1, 2, 3 +25oC 6 - MHz

VDD = 15V 1, 2, 3 +25oC 8 - MHz

Minimum Data Setup

Time TS VDD = 5V 1, 2, 3 +25oC - 40 ns

VDD = 10V 1, 2, 3 +25oC - 20 ns

VDD = 15V 1, 2, 3 +25oC - 10 ns

Minimum Data Hold Time TH VDD = 5V 1, 2, 3 +25oC - 80 ns

VDD = 10V 1, 2, 3 +25oC - 40 ns

VDD = 15V 1, 2, 3 +25oC - 30 ns

Minimum Clock Pulse

Width TW VDD = 5V 1, 2, 3 +25oC - 130 ns

VDD = 10V 1, 2, 3 +25oC - 60 ns

VDD = 15V 1, 2, 3 +25oC - 40 ns

Maximum Clock Rise and

Fall Time TRCL

TFCL VDD = 5V 1, 2, 3, 4 +25oC15-µs

VDD = 10V 1, 2, 3, 4 +25oC15-µs

VDD = 15V 1, 2, 3, 4 +25oC15-µs

Minimum CLEAR

Removal Time TREM VDD = 5V 1, 2, 3 +25oC-0ns

VDD = 10V 1, 2, 3 +25oC-0ns

VDD = 15V 1, 2, 3 +25oC-0ns

Minimum CLEAR Pulse

Width TW VDD = 5V 1, 2, 3 +25oC - 100 ns

VDD = 10V 1, 2, 3 +25oC - 50 ns

VDD = 15V 1, 2, 3 +25oC - 40 ns

Input Capacitance CIN CLEAR 1, 2 +25oC - 40 pF

All others 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation

delay of the output of the driving stage for the estimated capacitive load.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

7-1388

Speciﬁcations CD40174BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

LIMITS

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA

N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V

N Threshold Voltage

Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V

P Threshold Voltage

Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

VDD/2 VOL <

VDD/2 V

VDD = 3V, VIN = VDD or GND

Propagation Delay Time TPHL

TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

+25oC

Limit

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-1 IDD ± 0.2µA

Output Current (Sink) IOL5 ± 20% x Pre-Test Reading

Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUP MIL-STD-883

METHOD GROUP A SUBGROUPS READ AND RECORD

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Final Test 100% 5004 2, 3, 8A, 8B, 10, 11

Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11

Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS MIL-STD-883

METHOD

TEST READ AND RECORD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

1389

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Speciﬁcations CD40174BMS

Logic Diagram

FIGURE 1. 1 OF 6 FLIP-FLOPS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION OPEN GROUND VDD 9V ± -0.5V

OSCILLATOR

50kHz 25kHz

Static Burn-In 1

(Note 1) 2, 5, 7, 10, 12, 15 1, 3, 4, 6, 8, 9, 11,

13, 14 16

Static Burn-In 2

(Note 1) 2, 5, 7, 10, 12, 15 8 1, 3, 4, 6, 9, 11,

13, 14, 16

Dynamic Burn-In

(Note 1) - 8 1, 16 2, 5, 7, 10, 12, 15 9 3, 4, 6, 11, 13, 14

Irradiation

(Note 2) 2, 5, 7, 10, 12, 15 8 1, 3, 4, 6, 9, 11,

13, 14, 16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

VDD = 10V ± 0.5V

TRUTH TABLE FOR 1 OF 6 FLIP-FLOPS

INPUTS OUTPUT

CLOCK DATA CLEAR Q

010

111

X1NC

XX00

1 = High Level

2 = Low Level X = Don’t Care

NC = No Change

VDD

VSS

CLCL

CL CL

3 (4, 6, 11, 13, 14) CL

CLR* 1

2 (5, 7, 10, 12, 15)

CLK* 9

* All inputs (terms 1, 3, 4, 6, 9, 11, 13, 14)

protected by COS/MOS protection network

7-1390

CD40174BMS

Typical Performance Curves

FIGURE 2. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF CLOCK FREQUENCY

AMBIENT TEMPERATURE (T A) = +25oC

LOAD CAPACITANCE (CL) (pF)

0 40 60 80 10020

100

150

200

SUPPLY VOLT AGE (VDD) = 5V

10V

15V

TRANSITION TIME (fTHL, fTLH) (ns)

10V

AMBIENT TEMPERATURE (T A) = +25oC

GATE-TO-SOURCE VOLT AGE (VGS) = 15V

0 5 10 15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

10V

AMBIENT TEMPERATURE (T A) = +25oC

GATE-TO-SOURCE VOLT AGE (VGS) = 15V

0 5 10 15

7.5

5.0

2.5

10.0

12.5

15.0

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

-10V

-15V

AMBIENT TEMPERATURE (T A) = +25oC

GATE-TO-SOURCE VOLT AGE (VGS) = -5V

-5

-10

-15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-20

-25

-30

0-5-10-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

-10V

-15V

AMBIENT TEMPERATURE (T A) = +25oC0

-5

-10

-15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0-5-10-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLT AGE (VGS) = -5V

1 10 102103104

2 4 68 2 4 68 2 4 68 2 4 68

103

104

105

102

AMBIENT TEMPERATURE (T A) = +25oC

SUPPLY VOLT AGE (VDD) = 15V

10V

CLOCK INPUT FREQUENCY (fCL) (kHz)

POWER DISSIPATION PER FLIP-FLOP (PD) (µW)

CL = 50pF

CL = 15pF

7-1391

CD40174BMS

FIGURE 8. TYPICAL PROPAGATION DELAY TIME (CLOCK TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE

Typical Performance Curves (Continued)

AMBIENT TEMPERATURE (T A) = +25oC

SUPPLY VOLT AGE (VDD) = 5V

10V

15V

LOAD CAPACITANCE (CL) (pF)

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

0 102030405060708090100

100

125

150

175

200

Waveform

FIGURE 9. DEFINITION OF SETUP, HOLD, PROPAGATION

DELAY, AND REMOVAL TIMES

CLOCK

INPUT

DATA

INPUT

OUTPUT

VDD

CLEAR

90%

50%

10%

VDD

50%

tr CL tf CL

tH(HL)* tH(LH)*

tSU(HL)*

tSU(LH)*

tTLH tTHL

tPHLtPLH

tREM

90%

50%

10%

VDD

*(LH) OR (HL) OPTIONAL

Pad Layout

DIMENSIONS AND PAD LAYOUT FOR CD40174BMSH

The photographs and dimensions of each CMOS chip represent a chip when

it is part of the wafer. When the wafer is separated into individual chips, the an-

gle of cleavage may vary with respect to the chip face for different chips. The

actual dimensions of the isolated chip, therefore, may differ slightly from the

nominal dimensions shown. The user should consider a tolerance of -3 mils to

+16 mils applicable to the nominal dimensions shown.

Dimension in parenthesis are in millimeters and are derived from the basic inch

dimensions as indicated. Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ−14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches