PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT PD161606 720 OUTPUTS TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR DESCRIPTION The PD161606 is a TFT-LCD source driver that includes display RAM. This driver has 720 outputs, a display RAM capacity of 115,200 bits (240 pixels x 3 bits x 96 lines + rendering flag) of partial display RAM. FEATURES * TFT-LCD driver with on-chip display RAM * Logic power supply voltage: 1.7 to 2.5 V (Generating inside a chip is also possible from power supply IC interface power supply) * CPU/RGB interface power supply voltage: 1.7 to 3.3 V * Gate driver power supply voltage: 1.7 to 3.3 V * Driver power supply voltage: 4.0 to 5.5 V * Display RAM: 240 x 3 x 96 bits * Driver outputs: 720 outputs * CPU interface: Three types of interfaces selectable 6-bit/16-bit/18-bit RGB interface i80/M68 parallel interface (selectable from 8-bit) 8-bit serial interface (SPI correspondence) * Colors: 262,144 colors/pixel * On-chip timing generator * On-chip oscillator ORDERING INFORMATION Part Number Package PD161606P Chip Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum on product quality, so please contact one of our sales representatives. The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. Not all products and/or types are availabe in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16789EJ2V0PM00 (2nd edition) Date Published March 2004 NS CP(K) Printed in Japan The mark shows major revised points. 2003 PD161606 CONTENTS 1. BLOCK DIAGRAM.....................................................................................................................................4 2. PIN CONFIGURATION (Pad Layout) ......................................................................................................5 3. PIN FUNCTIONS........................................................................................................................................9 3.1 Power Supply System Pins ............................................................................................................................... 9 3.2 Logic System Pins ........................................................................................................................................... 11 3.3 Driver Pins ........................................................................................................................................................ 13 3.4 Pins for Gate Control Interface Power Supply............................................................................................... 13 2 3.5 E PROM Control Pins ...................................................................................................................................... 14 3.6 Test or Other Pins ............................................................................................................................................ 14 4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS....................................15 5. DESCRIPTION OF FUNCTIONS .............................................................................................................17 5.1 Interface ............................................................................................................................................................ 17 5.1.1 Selection of interface type ...................................................................................................................... 17 5.1.2 RGB interface......................................................................................................................................... 18 5.1.3 i80/M68 Parallel interface....................................................................................................................... 23 5.1.4 Serial interface ....................................................................................................................................... 25 5.1.5 Chip select ............................................................................................................................................. 28 5.1.6 Access to display data RAM and internal registers ................................................................................ 28 5.1.7 PD161645 control serial interface ....................................................................................................... 34 5.2 Partial Display RAM ......................................................................................................................................... 35 5.2.1 X address circuit..................................................................................................................................... 35 5.2.2 Y address circuit..................................................................................................................................... 36 5.2.3 Arbitrary address area access (window access mode (WAS))............................................................... 38 5.3 Oscillator........................................................................................................................................................... 40 5.4 Display Timing Generator................................................................................................................................ 41 5.5 - Curve Correction Circuit ............................................................................................................................. 45 5.5.1 Amplitude adjustment with internal amplifier .......................................................................................... 46 5.5.2 Amplitude adjustment by bulit-in resistance ........................................................................................... 48 5.5.3 Inclination adjustment ............................................................................................................................ 49 5.5.4 Fine tuning adjustment........................................................................................................................... 50 5.6 Partial Display Function .................................................................................................................................. 51 5.7 Stand-by............................................................................................................................................................ 52 2 Preliminary Product Information S16789EJ2V0PM PD161606 5.7.1 Stand-by mode 1.................................................................................................................................... 52 5.7.2 Stand-by mode 2.................................................................................................................................... 53 6. POWER SUPPLY INJECTION/INTERCEPTION ....................................................................................57 6.1 PD161606 Power Supply Injection Setting Sequence Example ................................................................ 57 6.2 PD161606 Power Supply Interception Setting Sequence Example .......................................................... 61 7. E2PROM INTERFACE..............................................................................................................................62 7.1 The PD161606 and E2PROM Connection .................................................................................................... 62 7.2 Each Operation................................................................................................................................................. 63 8. RESET......................................................................................................................................................68 9. COMMAND...............................................................................................................................................71 9.1 Command List .................................................................................................................................................. 71 10. ELECTRICAL SPECIFICATIONS..........................................................................................................80 11. EXAMPLE OF THE PD161606 AND CPU CONNECTION ................................................................88 Preliminary Product Information S16789EJ2V0PM 3 PD161606 1. BLOCK DIAGRAM T.B.D. Remark T.B.D.: To be determined. 4 Preliminary Product Information S16789EJ2V0PM PD161606 2. PIN CONFIGURATION (Pad Layout) Chip size: 2.4 x 19.5 mm2 Bump size (output, including long side and short side): 90 x 26 m Bump size (input): 106 x 54 m 2 2 Alignment mark (mark center, unit: m) X Y AM1 1025 9575 AM2 1025 -9575 Alignment mark size 30m 40m 30m 30m 40m 30m Preliminary Product Information S16789EJ2V0PM 5 PD161606 Table 2-1. Pad Coordinate (1/3) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 6 PIN NAME DUMMY GSTB GCLK VCOUT EQ GOE2 GOE1 GSO GCS GSCLK DCCLK GRESET DUMMY DUMMY DUMMY VCC3 VCC3 VCC3 VCC3 VSS VSS VSS VSS VS VS VS VS VSS VSS VSS VSS VSS VSS VCOM EQ1 VCOM EQ2 VCOM EQ3 VCOM EQ4 VSG VSG VSG VSG CVNH1 CVNH2 CVPH1 CVPH2 CVNL1 CVNL2 CVPL1 CVPL2 DVSS BWS1 DVCC2 BWS0 DVSS PSX DVCC2 SSEL DVSS C86 DVCC2 CSEG DVSS SCLEG1 DVCC2 SCLEG0 DVSS RSEL DVCC2 ECS ESK EDI EDO DVSS /RD(E) /WR(R,/W) D7 D6 D5 D4 D3 D2 D1 D0 /CS RS SO SI SCL DVSS RGB25 RGB24 RGB23 RGB22 RGB21 RGB20 RGB15 RGB14 RGB13 RGB12 RGB11 X -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 Y 9330.00 9220.00 9110.00 9000.00 8890.00 8780.00 8670.00 8560.00 8450.00 8340.00 8230.00 8120.00 8010.00 7900.00 7790.00 7680.00 7570.00 7460.00 7350.00 7240.00 7130.00 7020.00 6910.00 6800.00 6690.00 6580.00 6470.00 6360.00 6250.00 6140.00 6030.00 5920.00 5810.00 5700.00 5590.00 5480.00 5370.00 5260.00 5150.00 5040.00 4930.00 4820.00 4710.00 4600.00 4490.00 4380.00 4270.00 4160.00 4050.00 3940.00 3830.00 3720.00 3610.00 3500.00 3390.00 3280.00 3170.00 3060.00 2950.00 2840.00 2730.00 2620.00 2510.00 2400.00 2290.00 2180.00 2070.00 1960.00 1850.00 1740.00 1630.00 1520.00 1410.00 1300.00 1190.00 1080.00 970.00 860.00 750.00 640.00 530.00 420.00 310.00 200.00 90.00 -20.00 -130.00 -240.00 -350.00 -460.00 -570.00 -680.00 -790.00 -900.00 -1010.00 -1120.00 -1230.00 -1340.00 -1450.00 -1560.00 PIN No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN NAME RGB10 RGB05 RGB04 RGB03 RGB02 RGB01 RGB00 HSYNC VSYNC DOTCLK /RESET TIN2 TIN1 TIN0 TESTO17 TESTO16 TESTO15 TESTO14 TESTO13 TESTO12 TESTO11 TESTO10 TESTO9 TESTO8 TESTO7 TESTO6 TESTO5 TESTO4 TESTO3 TESTO2 TESTO1 TESTO0 TOSC1SEL TOSC1IN DVCC2 DVSS OSC2SEL OSC2IN OSC2OUT VSS VSS VSS VSS VCC1 VCC1 VCC1 VCC1 SF VCC1 SF VCC2 SF VCC3 SF VCC4 VSS VSS VSS VSS VCC2 VCC2 VCC2 VCC2 VSTBY DVSS VS VS VS VS VSS VSS VSS VSS VSS VSS DUMMY DUMMY DUMMY S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 X -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -675.30 -630.30 -585.30 -540.30 -495.30 -450.30 -405.30 -360.30 -315.30 -270.30 -225.30 -180.30 -135.30 -90.30 -45.30 -0.30 44.70 89.70 134.70 179.70 224.70 269.70 314.70 359.70 404.70 449.70 494.70 539.70 Y -1670.00 -1780.00 -1890.00 -2000.00 -2110.00 -2220.00 -2330.00 -2440.00 -2550.00 -2660.00 -2770.00 -2880.00 -2990.00 -3100.00 -3210.00 -3320.00 -3430.00 -3540.00 -3650.00 -3760.00 -3870.00 -3980.00 -4090.00 -4200.00 -4310.00 -4420.00 -4530.00 -4640.00 -4750.00 -4860.00 -4970.00 -5080.00 -5190.00 -5300.00 -5410.00 -5520.00 -5630.00 -5740.00 -5850.00 -5960.00 -6070.00 -6180.00 -6290.00 -6400.00 -6510.00 -6620.00 -6730.00 -6840.00 -6950.00 -7060.00 -7170.00 -7280.00 -7390.00 -7500.00 -7610.00 -7720.00 -7830.00 -7940.00 -8050.00 -8160.00 -8270.00 -8380.00 -8490.00 -8600.00 -8710.00 -8820.00 -8930.00 -9040.00 -9150.00 -9260.00 -9370.00 -9480.00 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 Preliminary Product Information S16789EJ2V0PM PIN No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 PIN NAME S27 S28 S29 S30 DUMMY DUMMY S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 X 584.70 629.70 674.70 719.70 764.70 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 Y -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9254.00 -9226.00 -9198.00 -9170.00 -9142.00 -9114.00 -9086.00 -9058.00 -9030.00 -9002.00 -8974.00 -8946.00 -8918.00 -8890.00 -8862.00 -8834.00 -8806.00 -8778.00 -8750.00 -8722.00 -8694.00 -8666.00 -8638.00 -8610.00 -8582.00 -8554.00 -8526.00 -8498.00 -8470.00 -8442.00 -8414.00 -8386.00 -8358.00 -8330.00 -8302.00 -8274.00 -8246.00 -8218.00 -8190.00 -8162.00 -8134.00 -8106.00 -8078.00 -8050.00 -8022.00 -7994.00 -7966.00 -7938.00 -7910.00 -7882.00 -7854.00 -7826.00 -7798.00 -7770.00 -7742.00 -7714.00 -7686.00 -7658.00 -7630.00 -7602.00 -7574.00 -7546.00 -7518.00 -7490.00 -7462.00 -7434.00 -7406.00 -7378.00 -7350.00 -7322.00 -7294.00 -7266.00 -7238.00 -7210.00 -7182.00 -7154.00 -7126.00 -7098.00 -7070.00 -7042.00 -7014.00 -6986.00 -6958.00 -6930.00 -6902.00 -6874.00 -6846.00 -6818.00 -6790.00 -6762.00 -6734.00 -6706.00 -6678.00 -6650.00 -6622.00 PD161606 Table 2-1. Pad Coordinate (2/3) PIN No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 PIN NAME S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S159 S160 S161 S162 S163 S164 S165 S166 S167 S168 S169 S170 S171 S172 S173 S174 S175 S176 S177 S178 S179 S180 S181 S182 S183 S184 S185 S186 S187 S188 S189 S190 S191 S192 S193 S194 S195 S196 S197 S198 S199 S200 S201 S202 S203 S204 S205 S206 S207 S208 S209 S210 S211 S212 S213 S214 S215 S216 S217 S218 S219 S220 S221 S222 S223 S224 X 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 Y -6594.00 -6566.00 -6538.00 -6510.00 -6482.00 -6454.00 -6426.00 -6398.00 -6370.00 -6342.00 -6314.00 -6286.00 -6258.00 -6230.00 -6202.00 -6174.00 -6146.00 -6118.00 -6090.00 -6062.00 -6034.00 -6006.00 -5978.00 -5950.00 -5922.00 -5894.00 -5866.00 -5838.00 -5810.00 -5782.00 -5754.00 -5726.00 -5698.00 -5670.00 -5642.00 -5614.00 -5586.00 -5558.00 -5530.00 -5502.00 -5474.00 -5446.00 -5418.00 -5390.00 -5362.00 -5334.00 -5306.00 -5278.00 -5250.00 -5222.00 -5194.00 -5166.00 -5138.00 -5110.00 -5082.00 -5054.00 -5026.00 -4998.00 -4970.00 -4942.00 -4914.00 -4886.00 -4858.00 -4830.00 -4802.00 -4774.00 -4746.00 -4718.00 -4690.00 -4662.00 -4634.00 -4606.00 -4578.00 -4550.00 -4522.00 -4494.00 -4466.00 -4438.00 -4410.00 -4382.00 -4354.00 -4326.00 -4298.00 -4270.00 -4242.00 -4214.00 -4186.00 -4158.00 -4130.00 -4102.00 -4074.00 -4046.00 -4018.00 -3990.00 -3962.00 -3934.00 -3906.00 -3878.00 -3850.00 -3822.00 PIN No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 PIN NAME S225 S226 S227 S228 S229 S230 S231 S232 S233 S234 S235 S236 S237 S238 S239 S240 S241 S242 S243 S244 S245 S246 S247 S248 S249 S250 S251 S252 S253 S254 S255 S256 S257 S258 S259 S260 S261 S262 S263 S264 S265 S266 S267 S268 S269 S270 S271 S272 S273 S274 S275 S276 S277 S278 S279 S280 S281 S282 S283 S284 S285 S286 S287 S288 S289 S290 S291 S292 S293 S294 S295 S296 S297 S298 S299 S300 S301 S302 S303 S304 S305 S306 S307 S308 S309 S310 S311 S312 S313 S314 S315 S316 S317 S318 S319 S320 S321 S322 S323 S324 X 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 Y -3794.00 -3766.00 -3738.00 -3710.00 -3682.00 -3654.00 -3626.00 -3598.00 -3570.00 -3542.00 -3514.00 -3486.00 -3458.00 -3430.00 -3402.00 -3374.00 -3346.00 -3318.00 -3290.00 -3262.00 -3234.00 -3206.00 -3178.00 -3150.00 -3122.00 -3094.00 -3066.00 -3038.00 -3010.00 -2982.00 -2954.00 -2926.00 -2898.00 -2870.00 -2842.00 -2814.00 -2786.00 -2758.00 -2730.00 -2702.00 -2674.00 -2646.00 -2618.00 -2590.00 -2562.00 -2534.00 -2506.00 -2478.00 -2450.00 -2422.00 -2394.00 -2366.00 -2338.00 -2310.00 -2282.00 -2254.00 -2226.00 -2198.00 -2170.00 -2142.00 -2114.00 -2086.00 -2058.00 -2030.00 -2002.00 -1974.00 -1946.00 -1918.00 -1890.00 -1862.00 -1834.00 -1806.00 -1778.00 -1750.00 -1722.00 -1694.00 -1666.00 -1638.00 -1610.00 -1582.00 -1554.00 -1526.00 -1498.00 -1470.00 -1442.00 -1414.00 -1386.00 -1358.00 -1330.00 -1302.00 -1274.00 -1246.00 -1218.00 -1190.00 -1162.00 -1134.00 -1106.00 -1078.00 -1050.00 -1022.00 Preliminary Product Information S16789EJ2V0PM PIN No. 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 PIN NAME S325 S326 S327 S328 S329 S330 S331 S332 S333 S334 S335 S336 S337 S338 S339 S340 S341 S342 S343 S344 S345 S346 S347 S348 S349 S350 S351 S352 S353 S354 S355 S356 S357 S358 S359 S360 S361 S362 S363 S364 S365 S366 S367 S368 S369 S370 S371 S372 S373 S374 S375 S376 S377 S378 S379 S380 S381 S382 S383 S384 S385 S386 S387 S388 S389 S390 S391 S392 S393 S394 S395 S396 S397 S398 S399 S400 S401 S402 S403 S404 S405 S406 S407 S408 S409 S410 S411 S412 S413 S414 S415 S416 S417 S418 S419 S420 S421 S422 S423 S424 X 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 Y -994.00 -966.00 -938.00 -910.00 -882.00 -854.00 -826.00 -798.00 -770.00 -742.00 -714.00 -686.00 -658.00 -630.00 -602.00 -574.00 -546.00 -518.00 -490.00 -462.00 -434.00 -406.00 -378.00 -350.00 -322.00 -294.00 -266.00 -238.00 -210.00 -182.00 -154.00 -126.00 -98.00 -70.00 -42.00 -14.00 14.00 42.00 70.00 98.00 126.00 154.00 182.00 210.00 238.00 266.00 294.00 322.00 350.00 378.00 406.00 434.00 462.00 490.00 518.00 546.00 574.00 602.00 630.00 658.00 686.00 714.00 742.00 770.00 798.00 826.00 854.00 882.00 910.00 938.00 966.00 994.00 1022.00 1050.00 1078.00 1106.00 1134.00 1162.00 1190.00 1218.00 1246.00 1274.00 1302.00 1330.00 1358.00 1386.00 1414.00 1442.00 1470.00 1498.00 1526.00 1554.00 1582.00 1610.00 1638.00 1666.00 1694.00 1722.00 1750.00 1778.00 7 PD161606 Table 2-1. Pad Coordinate (3/3) PIN No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 8 PIN NAME S425 S426 S427 S428 S429 S430 S431 S432 S433 S434 S435 S436 S437 S438 S439 S440 S441 S442 S443 S444 S445 S446 S447 S448 S449 S450 S451 S452 S453 S454 S455 S456 S457 S458 S459 S460 S461 S462 S463 S464 S465 S466 S467 S468 S469 S470 S471 S472 S473 S474 S475 S476 S477 S478 S479 S480 S481 S482 S483 S484 S485 S486 S487 S488 S489 S490 S491 S492 S493 S494 S495 S496 S497 S498 S499 S500 S501 S502 S503 S504 S505 S506 S507 S508 S509 S510 S511 S512 S513 S514 S515 S516 S517 S518 S519 S520 S521 S522 S523 S524 X 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 Y 1806.00 1834.00 1862.00 1890.00 1918.00 1946.00 1974.00 2002.00 2030.00 2058.00 2086.00 2114.00 2142.00 2170.00 2198.00 2226.00 2254.00 2282.00 2310.00 2338.00 2366.00 2394.00 2422.00 2450.00 2478.00 2506.00 2534.00 2562.00 2590.00 2618.00 2646.00 2674.00 2702.00 2730.00 2758.00 2786.00 2814.00 2842.00 2870.00 2898.00 2926.00 2954.00 2982.00 3010.00 3038.00 3066.00 3094.00 3122.00 3150.00 3178.00 3206.00 3234.00 3262.00 3290.00 3318.00 3346.00 3374.00 3402.00 3430.00 3458.00 3486.00 3514.00 3542.00 3570.00 3598.00 3626.00 3654.00 3682.00 3710.00 3738.00 3766.00 3794.00 3822.00 3850.00 3878.00 3906.00 3934.00 3962.00 3990.00 4018.00 4046.00 4074.00 4102.00 4130.00 4158.00 4186.00 4214.00 4242.00 4270.00 4298.00 4326.00 4354.00 4382.00 4410.00 4438.00 4466.00 4494.00 4522.00 4550.00 4578.00 PIN No. 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 PIN NAME S525 S526 S527 S528 S529 S530 S531 S532 S533 S534 S535 S536 S537 S538 S539 S540 S541 S542 S543 S544 S545 S546 S547 S548 S549 S550 S551 S552 S553 S554 S555 S556 S557 S558 S559 S560 S561 S562 S563 S564 S565 S566 S567 S568 S569 S570 S571 S572 S573 S574 S575 S576 S577 S578 S579 S580 S581 S582 S583 S584 S585 S586 S587 S588 S589 S590 S591 S592 S593 S594 S595 S596 S597 S598 S599 S600 S601 S602 S603 S604 S605 S606 S607 S608 S609 S610 S611 S612 S613 S614 S615 S616 S617 S618 S619 S620 S621 S622 S623 S624 X 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 Y 4606.00 4634.00 4662.00 4690.00 4718.00 4746.00 4774.00 4802.00 4830.00 4858.00 4886.00 4914.00 4942.00 4970.00 4998.00 5026.00 5054.00 5082.00 5110.00 5138.00 5166.00 5194.00 5222.00 5250.00 5278.00 5306.00 5334.00 5362.00 5390.00 5418.00 5446.00 5474.00 5502.00 5530.00 5558.00 5586.00 5614.00 5642.00 5670.00 5698.00 5726.00 5754.00 5782.00 5810.00 5838.00 5866.00 5894.00 5922.00 5950.00 5978.00 6006.00 6034.00 6062.00 6090.00 6118.00 6146.00 6174.00 6202.00 6230.00 6258.00 6286.00 6314.00 6342.00 6370.00 6398.00 6426.00 6454.00 6482.00 6510.00 6538.00 6566.00 6594.00 6622.00 6650.00 6678.00 6706.00 6734.00 6762.00 6790.00 6818.00 6846.00 6874.00 6902.00 6930.00 6958.00 6986.00 7014.00 7042.00 7070.00 7098.00 7126.00 7154.00 7182.00 7210.00 7238.00 7266.00 7294.00 7322.00 7350.00 7378.00 Preliminary Product Information S16789EJ2V0PM PIN No. 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 PIN NAME S625 S626 S627 S628 S629 S630 S631 S632 S633 S634 S635 S636 S637 S638 S639 S640 S641 S642 S643 S644 S645 S646 S647 S648 S649 S650 S651 S652 S653 S654 S655 S656 S657 S658 S659 S660 S661 S662 S663 S664 S665 S666 S667 S668 S669 S670 S671 S672 S673 S674 S675 S676 S677 S678 S679 S680 S681 S682 S683 S684 S685 S686 S687 S688 S689 S690 DUMMY DUMMY DUMMY S691 S692 S693 S694 S695 S696 S697 S698 S699 S700 S701 S702 S703 S704 S705 S706 S707 S708 S709 S710 S711 S712 S713 S714 S715 S716 S717 S718 S719 S720 DUMMY DUMMY X 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 764.70 719.70 674.70 629.70 584.70 539.70 494.70 449.70 404.70 359.70 314.70 269.70 224.70 179.70 134.70 89.70 44.70 -0.30 -45.30 -90.30 -135.30 -180.30 -225.30 -270.30 -315.30 -360.30 -405.30 -450.30 -495.30 -540.30 -585.30 -630.30 -675.30 Y 7406.00 7434.00 7462.00 7490.00 7518.00 7546.00 7574.00 7602.00 7630.00 7658.00 7686.00 7714.00 7742.00 7770.00 7798.00 7826.00 7854.00 7882.00 7910.00 7938.00 7966.00 7994.00 8022.00 8050.00 8078.00 8106.00 8134.00 8162.00 8190.00 8218.00 8246.00 8274.00 8302.00 8330.00 8358.00 8386.00 8414.00 8442.00 8470.00 8498.00 8526.00 8554.00 8582.00 8610.00 8638.00 8666.00 8694.00 8722.00 8750.00 8778.00 8806.00 8834.00 8862.00 8890.00 8918.00 8946.00 8974.00 9002.00 9030.00 9058.00 9086.00 9114.00 9142.00 9170.00 9198.00 9226.00 9254.00 9282.00 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 PD161606 3. PIN FUNCTIONS 3.1 Power Supply System Pins Symbol VCC1 Pin Name Logic power supply Pad No. 144 to 147 I/O - Function This is the power supply for the logic circuit. When VSTBY = H, the power supply voltage input from this pin is directly used as the power supply voltage of the internal logic circuit. When VSTBY = L, the voltage output to the SF_VCC1 pin is used as the logic power supply voltage, so connect this pin to the SF_VCC1 pin. For details, refer to Figure 3-1. 156 to 159 - This is the power supply pin for the CPU/RGB interface. Gate interface power supply 16 to 19 - This is the power supply pin for the gate driver interface. Driver power supply 24 to 27, - This is the power supply pin for the driver circuit. VCC2 CPU/RGB interface power VCC3 VS supply 162 to 165 VSC - power supply 38 to 41 - This is the power supply pin for the - circuit. VSS Ground 20 to 23, - This is the ground pin for the logic circuit, logic interface circuit, 28 to 33, source driver circuit, gate control circuit, and power supply control 140 to 143, circuit. 152 to 155, 166 to 171 SF_VCC1 Internal logic power supply 148 to 151 Output When VSTBY = L, connect a capacitor between this pin and VSS. For generation amplifier output VSTBY details, refer to Figure 3-1. Logic power supply generation 160 Input control Select the existence of voltage supply of power supply for logic circuits. VSTBY = L: With no voltage supply necessity for VCC1 VSTBY = H: VCC1 needs to be voltage supplied DVSS Mode setting 50, 54, 58, 62, - Pull-down power supply pin for mode setting. - Pull-up power supply pin for mode setting. 66, 73, 89, 136, 161 DVCC2 Mode setting 52, 56, 60, 64, 68, 135 Preliminary Product Information S16789EJ2V0PM 9 PD161606 Figure 3-1. Supplies of Power Supply [When using IC regulator for logic circuit] Usage conditions: VCC2 = 2.5 to 3.3 V, VCC3 = 1.7 to 3.3 V VCC3 On-chip power supply gate Dr interface circuit VCC2 2.5 to 3.3 V CPU/RGB Interface circuit VCC1 SF_VCC1 1.7 to 2.35 V IC internal logic circuit power supply VSTBY Regulator ON [When not using IC regulator for logic circuit] Usage conditions: VCC1 = 1.7 to 2.5 V, VCC2 = 1.7 to 3.3 V, VCC3 = 1.7 to 3.3 V, VCC1VCC2 VCC3 2.5 to 3.3 V On-chip power supply gate Dr interface circuit VCC2 CPU/RGB Interface circuit 1.7 to 2.5 V Open VCC1 SF_VCC1 IC internal logic circuit power supply VSTBY Regulator OFF 10 Preliminary Product Information S16789EJ2V0PM PD161606 3.2 Logic System Pins Symbol Pin Name (1/2) Pad No. BWS0, RGB interface bus width 53, BWS1 selection 51 PSX CPU interface mode 55 I/O Input Function This pin selects the bus width of the RGB interface. BWS1 L L H H Input selection BWS0 L H L H RGB interface bus width 18 bits 16 bits 6 bits Setting prohibited This pin selects the mode of the CPU interface. L: Parallel interface H: Serial interface /CS Chip select 84 Input This pin is used for chip select signals. When /CS = active level, the chip is active and can perform data I/O operations including command and data I/O. CSEG Chip select polarity 61 Input selection This selects active level of chip select (/CS). CSEG = L: Low level CSEG = H: High level /RESET Reset 111 Input When /RESET is L, an internal reset is performed. The reset operation is executed at the /RESET signal level. Be sure to perform reset via this pin at power application. RSEL Reset switch 67 Input Switches the effective range for hard reset for the registers. L H /RD Read (Enable) 74 Input (E) Hard reset Don't perform reset for registers. Perform reset for registers. Command reset Perform reset for registers. Perform reset for registers. When i80 series parallel data transfer (/RD) has been selected, the signal at this pin is used to enable read operations. Data is output to the data bus only when this pin is low. When M68 series parallel data transfer (E) has been selected, the signal at this pin is used to enable read/write operations. /WR Write (R, /W) (Read/write) 75 Input When i80 series parallel data transfer (/WR) has been selected, the signal at this pin is used to enable write operations. When M68 series parallel data transfer (R,/W) has been selected, this pin is used to determine the direction of data transfer. L: Write H: Read C86 Select interface 59 Input This pin is used to switch between interface modes (i80 series CPU or M68 series CPU). L: Selects i80 series CPU mode H: Selects M68 series CPU mode D0 to D7 Data bus 83 to 76 I/O These pins comprise 8-bit bi-directional data. When the chip is not selected, D0 to D7 are in high impedance mode. SI Serial input 87 Input SO Serial output 86 Output This pin is data input of serial interface. This pin is data output of serial interface. SCL Serial clock 88 Input This pin is clock input of serial interface. Remark /xxx indicates active low signal. Preliminary Product Information S16789EJ2V0PM 11 PD161606 (2/2) Symbol SCLEG0 Pin Name SCL data I/O edge Pad No. 65 I/O Input select SCLEG1 SCL polarity select Function Selects the serial clock edge for data I/O via the serial interface. For details, refer to Table 5-5. 63 Input Selects the active level of the serial clock (SCL) for the serial interface. SCLEG1 = L: Low level (high-level start) SCLEG1 = H: High level (low-level start) SSEL Serial interface mode 57 Input select Selects the serial interface mode. SSEL = L: Serial interface 1 SSEL = H: Serial interface 2 RS Data/command select 85 Input This pin is used in serial interface 1. When parallel data transfer has been selected, this pin is usually connected to the least significant bit of the standard CPU address bus and is used to distinguish between data from display data and commands. RS = L: Indicates that data from D0 to D7 is commands. RS = H: Indicates that data from D0 to D7 is display data. HSYNC Horizontal sync signal 108 Input This is the horizontal sync signal of the RGB interface. VSYNC Vertical sync signal 109 Input This is the vertical sync signal of the RGB interface. DOTCLK Dot clock 110 Input This is the dot clock signal of the RGB interface. RGB00 to RGB05, Data bus 107 to 102, Input These pins are RGB interface data signal. RGB10 to RGB15, 101 to 96, RGB20 to RGB25 95 to 90 OSC2SEL Oscillation signal select 137 Input This is the oscillation signal selection pin. L: Selects CR internal oscillator. H: Selects external resistor connected oscillator. OSC2IN OSC2OUT Oscillation signal 138 Input 139 Output These are the oscillation signal pins. OSCEL = H: Connect a resistor between the OSCIN pin and OSCOUT pin. For the resistance values to be used as a guide, refer to the electrical characteristics. OSCEL = L: Leave OSCIN and OSCOUT open. 12 Preliminary Product Information S16789EJ2V0PM PD161606 3.3 Driver Pins Symbol Pin Name S1 to S720 Source output Pad No. I/O 175 to 204, Output Function These pins are source output pins. 207 to 866, 870 to 899 - Operational amplifier output pins for -correction. CVPH1, CVPH2, Reference power 44, 45, CVPL1, CVPL2, supply pin for - 48, 49, Normally a capacitor of 1 F or greater is connected to these pins. CVNH1, CVNH2, correction power 42, 43, Leave these pins open when not using amplifier for - correction. CVNL1, CVNL2 supply 46, 47 3.4 Pins for Gate Driver Control Internal Power Supply Symbol Pin Name Pad No. I/O Function GCLK Gate driver CLK output 3 Output This is the CLK output to the gate driver. GSTB Gate driver STB output 2 Output Connect this pin to the STVR pin of the gate driver. GOE1 Gate driver OE1 output 7 Output This is the OE1 output pin to the gate driver. GOE2 Gate driver OE2 output 6 Output This is the OE2 output pin to the gate driver. VCOUT Square wave signal output 4 Output Outputs the square wave signal for common modulation of VP-P voltage 0 V to VCC3. GCS Chip select for gate driver 9 Output This is chip select for the gate driver serial interface. 10 Output This is the serial clock for the gate driver serial interface. 8 Output This is the serial data output for the gate driver serial interface. 12 Output This is the reset output for the gate driver serial interface. interface GSCLK Serial clock for gate driver interface GSO Serial data output for gate driver interface GRESET Reset output for gate driver interface DCCLK Boost clock output 11 Output Outputs the DC/DC converter boost clock. EQ Equalize control 5 Output Equalize control pin. VCOM_EQ1 to VCOM pin for equalize 34 to 37 VCOM_EQ4 control Input Pin used for equalize control. Preliminary Product Information S16789EJ2V0PM 13 PD161606 3.5 E2PROM Control Pins Symbol ECS Pin Name Chip select for Pad No. 69 I/O Function Output 2 2 This is the chip select for the E PROM interface. 2 E PROM interface E PROM is made active by outputting ECS = H, following which data transmission is performed. 2 Connect this pin to CS (chip select pin) of the E PROM. ESK Serial clock for 70 Output 2 2 This is the CLK for the E PROM interface. 2 E PROM interface Data is output from EDO to the E PROM at the rising edge of ESK. 2 Connect this pin to CLK (shift clock pin) of the E PROM EDI Serial data input for 71 Input 2 2 This is the data input for the E PROM interface. 2 E PROM interface This pin is used for E PROM data read. 2 Connect this pin to DOUT (data out pin) of the E PROM EDO Serial data output for 72 Output 2 2 This is the data output for the E PROM. 2 E PROM interface Data is output to E PROM. 2 Connect this pin to DIN (data in pin) of the E PROM. 3.6 Test or Other Pins Symbol Pin Name Pad No. TOUT0 to TOUT17 Test output 132 to 115 TIN0 to TIN2 Test input 114 to 112, I/O Function Output This is output pin when IC is in test mode. Normally, leave it open. Input This is input pin when IC is in test mode. Normally, leave it open or connected it to VSS. TOSC1IN Test input 134 Input This is input pin when IC is in test mode. Normally, leave it open or connected it to VSS. TOSC1SEL Test input 133 Input This is input pin when IC is in test mode. Normally, leave it open or connected it to VSS. DUMMY Dummy 1, 13 to 15, - Dummy pin 172 to 174, 205, 206, 867 to 869, 900, 901 14 Preliminary Product Information S16789EJ2V0PM PD161606 4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The I/O circuit types of each pin and recommended connection of unused pins are described below. (1/2) Pin Name Recommended Connection of Unused Pins Input Type I/O Power Supply BWS0, BWS1 Schmitt trigger Input VCC2 Mode setting pin O PSX Schmitt trigger Input VCC2 Mode setting pin O Schmitt trigger Input VCC2 Connect this pin to VCC2 and VSS when CSEG = L and - Schmitt trigger Input VCC2 Mode setting pin O Schmitt trigger Input VCC2 Always reset on power application - Schmitt trigger Input VCC2 Mode setting pin O Schmitt trigger Input VCC2 - Connect to VCC2 or VSS - Schmitt trigger Input VCC2 - - - D0 to D7 Schmitt trigger I/O VCC2 - Leave open - C86 Schmitt trigger Input VCC2 Mode setting pin Connect to VCC2 or VSS O SI, SCL Schmitt trigger Input VCC2 Connect to VCC2 or VSS - - Output VCC2 Leave open SCLEG0, SCLEG1 Schmitt trigger Input VCC2 Connect to VCC2 or VSS Mode setting pin O SSEL Schmitt trigger Input VCC2 Connect to VCC2 or VSS Mode setting pin O Schmitt trigger Input VCC2 Register setting pin - Schmitt trigger Input VCC2 Connect to VCC2 or VSS - Schmitt trigger Input VCC2 Connect to VCC2 or VSS - Schmitt trigger Input VCC2 Connect to VCC2 or VSS - Schmitt trigger Input VCC2 Leave this pin open. - /CS Parallel Interface Serial Interface Note CSEG = H, respectively. CSEG /RESET RSEL /RD (E) /WR (R,/W) SO RS HSYNC VSYNC DOTCLK RGB00 to RGB05, RGB10 to RGB15, - - The unused pins are as follows. RGB20 to RGB25 *Unused pins in case of 6-bit interface: RGB10 to RGB15, RGB20 to RGB25 *Unused pins in case of 16-bit interface: RGB00, RGB20 OSC2IN OSC2OUT OSC2SEL - Input VCC2 Leave open - - Output VCC2 Leave open - Schmitt trigger Input VCC2 Connect to VSS - Note O: Connect to VCC2 or VSS, depending on the mode selected. Preliminary Product Information S16789EJ2V0PM 15 PD161606 (2/2) Pin Name Recommended Connection of Unused Pins Input Type I/O Power Supply - Output VCC3 Leave open - - Output VCC3 Leave open - - Output VCC3 Leave open - - Output VCC3 Leave open - - Output VCC3 Leave open - - Output VCC3 Leave open - GSCLK - Output VCC3 Leave open - GSO - Output VCC3 Leave open - GRESET - Output VCC3 Leave open - DCCLK - Output VCC3 Leave open - EQ - Output VCC3 Leave open - VCOM_EQ - Input VS Leave open - ECS - Output VCC2 Leave open - ESK - Output VCC2 Leave open - EDI Schmitt trigger Input VCC2 Leave open - EDO - Output VCC2 Leave open - S1 to S720 - Output VS Leave open - Schmitt trigger Input VCC2 Mode setting pin O - Output VCC2 Leave open - TIN0 to TIN2 Schmitt trigger Input VCC2 Leave open or Connect to VSS - TOSC1IN Schmitt trigger Input VCC2 Leave open or Connect to VSS - TOSC1SEL Schmitt trigger Input VCC2 Leave open or Connect to VSS - GCLK GSTB GOE1 GOE2 VCOUT GCS VSTBY TOUT0 to TOUT17 Parallel Interface Note O: Connect to VCC2 or VSS, depending on the mode selected. 16 Preliminary Product Information S16789EJ2V0PM Serial Interface Note PD161606 5. DESCRIPTION OF FUNCTIONS 5.1 Interface 5.1.1 Selection of interface type The PD161606 can transfer data using the RGB interface (18/16/6-bit), i80/M68 parallel interface (8-bit), or serial interface (8-bit), or serial interface (8-bit). The modes listed in the following table can be selected by setting the PSX, BWS0, BWS1, and SSEL pins. The i80/M68 parallel interface allows writing and reading to/from both data RAM and registers. The serial interface allows writing to both display data RAM and registers, and reading of registers. The RGB interface allows display data input. Table 5-1. PSX L SSEL BWS0 BWS1 L L H L X Mode RS /RD (E) /WR (R,/W) C86 D7 to D0 SI, SCLK SI RGB RGB00 to RGB25 RGB 8-bit 16-bit H RGB00 to RGB25 RGB00 to RGB25 18-bit parallel L /CS /CS RS /RD (E) /WR (R,/W) C86 D7 to D0 (RGB00, RGB20 is X Note1 X Note1 open) RGB00 to RGB05 RGB (RGB10 to RGB15, 6-bit RGB20 to RGB25 is open) L L H L L RGB RGB00 to RGB25 RGB 8-bit 16-bit Serial1 L RGB00 to RGB25 18-bit H /CS RS X Note1 R,/W X Note1 Hi-Z Note2 SI, SCL (RGB00, RGB20 is SI open) RGB00 to RGB05 RGB (RGB10 to RGB15, 6-bit RGB20 to RGB25 is open) H L L H L H RGB H RGB00 to RGB25 RGB 8-bit 16-bit Serial2 L RGB00 to RGB25 18-bit /CS X Note1 X Note1 X Note1 X Note1 Hi-Z Note2 SI, SCL (RGB00, RGB20 is SI open) RGB00 to RGB05 RGB (RGB10 to RGB15, 6-bit RGB20 to RGB25 is open) Other the above Setting prohibited Notes1. Connect to VCC2 or VSS. 2. Hi-Z: High impedance. Leave open. Preliminary Product Information S16789EJ2V0PM 17 PD161606 5.1.2 RGB interface The PD161606 inputs display data from the DOTCLK, HSYNC, VSYNC, RGB00 to RGB05, RGB10 to RGB15, and RGB20 to RGB25 pins. The horizontal interval back porch is set with R75, and the vertical interval back porch with R76. 6-bit, 16-bit, and 18-bit as the data bus width for the RGB interface. Selection is performed with the BWS0 and BWS1 pins. When the 6-bit bus width is selected, the back porch, HSYNC width, etc., must be controlled in units of 3 DOTCLK. Table 5-2. Data Bus Width Selection BWS1 BWS0 Data Bus Width L L 18-bit L H 16-bit H L 6-bit The operation sequence is as follows (when DCKEG = L, HSEG = L, VSEG = L). Figure 5-1 shows the timing chart for when the 16-bit or 18-bit bus width is selected. Start VSYNC = 0, HSYNC = 0 1: Vertical back porch count reset, line count reset VSYNC = 1, HSYNC = 0 1: Vertical back porch count +1 The value of Vertical back porch counter is subtracted from the value (tVBP) set to the back porch of Vertical period. tVBP - Vertical back porch count number = not 0 =0 HSYNC = 0, DOTCLK = 0 1: Horizontal back porch count reset HSYNC = 1, DOTCLK = 0 1: Horizontal back porch count+1 The value of horizontal back porch counter is subtracted from the value (tHBP) set to the back porch of horizontal period. tHBP - horizontal back porch count number = not 0 =0 It is taking in about the first data at the rising edge of the next DOTCLK. Data is taken in by 240 clocks (data is disregarded after 241 clocks). The data taken in by HSYNC = 10 is latched to the output stage. VSYNC = 0 0 Remark As for low active and DOTCLK, VSYNC and HSYNC latch data by the rising edge. 18 Preliminary Product Information S16789EJ2V0PM PD161606 Figure 5-1. RGB Interface Timing Chart (DCKEG = H, HSEG = H, VSEG = L) VSYNC tVSS tVSH 1 line period tVB 1 2 3 4 HSYNC RGB 05 to RGB 00 RGB 15 to RGB 10 RGB 25 to RGB 20 Invalid Invalid 1st line RGB 05 to RGB 00 RGB 15 to RGB 10 RGB 25 to RGB 20 Last line Invalid Invalid 1st pixel 2nd pixel Last pixel HSYNC tHSS 1 pixel period tHH tHSH 1 2 3 DCK RGB 05 to RGB 00 RGB 15 to RGB 10 RGB 25 to RGB 20 Invalid Invalid 1st pixel Last pixel t VB = vertical back porch period t HB = horizontal back porch period Preliminary Product Information S16789EJ2V0PM 19 PD161606 The relationships between the input data and the various source output pins for each bus width are as follows. Figure 5-2. Relationship between Input Data and Source Output (16-/18-bit Bus Width) [16-/18-bit bus width] <ADC = 0> Source output S1 S2 S3 S4 S5 S6 S7 S8 Data bus RGB20 to RGB10 to RGB00 to RGB20 to RGB10 to RGB00 to RGB20 to RGB10 to RGB25 Note2 Receiving RGB15 RGB05 Note1 RGB25 Note2 1st pixel RGB15 RGB05 Note1 RGB25 Note2 2nd pixel RGB15 3rd pixel order S715 S716 S717 S718 S718 S720 RGB20 to RGB10 to RGB00 to RGB20 to RGB10 to RGB00 to RGB25 Note2 RGB15 RGB05 Note1 RGB25 Note2 239th pixel RGB15 RGB05 Note1 240th pixel <ADC = 1> Source output S1 S2 S3 S4 S5 S6 S7 S8 Data bus RGB00 to RGB10 to RGB20 to RGB00 to RGB10 to RGB20 to RGB00 to RGB10 to RGB05 Receiving Note1 RGB15 RGB25 Note2 RGB05 Note1 240th pixel RGB15 RGB25 Note2 239th pixel RGB05 Note1 RGB15 238th pixel order S715 S716 RGB00 to RGB10 to RGB05 Note1 RGB15 S717 RGB20 to RGB25 Note2 2nd pixel S718 S718 RGB00 to RGB10 to RGB05 Note1 RGB15 S720 RGB20 to RGB25 Note2 1st pixel Notes 1. When the 16-bit bus width is selected, RGB01 to RGB05 are used. When the 16-bit width is selected, data input to RGB00 need not be performed, but amp output is performed for data input to RGB05, because this is regarded as data input. 2. When the 16-bit bus width is selected, RGB21 to RGB25 are used. When the 16-bit width is selected, data input to RGB20 need not be performed, but amp output is performed for data input to RGB25, because this is regarded as data input. 20 Preliminary Product Information S16789EJ2V0PM PD161606 Figure 5-3. Relationship between Input Data and Source Output (6-bit bus width) [6-bit bus width] <ADC = 0> Source output S1 S2 S3 S4 S5 S6 S7 S8 Data bus RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB05 RGB05 RGB05 RGB05 RGB05 RGB05 RGB05 RGB05 Receiving 1st pixel 2nd pixel 3rd pixel order S715 S716 S717 S718 S718 S720 RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB05 RGB05 RGB05 RGB05 RGB05 RGB05 239th pixel 240th pixel <ADC = 1> Source output S1 S2 S3 S4 S5 S6 S7 S8 Data bus RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB05 RGB05 RGB05 RGB05 RGB05 RGB05 RGB05 RGB05 Receiving 240th pixel 239th pixel 238th pixel order S715 S716 S717 S718 S718 S720 RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB00 to RGB05 RGB05 RGB05 RGB05 RGB05 RGB05 2nd pixel 1st pixel The PD161606 contains on-chip partial RAM (3-bit/1-pixel). In addition to the data input form the RGB interface, the partial RAM area specified by registers R15 to R22 can also be displayed, by setting the R0 register, OSD = 1. Preliminary Product Information S16789EJ2V0PM 21 PD161606 [Example when using RGB Interface] RGB interface input data Partial display data RAM 10 / 23 [TUE] 10:35 R15: Partial RAM display area 1 start Y address R16: Partial RAM display area 1 line count R19: Partial RAM display area 2 start Y address R20: Partial RAM display area 2 line count Actually display screen 10 / 23 [TUE] 10:35 RGB interface start line (Setting by R60 register) Display data RAM area i80/M68 interface or It rewrites by serial interface RGB interface through display mode access area RGB interface end line (Setting by R61 register) <Cautions regarding use of RGB interface> <1> Be sure to input data for each frame as the data input from the RGB interface. <2> When switching to the partial mode, input at least 1 frame's worth of data after issuing the mode switching command. <3> When switching to the stand-by mode, input 1 frame's worth of data in the case of stand-by mode1, and input 4 frame's worth of data in the case of stand-by mode 2. Mode transition flows (1) Normal display mode To partial display mode (display clock: internal oscillation) DTY = 1 Wait time 1 (partial display mode transition) Data input stop "Normal display mode" (2) Partial display mode Normal display mode (display clock: DOTCLK) (3) Normal display mode To stand-by mode (4) Stand-by mode To normal display mode (stand-by release) Data input start DTY = 0 STBY = 1 Wait time 1 (STBSEL = 0) Wait time 2 (STBSEL = 1) Data input start STBY = 0 "Normal display mode" (stand-by mode transition) Data input stop "Stand-by mode" Wait time 1: Please secure sufficient time equal to 1 frame or more. Wait time 2: Please secure sufficient time equal to 4 frames or more. 22 Preliminary Product Information S16789EJ2V0PM "Normal display mode" PD161606 5.1.3 i80/M68 parallel interface When the parallel interface has been selected, setting the C86 pin as either H or L enables a direct connection to an i80 series or M68 series CPU (Refer to following table). Table 5-3. C86 Mode /RD (E) /WR (R, /W) H L D7 to D0 M68 series CPU E R, /W D7 to D0 i80 series CPU /RD /WR D7 to D0 The data bus signal is identified according to the combination of the RS, /RD (E), and /WR (R, /W) signals. Table 5-4. Common M68 series CPU RS R, /W H H i80 series CPU Function /RD /WR H L H Read display data L H L Write display data L H L H Read command L L H L Write command Preliminary Product Information S16789EJ2V0PM 23 PD161606 (1) i80 series parallel interface When i80 series parallel data transfer has been selected, data is written to the PD161606 at L period of the /WR signal. The data is output to the data bus when the /RD signal is L. Figure 5-4. i80 Series Interface Data Bus Status /CS (CSEG = L) /WR /RD Valid data Dn Data write Data read (2) M68 series parallel interface When M68 series parallel data transfer has been selected, data is written at the H period of the E signal when the R,/W signal is L. In a data read operation, data is output at the rising edge of the E signal in a period when the R,/W signal is H. The data bus is released (Hi-Z) at the falling edge of the E signal. Figure 5-5. M68 Series Interface Data Bus Status /CS (CSEG = L) R,/W E Valid data Dn Data write 24 Data read Preliminary Product Information S16789EJ2V0PM PD161606 5.1.4 Serial interface The serial interface can be selected from serial interface mode 1 and serial interface mode 2 through serial mode selection (SSEL). These mode are described in sections 5.1.4 (1) and 5.1.4 (2). This serial interface supports SPI. The settings are described in section 5.1.4 (3). (1) Serial interface mode 1 In serial interface mode 1, the data to be input can be specified either as "register number/register data" or "display data (RAM data)" through input to the RS pin. The concrete details are as follows. For the register number and register data input sequences, refer to Figure 5-9. RS Pin Input Level Data Input from Serial Interface Low-level Register number/register data High-level Display data (2) Serial interface mode 2 In serial interface mode 2, the 1st byte transfer sets the serial interface operation specification registers (A7 to A0) by the 1st byte transfer, and specifies whether the transfer data of 2nd byte is "register number", "register data", or "display data (RAM data)". During the 2nd byte transfer, the data specified with the 1st byte is transferred. The serial interface operation specification registers are as follows. Table5-5. Serial Interface Operation Specification Registers Number Bit name Function A7 - - A6 Register/RAM data select This bit sets whether the D7 to D0 data is data for the PD161606's registers or for its RAM. 0: D7 to D0 are data for the PD161606's registers. 1: D7 to D0 are data for the PD161606's RAM. A5 Read/write select This bit selects whether the D7 to D0 data transfer is a read operation or a write operation. However, a read operation is possible only for the PD161606's registers. For the read operation timing chart, refer to 0: D7 to D0 = Write operation 1: D7 to D0 = Read operation A4 - - A3 - - A2 - - A1 - - A0 Command/data select This bit selects whether the D7 to D0 data is the data specifying the register number of the command register, or the setting data for the command register. 0: D7 to D0 = register number 1: D7 to D0 = register setting value Preliminary Product Information S16789EJ2V0PM 25 PD161606 Therefore, as shown in the following timing chart, in serial interface mode 2, after the chip select signal becomes active, access to the serial interface operation specification register is always performed. Figure 5-6. Serial Interface Mode 2 Timing Chart /CS SCL SI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 Serial interface operation specification transfer . Register setting or RAM setting selection . Read or write selection . Register number value or register data value D5 D4 D3 D2 D1 D0 Command & data transfer . Register numbaer value transfer . Register data value transfer . Display data (RAM data) transfer Therefore, to perform write to a register, for example, 2-byte transfer is performed until a series of settings have been completed. Also note that during 4-byte transfer performing access to a register, and during 2-byte transfer performing display data (RAM) write, chip select must be kept active. Figure 5-7. When Performing Register Setting in Serial Interface Mode 2 1st byte 2nd byte /CS SCL SI A7 A6 A5 A4 A3 A2 A1 A0 D7 Serial interface operation specification transfer . Specification of transfer of the register number value at the next transfer D6 D5 D4 D3 D2 D1 D0 Command & data transfer . Register number value transger 3rd byte 4th byte /CS SCL SI A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operation specification transfer . Specification of transfer of the register data value at the next transfer 26 D7 D6 D5 D4 D3 D2 D1 Command & data transfer . Register data value transger Preliminary Product Information S16789EJ2V0PM D0 PD161606 (3) SPI When the serial interface is selected, serial data input (SI) and serial clock input (SCL) can be accepted if the chip is in active status, but the relationship between the I/O data and the valid edges of the serial clock at this time, and the active level of the serial clock can be set with the SCLEG0 and SCLEG1 pins. Table 5-6. Relationship between Serial Clock and Data Pin name Active level of serial clock Serial data load timing Serial data output timing SCLEG1 SCLEG0 L L Low-level Rising edge of serial clock Falling edge of serial clock L H Low-level Falling edge of serial clock Rising edge of serial clock H L High-level Falling edge of serial clock Rising edge of serial clock H H High-level Rising edge of serial clock Falling edge of serial clock An operation example when the active level of the serial clock is set to low level, data is output at the falling edge of the serial clock, and data is input at the rising edge of the serial clock, is described below. Serial data is read in the sequence of D7 first, then D6 to D0, in synchronization with the rising edge of the serial clock from the serial input pin. This data is converted into parallel data and processed in synchronization with the rising edge of the 8th serial clock. Whether the serial input data is display data or a register setting is judged from the RS input in the case of serial interface mode 1. If RS = H, the data is display data, and if RS = L, it is register number/register data. In the case of serial interface mode 2, this is judged from the data of the A6 operation specification bit. If A6 = H, the data is display data, and if A6 = L, it is register number/register data. Next, the serial interface signal chart is shown. Figure 5-8. Serial Interface Signal Chart /CS SCL (SCLEG1 = L) SCL (SCLEG1 = H) SI (SCLEG0 = L) SI (SCLEG0 = H) D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 RS D1 D1 D0 D0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 RS D2 D2 D1 D1 D0 D0 RS "" in the above figure indications the data read timing. Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings. 2. Display data RAM read is not possible. 3. When using SCL wiring, take care concerning the possible effects of terminating reflection and noise from external sources. Our recommends checking operation with the actual device. Preliminary Product Information S16789EJ2V0PM 27 PD161606 5.1.5 Chip select The PD161606 has a chip select pin (/CS). The CPU parallel interface and serial interface can be used only when /CS = L. When the chip select pin is inactive, D0 to D17 are set to high impedance (invalid) and input of RS, /RD, or /WR is not active. Therefore, keep the chip select pin active for 1 cycle period of data transfer (until a read/write operation has been completed once in the parallel interface mode). It is not necessary to keep the chip select signal active when successively transferring data. It may be non-active between data transfer operations. However, note that it is necessary to continue making chip selection active during "a register specification + register value setup" and transmission of "higher rank 8-bit+ low rank 8-bit of RAM" of 16-bit in the case of a serial interface. 5.1.6 Access to display data RAM and internal registers Figures 5-9 to 5-13 show write accesses to the display data RAM and read/write accesses to internal registers 8-bit parallel interface modes and serial interface mode. When the CPU accessed the PD161606, the CPU only has to satisfy the standard requirement of the cycle time (tCYC) and can transfer data at high speeds. Usually, it is not necessary for the CPU to take WAIT time into consideration. 28 Preliminary Product Information S16789EJ2V0PM PD161606 Figure 5-9. Read/Write in 8-Bit Parallel Interface Mode <8-bit Parallel Interface> <1> Write to Display data RAM /CS RS /WR D7-D0 Display data RAM Display data RAM Display data RAM D7 to D5: Invalid data, D4: D4-bit of RAM, D3: D3-bit of RAM, D2: D2-bit of RAM, D1: D1-bit of RAM, D0: D0-bit of RAM <2> Read of Display data RAM /CS RS /RD Display data RAM D7-D0 Display data RAM Display data RAM D7 to D5: Invalid data, D4: D4-bit of RAM, D3: D3-bit of RAM, D2: D2-bit of RAM, D1: D1-bit of RAM, D0: D0-bit of RAM <3> Write to Register /CS RS /WR /RD D7-D0 Command Data D7: IX7 to D0: IX0 D7: D7 of Register to D0: D0 of Register <4> Read of Register /CS RS /WR /RD D7-D0 Command D7: IX7 to D0: IX0 Data D7: D7 of Register to D0: D0 of Register Cautions 1. While setting the writing to a register, set it the fixed input of the low level to RS pin. The register write interval is the "register number specification" + "register value setting" interval. 2. While setting the writing to display data RAM, set it the fixed input of the high level to RS pin. The display data RAM write interval is the "1-pixel data transfer interval" Preliminary Product Information S16789EJ2V0PM 29 PD161606 Figure 5-10. Read/Write in 8-bit Serial Interface (Serial Interface Mode1) <8-bit Serial interface mode1> <1> Write to display data RAM (SCLEG0 = L, SCLEG1 = L) /CS RS R,/W SCL SI 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Display RAM data 1 D7 2 D6 3 D5 4 D4 5 D3 6 7 D2 D1 8 D0 Display RAM data (SCLEG0 = H, SCLEG1 = L) /CS RS R,/W SCL SI 1 D7 2 D6 3 D5 4 D4 5 D3 6 7 D2 D1 8 D0 Display RAM data 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Display RAM data (SCLEG0 = L, SCLEG1 = H) /CS RS R,/W SCL SI 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Display RAM data 1 D7 2 D6 3 D5 4 D4 5 D3 6 7 D2 D1 8 D0 Display RAM data (SCLEG0 = H, SCLEG1 = H) /CS RS R,/W SCL SI 1 D7 2 D6 3 D5 4 D4 Display RAM data 30 5 D3 6 7 D2 D1 8 D0 1 D7 2 D6 3 D5 4 D4 Display RAM data Preliminary Product Information S16789EJ2V0PM 5 D3 6 D2 7 D1 8 D0 PD161606 Figure 5-11. Read/Write in 8-bit Serial Interface (Serial Interface Mode1) <2> Write to Register (SCLEG0 = L, SCLEG1 = L) /CS RS R,/W SCL SI 1 2 3 4 5 6 7 8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 Command 9 D7 10 11 12 13 14 15 16 D6 D5 D4 D3 D2 D1 D0 Data (SCLEG0 = H, SCLEG1 = L) /CS RS R,/W SCL SI 1 2 3 4 5 6 7 8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 Command 9 D7 10 11 12 13 14 15 16 D6 D5 D4 D3 D2 D1 D0 Data (SCLEG0 = L, SCLEG1 = H) /CS RS R,/W SCL SI 1 2 3 4 5 6 7 8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 Command 9 D7 10 11 12 13 14 15 16 D6 D5 D4 D3 D2 D1 D0 Data (SCLEG0 = H, SCLEG1 = H) /CS RS R,/W SCL SI 1 2 3 4 5 6 7 8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 Command 9 D7 10 11 12 13 14 15 16 D6 D5 D4 D3 D2 D1 D0 Data Preliminary Product Information S16789EJ2V0PM 31 PD161606 Figure 5-12. Read/Write in 8-bit Serial Interface (Serial Interface Mode1) <3> Read of Register (SCLEG0 = L, SCLEG1 = L) /CS RS R,/W SCL SI 1 2 3 4 5 6 7 8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 9 10 11 12 13 14 15 16 Command SO X D7 D6 D5 D4 D3 D2 D1 D0 Data (SCLEG0 = H, SCLEG1 = L) /CS RS R,/W SCL SI 1 2 3 4 5 6 7 8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 9 10 11 12 13 14 15 16 Command SO X D7 D6 D5 D4 D3 D2 D1 D0 Data (SCLEG0 = L, SCLEG1 = H) /CS RS R,/W SCL SI 1 2 3 4 5 6 7 8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 9 10 11 12 13 14 15 16 Command SO X D7 D6 D5 D4 D3 D2 D1 D0 Data (SCLEG0 = H, SCLEG1 = H) /CS RS R,/W SCL SI 1 2 3 4 5 6 7 8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 9 10 11 12 13 14 15 16 Command SO X D7 D6 D5 D4 D3 D2 D1 D0 Data Cautions 1. During 16-bit transfer of the "register number specification + register value setting", chip select must be maintained active. 2. When performing register write, keep the output to the RS pin low level during the "register number specification + register value setting" interval. 3. When performing display data RAM write, keep the output to the RS pin high level during the 1-pixel data transfer interval. 32 Preliminary Product Information S16789EJ2V0PM PD161606 Figure 5-13. Read/Write in 8-bit Serial Interface (Serial Interface Mode2) <8-bit Serial interface mode2> <1> Write to Register (SCLEG0 = L, SCLEG1 = L) /CS SCL SI 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operatoin specification transfer 9 10 11 12 13 14 15 16 D7 D6 D5 D4 D3 D2 D1 D0 Command & data transfer (SCLEG0 = H, SCLEG1 = L) /CS SCL SI 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operatoin specification transfer 9 10 11 12 13 14 15 16 D7 D6 D5 D4 D3 D2 D1 D0 Command & data transfer (SCLEG0 = L, SCLEG1 = H) /CS SCL SI 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operatoin specification transfer 9 10 11 12 13 14 15 16 D7 D6 D5 D4 D3 D2 D1 D0 Command & data transfer (SCLEG0 = H, SCLEG1 = H) /CS SCL SI 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operatoin specification transfer 9 10 11 12 13 14 15 16 D7 D6 D5 D4 D3 D2 D1 D0 Command & data transfer <2> Read of Register (SCLEG0 = L, SCLEG1 = L) /CS SCL SI SO 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operatoin specification transfer X 9 10 D7 D6 Data 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 (SCLEG0 = H, SCLEG1 = L) /CS SCL SI SO 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operatoin specification transfer X 9 10 D7 D6 Data 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 (SCLEG0 = L, SCLEG1 = H) /CS SCL SI SO 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operatoin specification transfer X 9 10 D7 D6 Data 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 (SCLEG0 = H, SCLEG1 = H) /CS SCL SI SO 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Serial interface operatoin specification transfer X 9 10 D7 D6 Data 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 Caution During 16-bit transfer of the "serial interface operation specification transfer + command & data transfer", chip select must be maintained active. Preliminary Product Information S16789EJ2V0PM 33 PD161606 5.1.7 PD161645 control serial interface This is the 16-bit serial interface for performing control for the PD161645. The transfer operation is as follows. <Transfer operation> This interface performs batch transfer of 16-bit data. The data format for the PD161645 consists of the command in the first byte of transfer data, and the data to be set in the second byte. Transfer is performed MSB first. The transfer start trigger is data write to the control registers for the PD161645. When data is written to control registers, GCS, GS0, and GSCLK output automatically starts. Following input of the reset command, the PD161645 checks the data of the odd bytes to be transferred against the command, and checks the data of the even bytes against the data for the command. Perform write to the shift register following the completion of transfer. Thus secure an interval of at least 250 s between write operations to registers for the PD161645. Transfer data when performing data write during transfer cannot be guranteed. Figure 5-14. PD161645 Control Serial Interface Timing Chart /CS GSO IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 D7 D6 D5 D4 D3 D2 D1 D0 9 10 11 12 13 14 15 16 GSCLK 1 2 3 4 5 Command (first 8-bit data) 34 6 7 8 Data set as a command (2nd byte data) Preliminary Product Information S16789EJ2V0PM PD161606 5.2 Partial Display RAM The RAM holding the dots for display has a configuration of 115,200bits (240 X 5 bits) X 96 bits. Any pixel can be accessed by specifying the X address and Y address. Figure 5-15 shows the configuration of the display data RAM. The partial display RAM has a 5-bit configuration, and bits D0 to D2 are the display data bits. Bits D3 and D4 are used for the OSD function, and are enabled when this function is selected. Figure 5-16 shows the operation when the OSD function is enabled. Figure 5-15. Display RAM/Bit Configuration RAM bit D4 D3 Function 1 2 D2 D1 Display data R data Pixel LCD panel D0 G data B data 1 pixel Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 Figure 5-16. Transmittance when Blending Function is Selected OSD function 1 2 Display RAM data transmittance Invalid x x Transmittance 0% (base image 100%) Valid 0 0 Transmittance 0% (base image 100%) Valid 0 1 Transmittance 50% (base image 50%) Valid 1 0 Transmittance 75% (base image 25%) Valid 1 1 Transmittance 100% (base image 0%) Remark x: Don't care 5.2.1 X address circuit An X address of the display data RAM is specified by using the X address register (R6) as shown in Figure 5-18. The specified X address is incremented by one each time display data is written or read. In the X address increment mode, the X address is incremented up to EFH. If more display data is written or read, the Y address is incremented, and the X address returns to 00H. The relationship between the X address and source output can be inverted by the ADX flag of control register 1 as shown in Figure 5-18. After switched ADX, the input data can be rotated 90 degrees and displayed by changing the ADR function and address increment direction between X and Y. Preliminary Product Information S16789EJ2V0PM 35 PD161606 5.2.2 Y address circuit The Y address of the display data RAM is specified by using the Y address register (R7) as shown in Figure 5-18. The Y address is incremented each by one when one each time display is written or read and X address is incremented to last address. When the Y address has been incremented up to 5FH and the X address up to the final address, if further display data is read or written, the X and Y addresses return to 00H. As shown in Figure 5-18, the relationship between the Y address and gate output can be inverted by the ADR flag of the control register. The data written to the display can be rotated 90 degrees and output by changing the ADX function and address increment direction between X and Y. Table 5-7. Data Access Control (R5) Settings INC Setting 0 During data access, addresses are continuously incremented in the X direction. 1 During data access, addresses are continuously incremented in the Y direction. Figure 5-17. Example of 90-degree Rotation ADX = 0, ADR = 0 X address increment (INC = 0) ADX = 0, ADR = 1 Y address increment (INC = 1) Display image 36 Preliminary Product Information S16789EJ2V0PM PD161606 Figure 5-18. PD161606 RAM Addressing 1) ADX=0 ADC=0 Source output ADC=1 X-address Column address S1 S720 S2 S719 S3 S718 S4 S717 S5 S716 000H 001H 002H 003H D2 D1 1st Pixel D0 D2 000H S6 S715 ------- --- 004H 005H --- --- D1 2nd Pixel D0 001H ----- S715 S6 S716 S5 S717 S4 S718 S3 S719 S2 2CAH 2CBH 2CCH 2CDH 2CEH D2 2CFH D1 239th Pixel D0 D2 D1 240th Pixel D0 S716 S5 S717 S4 S718 S3 S719 S2 S720 S1 EEH S720 S1 EFH Y-address ADY=0 ADY=1 00H 01H 5FH 5EH | | 56H | | 59H 57H 58H 58H 57H 59H | | 56H | | 5EH 5FH 01H 00H Display area 2) ADX=1 ADC=0 Source output ADC=1 X-address Column address S1 S720 S2 S719 S3 S718 S4 S717 EFH S5 S716 S6 S715 EEH 2CFH 2CEH 2CDH 2CCH 2CBH 2CAH D2 D1 240th Pixel D0 D2 D1 239th Pixel D0 ----- ----- --- --- --- --- S715 S6 001H 000H 005H 004H 003H 002H 001H 000H D2 D1 2nd Pixel D0 D2 D1 1st Pixel D0 Y-address ADY=0 ADY=1 00H 01H 5FH 5EH | | | | 56H 57H 58H 59H 58H 57H 59H | 56H | | 5EH 5FH | 01H 00H Display area Preliminary Product Information S16789EJ2V0PM 37 PD161606 5.2.3 Arbitrary address area access (window access mode (WAS)) With the PD161606, any area of the display RAM selected by the MIN., X/Y address registers (R8 and R10) and MAX., X/Y address registers (R9 and R11) can be accessed. First, select the area to be accessed by using the MIN.*X/Y address registers and MAX.*X/Y address registers. When WAS of data access control register (R5) is set to 1, the window access mode is then selected. The address scanning setting is also valid in this mode, in the same manner as when data is normally written to the display RAM. In addition, data can be written from any address by specifying the X address register (R6) and Y address register (R7). Figure 5-19. Example of Incrementing Address when in Window Access Mode MIN. X address Start point MAX. X address EFH 00H 00H MIN. Y address . . . MAX. Y address 5FH End point Cautions 1. When using the window access mode, the relationship between the start point and end point shown in the table below must be established. Item Address Relationship X address 00H MIN.*X address X address (R6) MAX.*X address EFH Y address 00H MIN.*Y address Y address (R7) MAX.*Y address 5FH 2. If invalid address data is set as the MIN./MAX. address, operation is not guarateed. 38 Preliminary Product Information S16789EJ2V0PM PD161606 Example of Sequence in Window Access Mode The settings of the MIN. X address register (R8), MIN. Y address register (R10), MAX. X address register (R9), and MAX. Y address register (R11) van be performed in any order. Start MIN. . X address register (R8) Sets start point. MIN. . Y address register (R10) MAX. . X address register (R9) Sets end point. MAX. . Y address register (R11) Data access control register (R5) (WAS = 1) Sets window access mode. X address register (R6) Y address register (R7) Write display data Data Writing complete? No Yes End Preliminary Product Information S16789EJ2V0PM 39 PD161606 5.3 Oscillator The PD161606 allows selection of the on-chip oscillator (OSC2SEL = L: CR on-chip type) or an external oscillator (OSC2SEL = H: R external) as the oscillator generating the display clock by setting the OSC2SEL pin. Moreover, the on-chip oscillator contains two oscillation circuits. One of these oscillation circuits (OSC2) is used to generate the liquid crystal display output timing, while the other oscillation circuit (OSC1) is used when executing frame frequency calibration. D4 bit of R1 (OSC1OFF) 0 Internal oscillation start D3 bit of R1 (OSC2OFF) 0 WAIT time: T.B.D. s (Oscillation stabilization time wait) D0 bit of R45 (OC) 1 Calibration start It is WAIT about the time for one line of frame frequency to set up. D0 bit of R45 (OC) 0 Calibration stop WAIT time: T.B.D. s(Calibration processing time) D4 bit of R1 (OSC1OFF) 1 Oscillation circuit stop for calibrations Since the oscillation circuit for calibrations comes to unnecessary after calibration execution, in order to lower power consumption, suspend an oscillation ("1" is set to OSC1OFF of D4 bit of R1). In addition, when set calibration again once performing a calibration, start oscillation operation again. Moreover, the frame frequency by which the calibration was carried out is eliminated by command reset. Therefore, when command reset is input, set a calibration again. When selecting an external oscillator (OSCSEL = H), connect a T.B.D. resistor to the OSCIN pin and the OSCOUT pin. When the internal oscillator is selected, leave both pins unconnected. Cautions 1. If DIVSL (R46), HCKSL (R46), LNSEL (R50) are changed from their initial values, calibration is prohibited. 2. When an external oscillator is selected, calibration is prohibited. 40 Preliminary Product Information S16789EJ2V0PM PD161606 5.4 Display Timing Generator The display timing generator generates the timing signals for the internal timing of the source driver and for the gate driver. Horizontal interval The timing of the following signals is controlled by register setting. *GCLK *GSTB *GOE1 *EQ *Amplifier drive period In addition, a timing chart is shown next page. Preliminary Product Information S16789EJ2V0PM 41 PD161606 Figure 5-20. Display Driving Signal Timing Chart (RGB interface: 16/18-bit batch transfer, line inversion) 16, 18-bit Mode display timing chart <line inversion, 720 output, VSYNC width = 1H, non-dummy line> (1) HSYNC unit (Horizon period back porch (R75) = 3H) *VSEG = L, HSEG = L, DCKEG = L *Display CLK address value turns into a value which counted DOTCLK. *When [ all ] it puts in 245 CLK or more in 1H period, it is added after display CLK address(Hcnt) value 244 address. tHSW (MIN. 1 DOTCLK) HSYNC tHS (MIN. 245 DOTCLK) 230 240 245 1 DOTCLK tHBP (MIN. 3 DOTCLK) RGB Data Hcnt Invalid 12345 6789 222 - - - - 0 1234567 89 # 224 # 226 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Invalid 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 GCED[7:0] GCLK Polarity reversal is possible GSTB-GCLK (MIN. 4 DOTCLK) GSTB GOST[7:0] GOED[7:0] GOE1 *At the time of a display = H. It changes with the time of standby, or 59DR1 (GOE2ON) commands. GOE2 EQST[7:0] EQED[7:0] EQ APED[7:0] APST[7:0] AP Equalize drive period Amplifier drive period r-resistance direct drive period S1 to S720 Hi-Z Hi-Z VCOUT Gn OUT Gn+1 OUT * The MIN. value of EQST, APST, and GOST is set to 1. * The MIN. value of GCED is set to 2. * When the position of a standup and falling is the same, an output serves as L fixation. 42 Preliminary Product Information S16789EJ2V0PM PD161606 Figure 5-21. Display Driving Signal Timing Chart (RGB interface: 6-bit batch transfer, line inversion) 6 bit Mode display timing chart <line inversion, 720 output, VSYNC width = 1H, non-dummy line> * VSYNC and HSYNC operate for every 3 DOTCLK at the time of 6bit Mode. (1) HSYNC unit (Horizon period back porch (R75) = 3H) * VSEG = L, HSEG = L, DCKEG = L *Display CLK address value (Hcnt) turns into a value which counted DOTCLK. tHSW (MIN. 3 DOTCLK) HSYNC tHS (MIN. 735 DOTCLK) 720 730 735 DOTCLK tHBP (MIN. 9 Dotclk) CLK (Internal CLK) 1 RGB Data Hcnt D1 Invalid - - - 0 1 2 D2 2 D3 3 D1 D2 4 3 D3 D1 D2 4 D3 5 D1 D2 5 D3 D1 6 D2 7 6 D3 D1 D2 7 D3 8 D1 D2 9 8 D3 D1 D2 9 D3 10 D1 D2 11 236 D3 D1 D2 237 D3 238 D1 D2 238 D3 239 D1 D2 239 D3 240 D1 D2 1 240 D3 241 D1 D2 D3 242 D1 Invalid 243 244 0 1 2 D2 3 3 2 D3 D1 D2 4 D3 D1 D2 4 D3 5 D1 D2 6 5 D3 D1 D2 7 6 D3 D1 D2 8 8 7 D3 D1 D2 9 D3 D1 D2 10 9 D3 D1 D2 11 10 D3 D1 D2 12 11 D3 D1 D2 D3 D 13 GCED[5:0] GCLK Polarity reversal is possible GSTB GOST[5:0] GOED[5:0] GOE1 *At the time of a display = H. It changes with the time of standby, or 59DR1 (GOE2ON) commands. GOE2 EQST[5:0] EQED[5:0] EQ APST[5:0] APED[5:0] AP Amplifier drive period Equalize drive period S1 to S720 r-resistance direct drive period Hi-Z Hi-Z VCOUT Gn OUT Gn+1 OUT Preliminary Product Information S16789EJ2V0PM 43 PD161606 Figure 5-22. Display Driving Signal Timing Chart (partial display, line inversion) Display timing chart (Partial display) (1) HCNT unit *Display CLK address value (Hcnt) turns into a value which counted DOTCLK. * Horizontal, perpendicular address: MIN. setup CLK Hcnt 29 0 1 2 3 4 5 6 7 8 9 10 11 12 12 22 23 24 25 26 27 28 29 0 1 2 3 4 5 6 PGCED[7:0] GCLK Polarity reversal is possible GSTB PGOST[7:0] PGOED[7:0] GOE1 *At the time of a display = H. It changes with the time of stand-by, or 59DR1 (GOE2ON) commands. GOE2 PEQST[7:0] PEQED[7:0] EQ PAPST[7:0] PAPED[7:0] AP Amplifier drive period Equalize drive period S1 to S720 r-resistance direct drive period Hi-Z Hi-Z VCOUT Gn OUT Gn+1 OUT * The MIN. value of EQST, APST, and GOST is set to 1. * The MIN. value of GCED is set to 2. * When the position of a standup and falling is the same, an output serves as L fixation. 44 Preliminary Product Information S16789EJ2V0PM 7 8 9 10 11 12 PD161606 5.5 - Curve Correction Circuit The PD161606 has an on-chip - curve correction power supply circuit. If the internal - curve correction matches the LCD characteristics, no external parts are required. This circuit incorporates one - curve correction resistor and adjusts - Inclination and amplitude by switching between positive and negative polarity according to register settings. Figure 5-23. - Curve Correction Circuit Amplitude adjustment (fixed) Amplitude adjustment Amplitude adjustment (fixed) -register switch Inclination adjustment 64 gray-scale Fine tunig adjustment Inclination adjustment Amplitude adjustment (fixed) -register switch Amplitude adjustment (fixed) Amplitude adjustment Preliminary Product Information S16789EJ2V0PM 45 PD161606 5.5.1 Amplitude adjustment with internal amplifier Amplitude adjustment can select two ways, the method of adjusting with internal amplifier, and the method of adjusting by internal resistance. Each register of R101 (GPH [5:0]), R102 (GNH [5:0]), R103 (GPL [5:0]), and R104 (GNL [5:0]) performs adjustment with amplifier. Refer to Figure 5-24. Figure 5-24. Amplitude Adjustment 1 (This figure is a circuit by the side of positive-polarity. Use GPH reading it as GNH, GPL to GNL, VPH to VNH, and VPL to VNL if negative-polarity side's reading) VS VS GPH [5:0] VD127 to VD64 VPH D/A ... VPL VD63 to VD0 D/A GPL [5:0] VSS1 VSS1 Figure 5-25. Relationship of TFT Drive Voltage (Normally White) VS VPH VNH Black White VPL VNL VSS1 Positive polarity Drive Level 46 Negative polarity Setting Register VPH Positive polarity, black Contrast value setting register 1 R101 VNH Negative polarity, white Contrast value setting register 2 R102 VPL Negative polarity, white Contrast value setting register 3 R103 VNL Positive polarity, black Contrast value setting register 4 R104 Preliminary Product Information S16789EJ2V0PM PD161606 The value of each amplifier output can be expressed as follows and the value of can be set as shown in Table 5-8 and 5-9 by using the contrast value registers (R101, R102, R103, and R104) VNL, VPL, VNH, VPH = ( / 129) x VS Caution The usable range in which each output level of VPH, VNH, VPL, and VNL can be set depends on the curve. Table 5-8. - Contrast Value Setting and Electronic Volume Register Setting 1 (VPH, VNL) R101 VPH5 VPH4 VPH3 VPH2 VPH1 VPH0 value Setting or R102 VNH5 VNH4 VNH3 VNH2 VNH1 VNH0 Status Setting 00H 0 0 0 0 0 0 65 01H 0 0 0 0 0 1 66 02H 0 0 0 0 1 0 67 03H 0 0 0 0 1 1 68 3EH 1 1 1 1 1 0 127 3FH 1 1 1 1 1 1 128 Table 5-9. - Contrast Value Setting and Electronic Volume Register Setting 2 (VPL, VNL) R103 VPL5 VPL4 VPL3 VPL2 VPL1 VPL0 value Setting or R104 VNL5 VNL4 VNL3 VNL2 VNL1 VNL0 Statement Setting 00H 0 0 0 0 0 0 1 01H 0 0 0 0 0 1 2 02H 0 0 0 0 1 0 3 03H 0 0 0 0 1 1 4 3EH 1 1 1 1 1 0 63 3FH 1 1 1 1 1 1 64 Preliminary Product Information S16789EJ2V0PM 47 PD161606 5.5.2 Amplitude adjustment by built-in resistance The 4-bit data set as registers R105 and R109 sets amplitude adjustment by built-in resistance. Refer to Figure 5-26. Figure 5-26. Amplitude Adjustment VS V0RP[3:0] (V0RP[3:0]) VDR V0 GL V63 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 V0RN[3:0] (V0RN[3:0]) VDRP 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5R 10R 15R 20R 25R 30R 35R 40R 45R 50R 55R 60R 65R 70R 75R 80R 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Voltage GH 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VSR VSS1 Scale Data 48 Preliminary Product Information S16789EJ2V0PM 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VDNP 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5R 10R 15R 20R 25R 30R 35R 40R 45R 50R 55R 60R 65R 70R 75R 80R PD161606 5.5.3 Inclination adjustment Internal resistance also adjusts inclination adjustment. R106 and R110 register set adjustment. Refer to Figure 5-27. Figure 5-27. Inclination Adjustment V0 GH VGR4 VLR VHRP[3:0] (VLRP[3:0]) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 V1 V2 V3 VGR5 V4 0 0 0 0 1 1 1 1 V60 V61 0 1 0 1 0 1 0 1 V62 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VHRN[3:0] (VLRN[3:0]) VHRP 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2R 4R 6R 8R 10R 12R 14R 16R 18R 20R 22R 24R 26R 28R 30R 32R 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V0R5N[2:0] (V0R6N[2:0]) VDR5(6)P 4R 8R 12R 16R 20R 24R 28R 32R 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 V0R4N[2:0] (V0R7N[2:0]) VDR4(7)P 8R 16R 24R 32R 40R 48R 56R 64R 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VHRN 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2R 4R 6R 8R 10R 12R 14R 16R 18R 20R 22R 24R 26R 28R 30R 32R VDR4(7)N 8R 16R 24R 32R 40R 48R 56R 64R VDR5(6)N 4R 8R 12R 16R 20R 24R 28R 32R V63 Voltage GL 0 0 1 1 0 0 1 1 V0R5P[2:0] (V0R6P[2:0]) VGR6 VGR7 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 V0R4P[2:0] (V0R7P[2:0]) 0 0 0 0 1 1 1 1 V59 VHR 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ScaleData Preliminary Product Information S16789EJ2V0PM 49 PD161606 5.5.4 Fine tuning adjustment Internal resistance also sets fine tuning. Please adjust by R107, R108, R111, and R112 register. Refer to Figure 5-28. Figure 5-28. Fine Tuning Default R0:VGR0=R1:VGR1=R2:VGR2 =R3:VGR3=R:R'=1:1 GH r00 V0 R0 r01 VGR0 R0 VGR1 R1 V8 Ri r04 V8 V20 Default:ON R V43 VGR2 R2 VGRnP[2:0] V55 VGR3 GL 50 R3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VGR0P VGR1P VGR2P VGR3P 60R 56R 52R 48R 44R 40R 36R 32R 60R 56R 52R 48R 44R 40R 36R 32R 32R 36R 40R 44R 48R 52R 56R 64R 32R 36R 40R 44R 48R 52R 56R 64R V63 Preliminary Product Information S16789EJ2V0PM 0 0 0 0 1 1 1 1 VGRnN[2:0] VGR0N VGR1N VGR2N VGR3N 0 0 1 1 0 0 1 1 60R 56R 52R 48R 44R 40R 36R 32R 60R 56R 52R 48R 44R 40R 36R 32R 32R 36R 40R 44R 48R 52R 56R 64R 32R 36R 40R 44R 48R 52R 56R 64R 0 1 0 1 0 1 0 1 PD161606 5.6 Partial Display Function The PD161606 contains a partial display function. When this function is used, the display control clock becomes the internal oscillation clock, and the display image shows only the data written to the partial display RAM. Moreover, the partial non-display area displays the partial non-display area color set with the R23 register. Refer to Figure 5-29. Table5-10 shows a comparison of the regular operation and the partial display operation. Table 5-10. Comparison of Regular Operation and Partial Display Operation Regular Operation Partial Display Operation Display control clock DOTCLK, HDYNC, VSYNC Internal oscillation clock Partial RAM display Displayed only when OSD function is enabled Always displayed. OSD function Enabled. 1 bit and 2 bit settings are enabled. Disabled. Regardless of the 1 bit and 2 bit settings, the data written to the partial RAM is always enabled. Display outside partial Input data displayed via RGB interface Partial non-display area color set with R23 is RAM display displayed. Figure 5-29. Partial Display RGB interface input data Partial display data RAM 10 / 23 [TUE] 10 : 35 R15: Partial RAM display area 1 start Y address R16: Partial RAM display area 1 line count "Invalid" R19: Partial RAM display area 2 start Y address R20: Partial RAM display area 2 line count Actually display screen Partial non-display area Color set by R23 Data RAM display area i80/M68 interface or It rewtite by the serial interface 10 / 23 [TUE] 10 : 35 R17, R18: Partial RAM display area 1 display start line R21, R22: Partial RAM display area 2 display start line Preliminary Product Information S16789EJ2V0PM 51 PD161606 5.7 Stand-by The PD161606 has a stand-by function that allows two types of operation as stand-by operation, either of which can be selected. 5.7.1 Stand-by mode 1 Stand-by mode 1 is selected by setting STBSEL (R0, D2) = 0. By setting control register 1 (R0): STBY = 1, white display is performed, and during the frame dummy line interval, all gate outputs are set to ON and the panel charge is discharged. By setting the control register (R24): DCON = 0 after all gate outputs have become ON, regulator OFF and DC/DC converter OFF are executed, and by setting R1: OSC2OFF = 1, full stand-by mode is entered after the internal oscillator stops. <Stand-by sequence> STBY bit of R0= 1 (WAIT in one frame period) DCON bit of R24= 0 OSC2OFF bit of R1 = 1 The transition from the stand-by mode to the regular mode is the opposite sequence from the stand-by sequence, and is executed in the order of OSC2OFF = 0, DCON = 1, and STBY = 0. Figure 5-30. Outline of Operation during Stand-by Mode 1 Execution Operation of stand-by command execution Stand-by command exectuion (STBY = 1) Sourse output OFF level output start (white level when VCOUT = L) VCOUTn VSS level output After an one-frame end GOE2 output VSS level output Source output VSS level output Remark In the stand-by mode (STBY = 1), display data RAM access, display data RAM hold, and register access are possible even during DC/DC converter OFF and internal oscillation stop, as long as power is supplied to VCC1, VCC2, and VCC3 (including when power is supplied to VCC1 from SF_VCC1). 52 Preliminary Product Information S16789EJ2V0PM PD161606 5.7.2 Stand-by mode 2 Stand-by mode 2 is selected by setting STVSEL (R0, D2) = 1. By setting control register 1 (R0): STBY = 1, white display starts. After white output has been performed until the next frame after STBY = 1 has been set, GO21 = Low is executed for 2 frames. Then the source output becomes VSS level. After the source output becomes VSS level, by setting control register (R24): DCON = 0, regulator OFF and DC/DC converter OFF are executed, and by setting R1: OSC2OFF, the full stand-by mode is entered after the internal oscillator stops. <Stand-by sequence> STBY bit of R0= 1 (WAIT in four frame period) DCON bit of R24= 0 OSC2OFF bit of R1 = 1 The transition from the stand-by mode to the regular mode is the opposite sequence from the stand-by sequence, and is executed in the order of OSC2OFF = 0, DCON = 1, and STBY = 0. The outline of the operation during stand-by mode 2 execution is shown on the next page. Preliminary Product Information S16789EJ2V0PM 53 PD161606 Figure 5-31. Outline of Operation during Stand-by Mode 2 Execution 1st frame Stand-by command execution (STBY = 1) . Source output OFF level output start (White display) . VCOUTn Inverted operation 2nd frame White output 3rd and 4th frame GOE1 = Low output 5th frame Source output VSS level VCOUT VSS level Remark In the stand-by mode (STBY = 1), display data EAM access, display data RAM hold, and register access are possible even during DC/DC converter OFF and internal oscillation stop, as long as power is supplied to VCC1, VCC2, and VCC3 (including when power is supplied to VCC1 from SF_VCC1). 54 Preliminary Product Information S16789EJ2V0PM PD161606 (1) Stand-by sequence As power supply control, the example of a sequence at the time of performing an internal sequence is shown. PD161606 stand-by set R0 PD161606 stand-by mode set (R0 Register) RS D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 L D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1 X X X X: Set in accordance with the usage conditions. The electric charge of the panel is discharge. It 1 frame time wait (in case stand-by mode 1) will become white display if it is normally white (In stand-by mode 2, 4 frames time wait) panel. R24 RS PD161645 power supply OFF setting (R24 Register) L D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 X X X X X X 0 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait The Power OFF completed ! R24 PD161606 internal oscillation OFF setting (R1 Register) RS L D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1 X X X X: Set in accordance with the usage conditions. Oscillation stop (Stand-by status) Preliminary Product Information S16789EJ2V0PM 55 PD161606 (2) Stand-by release sequence As power supply control, the example of a sequence at the time of performing an internal sequence is shown. PD161606 stand-by mode release R1 PD161606 internal oscillation ON setting (R1 Register) RS D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 L D7 D6 D5 D4 D3 D2 D1 D0 X X X X 0 X X X D1 D0 X: Set in accordance with the usage conditions. Oscillation start R24 PD161645 power supply ON setting (R24 Register) RS D7 D6 D5 D4 D3 D2 0 0 0 1 1 0 0 0 L D7 D6 D5 D4 D3 D2 D1 D0 0 X X X X X X 1 D1 D0 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait Power ON after time set to PUPT0/PUPT1 of R33 register has lapsed! R0 PD161606 stand-by mode release (R0 Register) RS D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 0 0 L D7 D6 D5 D4 D3 D2 D1 D0 X X X X 0 X X X X: Set in accordance with the usage conditions. Complete return to regular mode! 56 Preliminary Product Information S16789EJ2V0PM PD161606 6. POWER SUPPLY INJECTION/INTERCEPTION An example of powering injection/interception a chip set for TFT-LCD panel driving using the PD161606 is shown below. 6.1 PD161606 Power Supply Injection Setting Sequence Example Hard reset PD161606 register. Reset PD161606 register R3 RS PD161606 command reset (R3 register) L D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 X X X 0 0 X X X D10 D9 D8 Start PD161606 internal oscillation R1 RS PD161606 internal oscillation ON setting (R1 register) L X: Set in accordance with the usage conditions. Oscillation start Reset PD161645 register R25 PD161645 command reset RS D15 0 0 0 1 1 0 1 0 L D7 D6 D5 D4 D3 D2 D1 D0 X 1 X X X X X X (R34 register) D14 D13 D12 D11 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait Set PD161606 Rxx to Rxx PD161606 setting The setting order Rxx to Rxx are any order RS (Perform this setting is required.) L D15 D14 D13 D12 D11 D10 D9 D8 X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X: Set in accordance with the usage conditions. Set PD161606 horizontal interval timing Rxx to Rxx The setting order Rxx to Rxx are any order RS PD161606 horizontal interval timing setting L D15 D14 D13 D12 D11 D10 D9 D8 X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X: Set in accordance with the usage conditions. Preliminary Product Information S16789EJ2V0PM 57 PD161606 Calibration R45 PD161606 power supply setting (R45 register) L D15 D14 D13 D12 D11 D10 D9 D8 0 0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X D1 D0 X: Set in accordance with the usage conditions. R1 PD161606 calibration internal oscillation OFF setting (R1 register) RS D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 0 1 L D7 D6 D5 D4 D3 D2 D1 D0 X X X 1 0 X X X X: Set in accordance with the usage conditions. Power supply setting R25 PD161645 power supply setting (R25 register) L D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 1 1 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 0 D9 D8 0 0 X X X X X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R26 D15 PD161645 power supply setting (R26 register) L D14 D13 D12 D11 D10 0 0 0 1 1 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 1 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R27 PD161645 power supply setting (R27 register) L D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 1 1 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 X 1 0 X X X X X X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R28 PD161645 power supply setting RS (R28 register) L 58 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 1 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 X X X X X X: Set in accordance with the usage conditions. T.B.D. s MIN. wait Preliminary Product Information S16789EJ2V0PM PD161606 R29 RS PD161645 power supply setting (R29 register) L D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 1 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 X X X X X D10 D9 D8 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R30 RS D15 0 0 0 1 1 1 1 0 L D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 X X X 0 0 D10 D9 D8 PD161645 power supply setting (R30 register) D14 D13 D12 D11 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R31 RS D15 0 0 0 1 1 1 1 1 L D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X D10 D9 D8 PD161645 power supply setting (R31 register) D14 D13 D12 D11 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R32 RS D15 0 0 1 0 0 0 0 0 L D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 X X X X X PD161645 power supply setting (R32 register) D14 D13 D12 D11 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R33 RS PD161645 power supply setting (R33 register) L D15 D14 D13 D12 D11 D10 D9 D8 0 0 1 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 1 1 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R24 RS PD161645 power supply setting (R24 register) L Power ON after time set to PUPT0/PUPT1 of R33 register has lapsed! D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 1 1 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 X X X X X X 1 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait Preliminary Product Information S16789EJ2V0PM 59 PD161606 Display data input start Data input start by the RGB interface Display start setting R59 RS PD161606 GOE1, GOE2 signal setting (R59 register) L D15 D14 D13 D12 D11 D10 D9 D8 0 0 1 1 1 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 After 1-frame time, all whites or all blacks are displayed. R0 PD161606 display setting RS D15 0 0 0 0 0 0 0 0 L D7 D6 D5 D4 D3 D2 D1 D0 0 0 X 0 0 0 0 0 (R0 register) D14 D13 D12 D11 D10 D9 D8 X: Set in accordance with the usage conditions. Regular RAM data display through DISP1, DISP0 cancellation RAM data display start 60 Preliminary Product Information S16789EJ2V0PM PD161606 6.2 PD161606 Power Supply Interception Setting Sequence Example PD161606 to the stand-by mode R0 PD161606 stand-by mode setting RS D7 0 0 0 0 0 0 0 0 L D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1 X X X D1 D0 (R0 register) D6 D5 D4 D3 D2 D1 D0 X: Set in accordance with the usage conditions. 1 frame time wait (In stand-by mode 2, 4 frames times wait) Discharge of the electric charge of panel is carried out. It will become white display if it is normally white panel. R24 PD161645 power supply OFF setting RS D7 0 0 0 1 1 0 0 0 L D7 D6 D5 D4 D3 D2 D1 D0 0 X X X X X X 0 (R24 register) D6 D5 D4 D3 D2 X: Set in accordance with the usage conditions. T.B.D. s MIN. wait R1 PD161606 power supply OFF setting RS (R1 register) L D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1 X X X X: Set in accordance with the usage conditions. Oscillation stop (Stand-by status) Preliminary Product Information S16789EJ2V0PM 61 PD161606 7. E2PROM INTERFACE 2 The PD161606 builds in the interface function to E PROM corresponding to the micro-wire interface. 2 However, the capacity of E PROM corresponds 4k-bit article. 7.1 The PD161606 and E2PROM Connection Connection with E2PROM is made as shown in the following figure. LCD Controller/ Driver IC ECS CS ESK CLK EDO DIN EDI Microwire E2PROM DOUT LCD controller side signal Pin ECS Function 2 Chip select signal over E PROM. 2 With outputting ECS = 1, E PROM is made into an active state and data is transmitted after that. 2 It connects with CS (chip select pin) of E PROM. ESK 2 Clock signal over E PROM. 2 In falling of ESK, data is outputted from EDO to E PROM. 2 It connects with CLK (shift clock pin) of E PROM. EDO Data output pin. 2 Data is outputted to E PROM. 2 It connects with DIN (data in pin) of E PROM EDI Data input pin. 2 It is used for reading of the data of E PROM. 2 It connects with DOUT (data out pin) of E PROM. 62 Preliminary Product Information S16789EJ2V0PM PD161606 7.2 Each Operation The PD161606 can perform writing of register data, reading of a register date and elimination of E2PROM data to 2 E PROM. Selection of each operation is performed using R118 register. R118 Register 2 E PROM Command E2OPC2 E2OPC1 E2OPC0 0 0 0 Setting prohibited 0 0 1 EPSAVE: Writing to E PROM 0 1 0 MASKON: Permission of the writing and elimination to E PROM 2 2 2 0 1 1 MASKOF: Prohibition of the writing and elimination to E PROM 1 0 0 EPCLR: All area elimination of E PROM 1 0 1 EPWALL: FFH is written in all the area of E PROM 2 2 2 1 1 0 EPREAD: Reading from E PROM 1 1 1 Setting prohibited In addition, explain each operation below. 2 2 [E PROM read command: Reading from E PROM] From the "E2PROM address" set as "the E2PROM reading start address register (R124)", it reads in order of "index" + "a 2 register value" (a total of 16 bits) and the register data stored in E PROM is saved to the applicable index of the PD161606. In addition, reading operation is continuously performed until it reads the reading end ID (FFFFH or 7FFFH). When FFFFH or 7FFFH are not read, reading operation is stopped if reading exceeds 128 times. Command input R124: Setting of reading start address 2 R118: E PROM read execution (06H) 2 E PROM read Writing to IR register Register data reading is repeated until it reads FFFF Completion Completion of processing Preliminary Product Information S16789EJ2V0PM 63 PD161606 [EPSAVE command: Writing of the data to E2PROM] The register data of the PD161606, data is written in the E2PROM address based on R119 (E2PROM address) and R120 (IR data). Elimination/writing permission and R118: Elimination/writing permission carry out (MASKON command = 02H) command input EWEN issue To elimination/writing permission state 2 E PROM writing address specification It writes in R119 and is specification of address. Remark Since increment is not carried out, it is required. 2 Writing index specification of E PROM The data transmission command input The index which wants to write in R120 is set up. (As for the data of an index, the register value in PD161606 is written in.) 2 R118: Data transmission execution to E PROM (EPSAVE command = 01H) 2 to E PROM Wait It is wait time in order to write in ROM. It is needed. 2 Insert wait time after confirming the specification of E PROM used. Completion Elimination/writing protected and R118: Elimination/writing protected execution (03H) command input EWDS It passes elimination/writing protected. 2 About the data of E PROM, they are elimination or the disposal for making it not rewrite carelessly. Completion of processing 64 Preliminary Product Information S16789EJ2V0PM PD161606 [MASKON command: Writing/elimination permission to E2PROM] Elimination/writing to E2PROM are permitted. Command input R118 = 02H EWEN <Erase write enable> To an elimination/writing permission state Completion of processing [MASKOF: Writing protected to E2PROM] Elimination/writing to E2PROM are protected (Reading of data is possible). Command input R118 = 03H EWDS <Erase write disable> It passes elimination/writing protected. Completion of processing Preliminary Product Information S16789EJ2V0PM 65 PD161606 [EPCLR command: E2PROM elimination] : The data of E2PROM is initialized. Elimination/writing permission and R118 = 02H command input EWEN To elimination/writing permission state ERAL <Erase All> 2 All data elimination of E PROM 2 E PROM elimination and command R118 = 04H input Wait After a command input (CS = L H) in order to access ROM, ERAL is needed wait time like a data write. 2 Insert wait time after confirming the specification of E PROM used. Completion of processing Elimination/write-protected and R118 = 03H command input EWDS It passes elimination/write-protected. Completion of processing 66 Preliminary Product Information S16789EJ2V0PM PD161606 [EPWALL] : "Index = 7FH"+ "Data = FFH" is written in all the data of E2PROM. 2 2 At the time of E PROM initialization, it reads to all E PROM data, an end command (R127) is written and the infinite loop of reading by the noise etc. is prevented. Elimination/writing permission and R118 = 02H command input EWEN To elimination/writing permission state EPWALL command input R118 = 05H WRAL <Erase All> 2 "Index = 7FH (R127) "+ "Data = FFH" is written in to all the data of E PROM. After a command input (CS = L H) in order to access ROM, WRAL is Wait needed wait time like a data write. 2 Insert wait time after confirming the specification of E PROM used. Elimination/write-protected and R118 = 03H command input EWDS It passes elimination/write-protected. Completion of processing Preliminary Product Information S16789EJ2V0PM 67 PD161606 8. RESET If the /RESET input becomes L or the reset command is input, the internal timing generator is initialized. The reset command will also initialize each register to its default value. These default values are listed in the table below. When the RSEL pin is set to High-level, initialization is performed up to the reset command range by setting /RESET input to Lowlevel. (1/3) /RESET Pin Register Note Reset Command Default Value Control register 1 R0 X O 80H Control register 2 R1 X O 18H RGB interface register R2 X O 00H Command reset register R3 X O 00H Output amplitude power supply setup register for 8-color R4 X O 0FH R5 X O 00H display register Data access control register X address register R6 X O 00H Y address register MIN. X address register R7 X O 00H R8 X O 00H MAX. X address register R9 X O EFH MIN. Y address register R10 X O 00H MAX. Y address register R11 X O 5FH Partial RAM display area 1 start Y address register R15 X O 00H Partial RAM display area 1 line count register R16 X O 00H Partial RAM data display area 1 start line register R17 X O 00H Partial RAM data display area 1 start line register R18 X O 01H Partial RAM display area 2 start Y address register R19 X O 00H Partial RAM display area 2 line count register R20 X O 00H Partial RAM data display area 2 start line register R21 X O 00H Partial RAM data display area 2 start line register R22 X O 01H Partial OFF area color register R23 X O 07H Power supply control register 1 R24 X O 00H Power supply control register 2 R25 X O 00H Power supply control register 3 R26 X O 00H Power supply control register 4 R27 X O 00H Power supply control register 5 R28 X O 00H Gate scan setting register R29 X O 00H Common setting register R30 X O 00H Common amplitude setting register R31 X O 00H Common center voltage setting register R32 X O 00H Power supply rising select register R33 X O 00H Power supply command reset register 5 R34 X O 00H Remark O: Default value set, X: Default value not set Note In the case of reset via the /RESET pin, only internal counters are initialized. At power application, be sure to perform reset via the /RESET pin. 68 Preliminary Product Information S16789EJ2V0PM PD161606 (2/3) /RESET Pin Register Calibration register R45 Note X Reset Command Default Value O 00H Partial display/horizontal interval clock setting register R46 X O 00H Gate scan line count select register R50 X O 2BH Line count specify during line inversion register R51 X O 00H Partial display OFF area gate scan cycle set register R52 X O 00H GOE1 output control register R59 X O 01H DCCLK frequency set register R65 X O 00H Horizontal back porch set register R75 X O 03H Vertical back porch set register R76 X O 01H Dummy line control select register R77 X O 00H GCLK, GSTB polarity select register R78 X O 00H GCLK inversion timing set register R79 X O 10H Equalize interval start position set register R80 X O 01H Equalize interval end position set register R81 X O 15H Amplifier drive start position set register R82 X O 18H Amplifier drive end position set register R83 X O B8H GOE1 start position set register R86 X O 18H GOE1 end position set register R87 X O E8H Partial mode GCLK inversion timing set register R88 X O 03H Partial mode equalize interval start position set register R89 X O 01H Partial mode equalize interval end position set register R90 X O 03H Partial mode amplifier drive start position set register R91 X O 04H Partial mode amplifier drive end position set register R92 X O 15H Partial mode GOE1 start position set register R93 X O 05H Partial mode GOE1 end position set register R94 X O 1BH Bias adjustment register 1 R95 X O 12H Bias adjustment register 2 R96 X O 22H - adjustment register R100 X O 0FH - adjustment register R101 X O 35H - adjustment register R102 X O 30H - adjustment register R103 X O 16H - adjustment register R104 X O 1CH - adjustment register R105 X O 37H Remark O: Default value set, X: Default value not set Note In the case of reset via the /RESET pin, only internal counters are initialized. At power application, be sure to perform reset via the /RESET pin. Preliminary Product Information S16789EJ2V0PM 69 PD161606 (3/3) /RESET Pin Register Note Reset Command Default Value - adjustment register R106 X O 67H - adjustment register R107 X O 70H - adjustment register R108 X O 07H - adjustment register R109 X O 00H - adjustment register R110 X O 00H - adjustment register R111 X O 95H - adjustment register R112 X O 33H - adjustment register R113 X O 70H - adjustment register R114 X O 07H - adjustment register R115 X O 00H - adjustment register R116 X O 00H NW/NB polarity select register R117 X O 00H 2 R118 X O 00H 2 R119 X O 00H 2 R120 X O 00H 2 R121 X O 00H 2 R122 X O 00H E PROM OPC setting E PROM writing address specification E PROM writing register address specification E PROM products information register E PROM products information register 2 R123 X O 00H 2 R124 X O 00H E PROM products information register E PROM reading address specification 2 E PROM OSC divide register R125 X O 01H PD161645 OSC divide register R126 X O 00H R127 X O FFH 2 E PROM read stop register Remark O: Default value set, X: Default value not set Note In the case of reset via the /RESET pin, only internal counters are initialized. At power application, be sure to perform reset via the /RESET pin. Cautions 1. Whether reset is performed via the /RESET pin or the reset command, the contents of the display RAM are held. However, the RAM contents are undefined immediately following power application. 2. Calibration setting time tcal is set to the following value using the reset command. tcal = 1/fOSC x 30 70 Preliminary Product Information S16789EJ2V0PM PD161606 9. COMMAND 9.1 Command List (1/9) Register R0 Bit Symbol D7 DISP1 D6 DISP0 D5 INV D4 DTY D3 STBY D2 STBSEL D1 OSD D0 GSM Function This command performs the same output as when all data is 1, independently of the internal RAM data (white display in the case of normally white). This command is executed, after it has been transferred, when the next line is output. 0: Normal operation 1: Ignores data of RAM and outputs all data as 1. DISP1 takes precedence over DISP0. When DISP1 = H, DISP0 = H is ignored. This command performs the same output as when all data is 0, independently of the internal RAM data (black display in the case of normally white). This command is executed, after it has been transferred, when the next line is output. 0: Normal operation 1: Ignores data of RAM and outputs all data as 0. This command selects a line reversal function and a frame reversal function. Execution in the mode set by this command is from the timing which gate scan at the time of command execution ends to 360 lines, and the following scan starts. 0: Line inversion 1: frame inversion Selects the partial function. Execution of the mode selected with this command starts after gate scan during command execution completes 360 lines and the next scan starts. 0: Normal display mode 1: Partial display mode This bit selects the stand-by function. When the stand-by function is selected, a display OFF operation is executed, the amplifiers, and oscillator at each output stage are stopped. After executing the stand-by function using this bit, set the regulator for gate power supply Block to OFF and set the DC/DC converter to OFF. For the sequence, refer to the preliminary product information machine. Note that when releasing stand-by, perform the opposite operation, i.e., after setting the DC/DC converter to ON and setting the regulators to ON, set to 0 on this bit and execute the normal operation command. 0: Normal operation 1: Stand-by function Stand-by mode is chosen from two kinds of operation (Stand-by mode 1, Stand-by mode 2). Refer to 5.7 Stand-by for details of operation. 0: Stand-by mode 1 1: Stand-by mode 2 Selects the OSD function. Execution of the mode selected with this command starts after gate scan during command execution completes 360 lines and the next scan starts. This command becomes invalid at the time of partial display mode. 0: Normal display mode 1: OSD display mode Sets output of the gate scanning signal during partial display. If this bit is set to 1, the gate scan of the lines set in the partial non-display area is it carries out for every frame cycle set up by R52 register. 0: Normal mode 1: Gate scanning in partial non-display area is determined with the setting value to the setting value of R52 Preliminary Product Information S16789EJ2V0PM 71 PD161606 (2/9) Register R1 Bit Symbol Function D7 D6 D5 ADX ADY ADC Addressing of X address is inverted. For more details, refer to Figure 5-18. Addressing of Y address is inverted. For more details, refer to Figure 5-18. The direction of a column address. The direction of a sauce driver output can be select. For more details, refer to Figure 5-16. D4 OSC1OFF D3 OSC2OFF D2 COLOR D1 LTS D0 BGR This is oscillator circuit stop bit for calibration. This command is stop when in stand-by mode. 0: Oscillator operation 1: Oscillator stop This is oscillator circuit stop bit for LCD display. Regardless of setup of this bit, oscillation for LCD display is stop at the time of stand-by. 0: Oscillator operation 1: Oscillator stop Switches the 260K color mode and 8 colors mode. Execution of the mode selected with this command starts after gate scan during command execution completes 360 lines and the next scan starts. 0: 262,144 colors 1: 8 colors Selects set time of calibration. The calibration function adjusts the frame frequency by setting time of one line. This command can select the set time of aline form the following. 0: 1-line time = tcal 1: 1-line time = tcal x 2 (tcal: Calibration set time = 1 / Frame frequency / Number of displayed lines) In addition to changing the sequence of RGB data during RAM write, switches the relationship between the data input from RGB interface and the RGB data of the source output. (The R and B data are switched.) 0: Normal operation Source output (n = 1, 4, 7, ....) Data bus RAM Sn Sn+1 Sn+2 RGB25 to RGB20 D2 RGB15 to RGB10 D1 RGB05 to RGB00 D0 Sn Sn+1 Sn+2 RGB05 to RGB00 D2 RGB15 to RGB10 D1 RGB25 to RGB20 D0 1: Switch R and B data and perform write. Source output (n = 1, 4, 7, ....) Data bus RAM R2 72 D6 DCKEG D5 VSEG D4 HSEG Selects the DOTCLK active level. 0: High active 1: Low active Selects the VSYNC active level. 0: High active 1: Low active Selects the HSYNC active level. 0: High active 1: Low active Preliminary Product Information S16789EJ2V0PM PD161606 (3/9) Register Bit Symbol R3 D0 RES R4 D3 DSELPH D2 DSELNH D1 DESLPL D0 DSELNL D4 WAS D2 INC R6 D7 to D0 XAn R7 D6 to D0 YAn R8 D7 to D0 XMINn R9 D7 to D0 XMAXn R10 D6 to D0 YMINn R11 D6 to D0 YMAXn R5 Function Command reset function. Be sure to execute this bit after power ON. Command reset automatically clears this bit following execution (CRES = 1). Therefore, it is not necessary to set 0 (select normal operation) again by software. Moreover, since the time required for the value of this bit to change (1 0) following command reset execution is extremely short, it is not necessary to secure time until the command is set following command reset setting. 0: Normal operation 1: Command reset When the 8 colors mode is selected, sets the positive side black data drive method. 0: Inverter drive 1: Amplifier drive When the 8 colors mode is selected, sets the positive side black data drive method. 0: Inverter drive 1: Amplifier drive When the 8 colors mode is selected, sets the positive side black data drive method. 0: Inverter drive 1: Amplifier drive When the 8 colors mode is selected, sets the positive side black data drive method. 0: Inverter drive 1: Amplifier drive Window access mode setting When the window access mode is set, the address is incremented/decremented only in the range set by the MIN. X address setting register (R8), MAX. X address setting register (R9), MIN. Y address setting register (R10), and MAX. Y address setting register (R11). 0: Normal operation 1: Window access mode This bit selects the direction in which the address is to be incremented. 0: Increments X address 1: Increments Y address This register sets the X address of the display RAM. Set a value between 00H and EFH. This register sets the Y address of the display RAM. Set a value between 00H and 5FH. Sets the minimum value of the X address in the window access mode. The X address is incremented up to the maximum value set by the MAX. X address register (R9), and then initialized to the address value set by this command. Set this register to 00H to EFH. Sets the maximum value of the X address in the window access mode. The X address is incremented up to the maximum value set by the MIN. X address register (R8), and then initialized to the address value set by this command. Set this register to 00H to EFH. Sets the minimum value of the Y address in the window access mode. The Y address is incremented up to the maximum value set by the MAX. Y address register (R11), and then initialized to the address value set by this command. Set 00H to 5FH. Sets the maximum value of the Y address in the window access mode. The Y address is incremented up to the address value set by this command, and then initialized to the minimum address value set by the MIN. Y address register (R10). Set 00H to 5FH. Preliminary Product Information S16789EJ2V0PM 73 PD161606 (4/9) Register Bit Symbol Function R15 D6 to D0 P1SLn This is the start Y address register (00H to 5FH) of partial RAM data display area 1. During partial display or OSD display, the RAM data display area extends up to the line set with this command and the line count register (R16) of the partial RAM data display area 1. R16 D6 to D0 P1AWn This is the line count register (00H to 60H) of partial RAM data display area 1. During partial display or OSD display, the RAM data display area is from to the line set with this command and the start Y address register (R15) of partial RAM data display area 1. R17 D0 P1DLn Sets the display start line of partial RAM data display area 1 (00H to 168H). The display start line of area 1 is specified with R17 and R18. R17 R18 Start line 00H 00H 00H 01H Setting prohibited 1st line 01H 01H 67H 68H 359th line 360th line Perform settings so as to preserve the following relationship. R17.R18+R16R21.R22 R18 D7 to D0 P1DLn Sets the display start line of partial RAM display area 1. R19 D6 to D0 P2STn This is the start Y address register (00H to 5FH) of partial RAM data display area 2. During partial display or OSD display, the RAM data display area extends up to the line set with this command and the line count register (R20) of partial RAM data display area 2. R20 D6 to D0 P2AWn This is the line count register (00H to 60H) of partial RAM data display area 2. During partial display or OSD display, the RAM data display area is from to the line set with this command and the start Y address register (R19) of partial RAM data display area 2. R21 D0 P2DLn Sets the display start line of partial RAM data display area 2 (00H to 168H). The display start line of area 1 is specified with R21 and R22. R21 R22 Start line 00H 00H 00H 01H Setting prohibited 1st line 01H 01H 67H 68H 359th line 360th line Perform settings so as to preserve the following relationship. R17.R18+R16R21.R22 R22 D7 to D0 P2DLn Sets the display start line of partial RAM display area 2. R23 D2, D1, D0 PGR, PGC, PGB Partial OFF display color register Sets the screen color for areas other than the partial display area, during partial display (R0: DTY = 1). One color can be selected from among 8 colors (1 bit each for R, G, and B) and be set as the off color. The relationships between each color data and this register's bits are as follows. These relationships do not depend on the ADC value. Following transfer, this command is executed from the timing at which the next line data is output. PGR: OFF of R = 0, ON = 1 PGG: OFF of G = 0, ON = 1 PGB: OFF of B = 0, ON = 1 74 Preliminary Product Information S16789EJ2V0PM PD161606 When registers R24 to R34 are written to, the serial interface for PD161645 control is started and data transfer starts. (5/9) Register R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 Bit Symbol Function D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 D6 RGONR VS4ON VS3ON VS2ON VD2ON VD1ON DCON VRSEL2 VRSEL1 VRSEL0 VMS VCD2 FUP For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 D4 D3 D2 D7 to D0 D7 to D0 D5 D4 D3 D2 D1 D0 D0 CLS1 CLS0 FS3 FS2 FS1 FS0 ACS1 ACS0 EXRV VSEL2 VSEL1 VSEL0 RGON LACS1 LACS0 LFS3 LFS2 LFS1 LFS0 LPM 0E2SEL 0E1SEL STVSEL SCN2 SCN1 SCN0 COMHI COMSEL COMON Dan CDAn PONM PON DUPF1 DUPF0 PUPT1 PUPT0 RSE For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. For details, refer to the PD161645 preliminary products information. Preliminary Product Information S16789EJ2V0PM 75 PD161606 (6/9) Register R45 Bit D0 Symbol OC Function This bit is used for calibration. The time from calibration start command execution until calibration stop command execution becomes the time for 1 line. 0: Calibration stop 1: Calibration start R46 D5, D4 D3 to D0 DIVSLn HCKSLn Selects the horizontal interval clock division ratio. DIVSL1 DIVSL0 Division ratio Horizontal interval time 0 0 1 1 0 1 0 1 1 2 4 Setting prohibited 1 x HCKSLn setting value 2 x HCKSLn setting value 4 x HCKSLn setting value - Selects horizontal interval clock count during partial mode. Horizontal interval clock = [30 + (2 x HCKSLn setting value)] clock R50 D5 to D0 LNSELn HCKSL3 HCKSL2 HCKSL1 HCKSL0 Horizontal interval clock count Horizontal interval time 0 0 0 0 0 0 0 0 1 0 1 0 30 32 34 30 x DIVSLn setting value 32 x DIVSLn setting value 34 x DIVSLn setting value 1 1 1 1 1 1 0 1 58 Setting prohibited 58 x DIVSLn setting value - Selects gate scan line count. LNSEL5 0 0 0 LNSEL4 0 0 0 1 R51 D1, D0 NLINE1 NLINE0 R52 D1, D0 GSMLN1 GSMLN0 76 LNSEL3 0 0 0 LNSEL2 0 0 0 LNSEL1 0 0 1 0 1 0 1 Settings other than above prohibited LNSEL0 0 1 0 Line count 16 lines 24 lines 32 lines 1 360 lines Selects n line inversion line count. NLINE1 0 0 1 1 NLINE0 0 1 0 1 n line inversion line count n=1 n=2 n=4 n=8 Selects partial non-display area gate scan operation. GSMLN1 0 0 1 1 GSMLN0 0 1 0 1 Partial non-display area gate scan Gate scan stop Gate scan during 3 frames interval Gate scan during 5 frames interval Setting prohibited Preliminary Product Information S16789EJ2V0PM - PD161606 (7/9) Register R59 R65 Bit D1 Symbol GOE2ON D0 GOE1ON D1, D0 DCSELn Function Controls GOE2 output. 0: Normal operation 1: GOE2 output fixed to Low-level. (All gates ON) Selects gate scan ON/OFF based on GOE1 output. 0: Gate scan OFF (GOE1 fixed to Low-level) 1: Normal operation Selects DCCLK frequency. DCSEL1 0 0 1 1 R75 D7 to D0 HBPn R76 D7 to D0 VBPn R77 D0 DMSEL R78 D1 GSSEL D0 GCSEL R79 R80 R81 R82 D7 to D0 D7 to D0 D7 to D0 D7 to D0 GCEDn EQSTn EQEDn APSTn R83 D7 to D0 APEDn R86 D7 to D0 GOSTn R87 D7 to D0 GOEDn R88 R89 R90 R91 D5 to D0 D5 to D0 D5 to D0 D5 to D0 PGCEDn PEQSTn PEQEDn PAPSTn R92 D5 to D0 PAPEDn R93 D5 to D0 PGOSTn R94 D5 to D0 PGOEDn DCSEL0 0 1 0 1 Output frequency Output stop fOSC/30 fOSC/20 fOSC/10 Sets horizontal direction back porch interval for RGB interface. Horizontal back port interval = Setting value x DOTCLK unit Set the horizontal back porch interval to 3 or higher. Sets vertical direction back porch interval for RGB interface. Vertical back porch interval = Setting value x HSYNC unit Set the horizontal back porch interval to 1 or higher. Sets whether or not to perform dummy output to the first line of a frame. 0: Dummy line 1: No dummy line Inverts the GSTB signal polarity. 0: Low active 1: High active Inverts the GCLK signal's polarity. 0: When the HSYNC active level is input, GCLK = High results and changes to Low at the timing set to R79. 1: When the HSYNC active level is input, GCLK = Low results and changes to High at the timing set to R79. Sets the GCLK inversion timing during normal operation. Sets the equalize interval start position in the horizontal interval during normal operation. Sets the equalize interval end position in the horizontal during normal operation. Sets the start position of the amplifier driver interval in the horizontal interval during normal operation. Sets the end position of the amplifier driver interval in the horizontal interval during normal operation. Sets the start position (rising edge position) of the GOE1 signal in the horizontal interval during normal operation Sets the stop position (falling edge position) of the GOE1 signal in the horizontal interval during normal operation Sets the GCLK inversion timing in the partial display mode. Sets the start position of the equalize interval in the horizontal interval in the partial display mode. Sets the stop position of the equalize interval in the horizontal interval in the partial display mode. Sets the start position of the amplifier drive interval in the horizontal interval in the partial display mode. Sets the stop position of the amplifier drive interval in the horizontal interval in the partial display mode. Sets the start position (rising edge position) of the GOE1 signal in the horizontal interval during the partial display mode. Sets the stop position (falling edge position) of the GOE1 signal in the horizontal interval during the partial display mode. Preliminary Product Information S16789EJ2V0PM 77 PD161606 (8/9) Register Bit Symbol Function D4 to D2 D1, D0 D5 to D2 D1, D0 D3 RBIASn BBIASn ABIASn OPADJn GSELPH D2 GSELNH D1 GSELPL D0 GSELNL R101 D5 to D0 GPHn R102 D5 to D0 GNHn R103 D5 to D0 GPLn R104 D5 to D0 GNLn R105 D7 to D4 VDRPn D3 to D0 VSRPn D7 to D4 D3 to D0 D6 to D4 D2 to D0 D6 to D4 D2 to D0 D6 to D4 D2 to D0 D6 to D4 D2 to D0 D7 to D4 VLRPn VHRPn VGR1Pn VGR0Pn VGR3Pn VGR2Pn VGR5Pn VGR4Pn VGR7Pn VGR6Pn VDRNn D3 to D0 VSRNn D7 to D4 D3 to D0 D6 to D4 D2 to D0 VLRNn VHRNn VGR1Nn VGR0Nn Adjust the bias of the - operational amplifier. Adjust the bias of the operational amplifier in the bias circuit. Adjust the bias of the output operational amplifier. Adjust the capacity of the output operational amplifier. Sets the output source power supply for the black data on the positive side of the - compensation resistor. 0: Sets power supply voltage. (Outputs VS, VSS potential) 1: Uses internal - output adjustment circuit. (Uses VPH, VNH, VPL, and VNL outputs) Sets the output source power supply for the white data on the negative side of the - compensation resistor. 0: Sets power supply voltage. (Outputs VS, VSS potential) 1: Uses internal - output adjustment circuit. (Uses VPH, VNH, VPL, and VNL outputs) Sets the output source power supply for the white data on the positive side of the - compensation resistor. 0: Sets power supply voltage. (Outputs VS, VSS potential) 1: Uses internal - output adjustment circuit. (Uses VPH, VNH, VPL, and VNL outputs) Sets the output source power supply for the black data on the negative side of the - compensation resistor. 0: Sets power supply voltage. (Outputs VS, VSS potential) 1: Uses internal - output adjustment circuit. (Uses VPH, VNH, VPL, and VNL outputs) Positive-polarity - amplitude adjustment register. Refer to 5.5.1 Amplitude adjustment with internal amplifier. Negative-polarity - amplitude adjustment register. Refer to 5.5.1 Amplitude adjustment with internal amplifier. Positive-polarity - amplitude adjustment register. Refer to 5.5.1 Amplitude adjustment with internal amplifier. Negative-polarity - amplitude adjustment register. Refer to 5.5.1 Amplitude adjustment with internal amplifier. Positive-polarity - amplitude adjustment register. Refer to 5.5.2 Amplitude adjustment by built-in resistance. Positive-polarity - amplitude adjustment register. Refer to 5.5.2 Amplitude adjustment by built-in resistance. Positive-polarity - tilt adjustment register. Refer to 5.5.3 Inclination adjustment. Positive-polarity - tilt adjustment register. Refer to 5.5.3 Inclination adjustment. Positive-polarity - fine adjustment register. Refer to 5.5.4 Fine tunig adjustment. Positive-polarity - fine adjustment register. Refer to 5.5.4 Fine tunig adjustment. Positive-polarity - fine adjustment register. Refer to 5.5.4 Fine tunig adjustment. Positive-polarity - fine adjustment register. Refer to 5.5.4 Inclination adjustment. Positive-polarity - tilt adjustment register. Refer to 5.5.3 Inclination adjustment. Positive-polarity - tilt adjustment register. Refer to 5.5.3 Inclination adjustment. Positive-polarity - tilt adjustment register. Refer to 5.5.3 Inclination adjustment. Positive-polarity - tilt adjustment register. Refer to 5.5.3 Inclination adjustment. Negative-polarity - amplitude adjustment register. Refer to 5.5.2 Amplitude adjustment by built-in resistance. Negative-polarity - amplitude adjustment register. Refer to 5.5.2 Amplitude adjustment by built-in resistance. Negative-polarity - inclination adjustment register. Refer to 5.5.3 Inclination adjustment. Negative-polarity - inclination adjustment register. Refer to 5.5.3 Inclination adjustment. Negative-polarity - fine adjustment register. Refer to 5.5.4 Fine tunig adjustment. Negative-polarity - fine adjustment register. Refer to 5.5.4 Inclination adjustment. R95 R96 R100 R106 R107 R108 R109 R110 R111 R112 R113 78 Preliminary Product Information S16789EJ2V0PM PD161606 (9/9) Register R114 R115 Bit D6 to D4 VGR3Nn D2 to D0 VGR2Nn VGR5Nn D6 to D4 D2 to D0 R116 R117 Symbol Function Negative-polarity - fine adjustment register. Refer to 5.5.4 Fine tuningadjustment. Negative-polarity - fine adjustment register. Refer to 5.5.4 Fine tuning adjustment. Negative-polarity - inclination adjustment register. Refer to 5.5.3 Inclination adjustment. Negative-polarity - inclination adjustment register. Refer to 5.5.3 Inclination adjustment. D6 to D4 VGR4Nn VGR7Nn D2 to D0 VGR6Nn Negative-polarity - inclination adjustment register. Refer to 5.5.3 Inclination adjustment. Negative-polarity - inclination adjustment register. Refer to 5.5.3 Inclination adjustment. D0 NWBSL Switches normally white and normally black. 0: Normally white 1: Normally black 2 R118 D2 to D0 - E PROM OPC set R119 D7 to D0 - E PROM write address specify R120 D6 to D0 - E PROM write register address specify R121 D7 to D0 - E PROM fabrication information register R122 D7 to D0 - E PROM fabrication information register R123 D7 to D0 - E PROM fabrication information register R124 D7 to D0 - E PROM read start address specify R125 D1, D0 - E PROM OSC divide register 2 2 2 2 2 2 2 2 Selects the serial clock frequency of E PROM interface. D1 0 0 1 1 R126 D1, D0 - D0 0 1 0 1 2 E PROM interface serial clock frequency Interface oscillation frequency/2 Interface oscillation frequency/4 Interface oscillation frequency/8 Interface oscillation frequency/16 PD161645 OSC divide register Selects the serial clock frequency of the PD161645 interface. D1 0 0 1 1 R127 D7 to D0 - D0 0 1 0 1 2 E PD161645 interfaceserial serialclock clockfrequency frequency PROM interface Interface oscillation frequency/1 frequency/2 Interface oscillation frequency/2 frequency/4 Interface oscillation frequency/4 frequency/8 Interface oscillation oscillation frequency/16 frequency/6 Interface 2 E PROM read stop register Preliminary Product Information S16789EJ2V0PM 79 PD161606 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C, VSS = 0 V) Parameter Symbol Ratings Unit Power supply voltage VCC1 -0.5 to +3.0 V Power supply voltage VCC2 -0.5 to +6.0 V Power supply voltage VCC3 -0.5 to +6.0 V Power supply voltage VS -0.5 to +6.0 V Power supply voltage VSG -0.5 to +6.0 V -0.5 to VCC2 + 0.5 V -0.5 to VS + 0.5 V 10 mA Input voltage VI1 Input voltage VI2 Input current II Note1 Note2 Output current IO 10 mA Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -55 to +125 C Notes 1. Power supply system is pin of VCC2. 2. Power supply system is pin of VS. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = -40 to +85C, VSS = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Power supply voltage VCC1 1.65 2.5 V Power supply voltage VCC2 1.65 3.3 V Power supply voltage VCC3 1.65 3.3 V Power supply voltage VS 4.0 5.0 5.5 V Power supply voltage VSG 4.0 5.0 Input voltage VI1 Input voltage VI2 Note1 Note2 5.5 V 0 VCC2 V 0 VS V Notes 1. Power supply system is pin of VCC2. 2. Power supply system is pin of VS. 80 Preliminary Product Information S16789EJ2V0PM PD161606 Electrical Specifications (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 1.7 to 2.5 V, VCC2 = 1.7 to 3.3 V, VCC3 = 1.7 to 3.3 V, VSS = 0 V) Parameter Input leakage Symbol Condition VIH VCC2 Low level input voltage VIL VCC2 Low level output voltage High level input current TYP. Note1 ILI High level input voltage High level output voltage MIN. MAX. Unit 10 A 0.2 VCC2 V 0.8 VCC2 V VOH1 VCC2, IOUT = -100 A 0.8 VCC2 VOH2 VCC3, IOUT = -100 A 0.8 VCC3 VOL1 VCC2, IOUT = -100 A 0.2 VCC2 VOL2 VCC3, IOUT = -100 A 0.2 VCC3 V IIH VCC2 3 A Low level input current IIL VCC2 SF_VCC1 output voltage SF_VCC1 ISFVCC1 = 10 mA SF_VCC1 output resistor RSFVCC1 Source driver output voltage VP-P V V A -3 1.65 V 2.0 1 VSS + 0.1 2.5 V 10 VS - 0.1 V T.B.D. A T.B.D. A T.B.D. mV s range Source driver output current IVOH VOUT = VS - 0.1, VX = VOUT - 0.5 V IVOL VOUT = VSS + 0.1, VX = VOUT + 0.5 V Source driver output bias VO T.B.D. Source driver output delay tPHLSI CL = T.B.D. pF T.B.D. T.B.D. time tPLHSI CL = T.B.D. pF T.B.D. T.B.D. s Current consumption ICC1 VCC1 (when non-access CPU) T.B.D. T.B.D. A ICC2 VCC2 (when non-access CPU) T.B.D. T.B.D. A ICC3 VCC3 (when non-access CPU) T.B.D. T.B.D. A IS VS T.B.D. T.B.D. A ISC VSG T.B.D. T.B.D. A ISTBY VCC1 (stand-by mode) 10 A 10 A VCC3 (stand-by mode) 10 A VS (stand-by mode) 10 A VSG (stand-by mode) 10 A VCC2 (stand-by mode) Note 2 Notes 1. TYP. values are reference values when TA = 25C 2. VSTBY = L Preliminary Product Information S16789EJ2V0PM 81 PD161606 AC Characteristics (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 1.7 to 2.5 V, VCC2 = 1.7 to 3.3 V, VCC3 = 1.7 to 3.3 V, VSS = 0 V) (a) 18-/16-bit RGB interface Horizontal system tCLK tDH tDS DOTCLK tHBP RGB00 to RGB25 tHSS tHSH HSYNC tHSW 1st pixel 2nd pixel Last Data tHS VSYNC tVSS Vertiacal system HSYNC tVBP RGB00 to RGB25 VSYNC 1st line 2nd line Last line tVS tVSW Parameter Symbol Condition MIN. TYP. MAX. Unit Dot clock cycle time tCLK 114 ns Dot clock high level pulse width tCLKH 40 ns Dot clock low level pulse width tCLKL 40 ns Data setup time tDS 10 ns Data hold time tDH 10 ns HSYNC pulse width tHSW 1 DOTCLK HSYNC setup time tHSS 10 ns HSTNC hold time tHSH 10 ns Horizon period back porch time tHBP 3 DOTCLK VSYNC pulse width tVSW 1 HS VSYNC setup time tVSS 10 ns Vertical period back porch time tVBP 1 HS Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC1. 3. The minimum number of DOTCLK clocks that should be input per 1 horizontal interval is as follows. DOTCLK count for 1 horizontal interval (DOTCLK count of HSYNC Low interval) + (horizontal back porch interval) + (pixel display interval 240 times) + 1 = 245 4. The number of HSYNC that should be input per 1 frame interval as follows. HSYNC for 1 frame interval (HSYNC count during VSYNC Low interval) + (vertical back porch interval) + (pixel display interval) 82 Preliminary Product Information S16789EJ2V0PM PD161606 (b) 6-bit RGB interface Horizontal system tDH tDS tCLK DOTCLK ENABLE RGB20 to RGB25 tHSS tHSH tHBP tHSW HSYNC R Data G Data B Data Last data tHS VSYNC tVSS Vertical system HSYNC tVBP RGB20 to RGB25 VSYNC 1st line tVSW Parameter Symbol Last line tVS Condition MIN. TYP. MAX. Unit Dot clock cycle time tCLK 38 ns Dot clock high level pulse width tCLKH 15 ns Dot clock low level pulse width tCLKL 15 ns Data setup time tDS 10 ns Data hold time tDH 10 ns HSYNC pulse width tHSW 3 DOTCLK HSYNC setup time tHSS 10 ns HSTNC hold time tHSH 10 ns Horizon period back porch time tHBP 9 DOTCLK VSYNC pulse width tVSW 1 HS VSYNC setup time tVSS 10 ns Vertical period back porch time tVBP 1 HS Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC1. 3. The minimum number of DOTCLK clocks that should be input per 1 horizontal interval is as follows. DOTCLK count for 1 horizontal interval (DOTCLK count of HSYNC Low interval) + (horizontal back porch interval) + (pixel display interval 240 times * 3) + 3 = 735 4. The number of HSYNC that should be input per 1 frame interval as follows. HSYNC for 1 frame interval (HSYNC count during VSYNC Low interval) + (vertical back porch interval) + (pixel display interval) Preliminary Product Information S16789EJ2V0PM 83 PD161606 (c) i80 CPU interface RS tAS8 tf tr tAH8 /CS tCYC8 tCCLW, tCCLR /WR, /RD tCCHR, tCCHW tDS8 tDH8 D0 to D7 (Write) tOH8 tACC8 D0 to D7 (Read) (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 1.7 to 2.5 V, VCC2 = 1.7 to 3.3 V, VCC3 = 1.7 to 3.3 V, VSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Address hold time tAH8 RS 0 ns Address setup time tAS8 RS 0 ns System cycle time tCYC8 Read (Register) 250 ns Read (RAM) 450 ns Write 120 ns Control low-level pulse width (/WR) tCCLW /WR 60 ns Control low-level pulse width (/RD) tCCLR /RD (Register) 140 ns /RD (RAM) 320 ns /WR 40 ns /RD (Register) 80 ns /RD (RAM) 80 ns Control high-level pulse width (/WR) tCCHW Control high-level pulse width (/RD) tCCHR Write Read time TW to R8 /WR (RAM), /RD (RAM) T.B.D. ns Data setup time tDS8 D0 to D7 50 ns Data hold time tDH8 D0 to D7 0 /RD access time (Register) tACC8 D0 to D7, CL = 100 pF tOH8 D0 to D7, CL = 100 pF /RD access time (RAM) Output disable time Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. 84 Preliminary Product Information S16789EJ2V0PM ns 120 ns 300 ns 100 ns PD161606 (d) M68 CPU interface RS R,/W tAS6 tf tr tAH6 /CS tCYC6 tEWHR, tEWHW E tEWLR, tEWLW tDS6 tDH6 D0 to D7 (Write) tACC6 tOH6 D0 to D7 (Read) (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 1.7 to 2.5 V, VCC2 = 1.7 to 3.3 V, VCC3 = 1.7 to 3.3 V, VSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Address hold time tAH6 RS 0 Address setup time tAS6 RS 0 ns ns System cycle time tCYC6 Read (Register) 250 ns Read (RAM) 450 ns Write 120 ns Data setup time tDS6 D0 to D7 50 ns Data hold time tDH6 D0 to D7 0 ns Access time (Register) tACC6 D0 to D7, CL = 100 pF Access time (RAM) 120 ns 300 ns Write Read time TW to R6 /WR (RAM), /RD (RAM) Output disable time tOH6 D0 to D7, CL = 100 pF Read tEWHR E (Register) 140 E (RAM) 320 ns Write tEWHW E 60 ns Read tEWLR E (Register) 80 ns E (RAM) 80 ns E 40 ns Enable high pulse width Enable low pulse width Write tEWLW T.B.D. ns 100 ns ns Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. Preliminary Product Information S16789EJ2V0PM 85 PD161606 (e) Serial interface tCSS tCSH /CS tSAS tSAH tSWRS tSWRH RS R,/W tSCYC tSLW SCL tf tr tSDS tSHW tSDH SI tOHS tACCS SO (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 1.7 to 2.5 V, VCC2 = 1.7 to 3.3 V, VCC3 = 1.7 to 3.3 V, VSS = 0 V) Parameter Serial clock cycle SCL high level pulse width SCL low level pulse width Symbol tSCYC tSHW MIN. TYP. MAX. Unit Read 300 ns Write 66 ns Read 140 ns Write 25 ns Read 140 ns Write 25 ns tCSS /CS 30 ns /CS hold time tCSH /CS 20 ns RS set up time tSAS RS 30 ns RS hold time tSAH RS 20 ns R,/W set up time tSWRS R,/W 30 ns R,/W hold time tSWRH R,/W 20 ns Data set up time tSDS SI 20 ns Data hold time tSDH SI 10 Access time tACCS SCL = 100 pF 120 ns Output disable time tOHS SCL = 100 pF 100 ns /CS set up time tSLW Condition Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. 86 Preliminary Product Information S16789EJ2V0PM ns PD161606 (f) Common Parameter Symbol Condition Note2, fFRAME = 60 Hz TYP. Note1 MAX. Unit 44.3 s (60) (Hz) 60 Hz 60 Hz Calibration setting time tcal (frame frequency) (fFRAME0) Frame frequency fFRAME2 Calibrated Frame frequency fFRAME3 Calibrated Frame frequency fFRAME4 Before calibration, OSCSEL = L T.B.D. T.B.D. T.B.D. kHz Oscillation frequency fOSC1 OSCSEL = L T.B.D. T.B.D. T.B.D. kHz T.B.D. T.B.D. T.B.D. kHz 1745 kHz fOSC2 Note3 Note4 VCC1 = 2.3 V, OSCSEL = H, R = T.B.D. k MIN. External oscillation frequency fOSCIN Reset pulse width at the time tVR Note5 338 VSTBY = L, SF_VCC1 = 4.7 F 2 ms 2 s 500 ns of power supply injection Reset pulse width tRW Reset time tR /RESET to interface operation Notes 1. TYP. values are reference values when TA = 25C. 2. The relationship between the frame frequency and the calibration setting time is as follows. tcal = 1/(fFRAME x (360 + 16)) 3. Measured at TA = -40 to +85C, after calibration at frame frequency = 60 Hz, TA = 25C exactly. 4. Measured at 5C, after calibration at frame frequency = 60 Hz exactly. 5. Since oscillation frequency is changed with a parasitism capacity value in external resistance, please refer to as a standard. Preliminary Product Information S16789EJ2V0PM 87 PD161606 11. EXAMPLE OF PD161606 AND CPU CONNECTION Examples of PD161606 and CPU connection are shown below. In the example below, RS pin control in parallel interface mode is described for the case when the least significant bit of the address bus is being used. (1)i80seriesformat PD161606 CPU V DD PD161606 CPU V DDIO V DD V DDIO VSYNC VSYNC VSYNC VSYNC HSYNC HSYNC HSYNC HSYNC DOTCLK RGB 00 toRGB 25 DOTCLK RGB 00 toRGB 25 DOTCLK RGB 00 toRGB 25 DOTCLK RGB 00 toRGB 25 /CS /CS /CS /CS PortorA0 RS PortorA0 RS D0toD7 D0toD7 D0toD7 D0toD7 /RD /RD /RD /RD /WR /WR /WR /WR /RESET V SS 88 (2)M68seriesformat /RESET /RESET V SS1 V SS Preliminary Product Information S16789EJ2V0PM /RESET V SS1 PD161606 RIVISION HISTORY Edition/ Date Page Description This Previous Type of edition edition revision Preliminary Product Information S16789EJ2V0PM Location 89 PD161606 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 90 Preliminary Product Information S16789EJ2V0PM PD161606 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) * The information contained in this document is being issued in advance of the production cycle for the product. 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