uPD161606 - NEC Electronics

The information contained in this document is being issued in advance of the production cycle for the

product. The parameters for the product may change before final production or NEC Electronics

Corporation, at its own discretion, may withdraw the product prior to its production.

Not all products and/or types are availabe in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

MOS INTEGRATED CIRCUIT

PD161606

720 OUTPUTS TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR

PRELIMINARY PRODUCT INFORMATION

Document No. S16789EJ2V0PM00 (2nd edition)

Date Published March 2004 NS CP(K)

Printed in Japan

2003

The mark ★ shows major revised points.

DESCRIPTION

The

 PD161606 is a TFT-LCD source driver that includes display RAM.

This driver has 720 outputs, a display RAM capacity of 115,200 bits (240 pixels x 3 bits x 96 lines + α rendering flag) of

partial display RAM.

FEATURES

• TFT-LCD driver with on-chip display RAM

• Logic power supply voltage: 1.7 to 2.5 V (Generating inside a chip is also possible from power supply IC interface power

supply)

• CPU/RGB interface power supply voltage: 1.7 to 3.3 V

• Gate driver power supply voltage: 1.7 to 3.3 V

• Driver power supply voltage: 4.0 to 5.5 V

• Display RAM: 240 x 3 x 96 bits

• Driver outputs: 720 outputs

• CPU interface: Three types of interfaces selectable

⋅ 6-bit/16-bit/18-bit RGB interface

⋅ i80/M68 parallel interface (selectable from 8-bit)

⋅ 8-bit serial interface (SPI correspondence)

• Colors: 262,144 colors/pixel

• On-chip timing generator

• On-chip oscillator

ORDERING INFORMATION

Part Number Package

PD161606P Chip

Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum on

product quality, so please contact one of our sales representatives.

Preliminary Product Information S16789EJ2V0PM

PD161606

CONTENTS

1. BLOCK DIAGRAM.....................................................................................................................................4

2. PIN CONFIGURATION (Pad Layout) ......................................................................................................5

3. PIN FUNCTIONS........................................................................................................................................9

3.1 Power Supply System Pins ............................................................................................................................... 9

3.2 Logic System Pins ........................................................................................................................................... 11

3.3 Driver Pins ........................................................................................................................................................ 13

3.4 Pins for Gate Control Interface Power Supply............................................................................................... 13

3.5 E2PROM Control Pins ...................................................................................................................................... 14

3.6 Test or Other Pins ............................................................................................................................................ 14

4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS....................................15

5. DESCRIPTION OF FUNCTIONS.............................................................................................................17

5.1 Interface ............................................................................................................................................................ 17

5.1.1 Selection of interface type...................................................................................................................... 17

5.1.2 RGB interface......................................................................................................................................... 18

5.1.3 i80/M68 Parallel interface....................................................................................................................... 23

5.1.4 Serial interface ....................................................................................................................................... 25

5.1.5 Chip select ............................................................................................................................................. 28

5.1.6 Access to display data RAM and internal registers ................................................................................ 28

5.1.7

PD161645 control serial interface ....................................................................................................... 34

5.2 Partial Display RAM ......................................................................................................................................... 35

5.2.1 X address circuit..................................................................................................................................... 35

5.2.2 Y address circuit..................................................................................................................................... 36

5.2.3 Arbitrary address area access (window access mode (WAS))............................................................... 38

5.3 Oscillator........................................................................................................................................................... 40

5.4 Display Timing Generator................................................................................................................................ 41

5.5

- Curve Correction Circuit............................................................................................................................. 45

5.5.1 Amplitude adjustment with internal amplifier .......................................................................................... 46

5.5.2 Amplitude adjustment by bulit-in resistance ........................................................................................... 48

5.5.3 Inclination adjustment ............................................................................................................................ 49

5.5.4 Fine tuning adjustment........................................................................................................................... 50

5.6 Partial Display Function .................................................................................................................................. 51

5.7 Stand-by............................................................................................................................................................ 52

Preliminary Product Information S16789EJ2V0PM 3

PD161606

5.7.1 Stand-by mode 1.................................................................................................................................... 52

5.7.2 Stand-by mode 2.................................................................................................................................... 53

6. POWER SUPPLY INJECTION/INTERCEPTION ....................................................................................57

6.1

PD161606 Power Supply Injection Setting Sequence Example ................................................................ 57

6.2

PD161606 Power Supply Interception Setting Sequence Example .......................................................... 61

7. E2PROM INTERFACE..............................................................................................................................62

7.1 The

PD161606 and E2PROM Connection .................................................................................................... 62

7.2 Each Operation................................................................................................................................................. 63

8. RESET......................................................................................................................................................68

9. COMMAND...............................................................................................................................................71

9.1 Command List .................................................................................................................................................. 71

10. ELECTRICAL SPECIFICATIONS..........................................................................................................80

11. EXAMPLE OF THE

PD161606 AND CPU CONNECTION ................................................................88

Preliminary Product Information S16789EJ2V0PM

PD161606

1. BLOCK DIAGRAM

T.B.D.

Remark T.B.D.: To be determined.

Preliminary Product Information S16789EJ2V0PM 5

PD161606

2. PIN CONFIGURATION (Pad Layout)

Chip size: 2.4 x 19.5 mm2

Bump size (output, including long side and short side): 90 x 26

Bump size (input): 106 x 54

Alignment mark (mark center, unit:

X Y

AM1 1025 9575

AM2 1025 −9575

Alignment mark size

30µm40µm30µm

30µm

40µm

30µm

★

Preliminary Product Information S16789EJ2V0PM

PD161606

Table 2–1. Pad Coordinate (1/3)

PIN No. PIN NAME X Y PIN No. PIN NAME X Y PIN No. PIN NAME X Y

1 DUMMY -1038.26 9330.00 101 RGB10 -1038.26 -1670.00 201 S27 584.70 -9596.26

2 GSTB -1038.26 9220.00 102 RGB05 -1038.26 -1780.00 202 S28 629.70 -9461.26

3 GCLK -1038.26 9110.00 103 RGB04 -1038.26 -1890.00 203 S29 674.70 -9596.26

4 VCOUT -1038.26 9000.00 104 RGB03 -1038.26 -2000.00 204 S30 719.70 -9461.26

5 EQ -1038.26 8890.00 105 RGB02 -1038.26 -2110.00 205 DUMM

764.70 -9596.26

6 GOE2 -1038.26 8780.00 106 RGB01 -1038.26 -2220.00 206 DUMM

1046.26 -9254.00

7 GOE1 -1038.26 8670.00 107 RGB00 -1038.26 -2330.00 207 S31 911.26 -9226.00

8 GSO -1038.26 8560.00 108 HSYNC -1038.26 -2440.00 208 S32 1046.26 -9198.00

9 GCS -1038.26 8450.00 109 VSYNC -1038.26 -2550.00 209 S33 911.26 -9170.00

10 GSCLK -1038.26 8340.00 110 DOTCLK -1038.26 -2660.00 210 S34 1046.26 -9142.00

11 DCCLK -1038.26 8230.00 111

RESET -1038.26 -2770.00 211 S35 911.26 -9114.00

12 GRESET -1038.26 8120.00 112 TIN2 -1038.26 -2880.00 212 S36 1046.26 -9086.00

13 DUMMY -1038.26 8010.00 113 TIN1 -1038.26 -2990.00 213 S37 911.26 -9058.00

14 DUMMY -1038.26 7900.00 114 TIN0 -1038.26 -3100.00 214 S38 1046.26 -9030.00

15 DUMMY -1038.26 7790.00 115 TESTO17 -1038.26 -3210.00 215 S39 911.26 -9002.00

16 VCC3 -1038.26 7680.00 116 TESTO16 -1038.26 -3320.00 216 S40 1046.26 -8974.00

17 VCC3 -1038.26 7570.00 117 TESTO15 -1038.26 -3430.00 217 S41 911.26 -8946.00

18 VCC3 -1038.26 7460.00 118 TESTO14 -1038.26 -3540.00 218 S42 1046.26 -8918.00

19 VCC3 -1038.26 7350.00 119 TESTO13 -1038.26 -3650.00 219 S43 911.26 -8890.00

20 VSS -1038.26 7240.00 120 TESTO12 -1038.26 -3760.00 220 S44 1046.26 -8862.00

21 VSS -1038.26 7130.00 121 TESTO11 -1038.26 -3870.00 221 S45 911.26 -8834.00

22 VSS -1038.26 7020.00 122 TESTO10 -1038.26 -3980.00 222 S46 1046.26 -8806.00

23 VSS -1038.26 6910.00 123 TESTO9 -1038.26 -4090.00 223 S47 911.26 -8778.00

24 VS -1038.26 6800.00 124 TESTO8 -1038.26 -4200.00 224 S48 1046.26 -8750.00

25 VS -1038.26 6690.00 125 TESTO7 -1038.26 -4310.00 225 S49 911.26 -8722.00

26 VS -1038.26 6580.00 126 TESTO6 -1038.26 -4420.00 226 S50 1046.26 -8694.00

27 VS -1038.26 6470.00 127 TESTO5 -1038.26 -4530.00 227 S51 911.26 -8666.00

28 VSS -1038.26 6360.00 128 TESTO4 -1038.26 -4640.00 228 S52 1046.26 -8638.00

29 VSS -1038.26 6250.00 129 TESTO3 -1038.26 -4750.00 229 S53 911.26 -8610.00

30 VSS -1038.26 6140.00 130 TESTO2 -1038.26 -4860.00 230 S54 1046.26 -8582.00

31 VSS -1038.26 6030.00 131 TESTO1 -1038.26 -4970.00 231 S55 911.26 -8554.00

32 VSS -1038.26 5920.00 132 TESTO0 -1038.26 -5080.00 232 S56 1046.26 -8526.00

33 VSS -1038.26 5810.00 133 TOSC1SEL -1038.26 -5190.00 233 S57 911.26 -8498.00

34 VCOM EQ1 -1038.26 5700.00 134 TOSC1IN -1038.26 -5300.00 234 S58 1046.26 -8470.00

35 VCOM EQ2 -1038.26 5590.00 135 DVCC2 -1038.26 -5410.00 235 S59 911.26 -8442.00

36 VCOM EQ3 -1038.26 5480.00 136 DVSS -1038.26 -5520.00 236 S60 1046.26 -8414.00

37 VCOM EQ4 -1038.26 5370.00 137 OSC2SEL -1038.26 -5630.00 237 S61 911.26 -8386.00

38 VSG -1038.26 5260.00 138 OSC2IN -1038.26 -5740.00 238 S62 1046.26 -8358.00

39 VSG -1038.26 5150.00 139 OSC2OUT -1038.26 -5850.00 239 S63 911.26 -8330.00

40 VSG -1038.26 5040.00 140 VSS -1038.26 -5960.00 240 S64 1046.26 -8302.00

41 VSG -1038.26 4930.00 141 VSS -1038.26 -6070.00 241 S65 911.26 -8274.00

42 CVNH1 -1038.26 4820.00 142 VSS -1038.26 -6180.00 242 S66 1046.26 -8246.00

43 CVNH2 -1038.26 4710.00 143 VSS -1038.26 -6290.00 243 S67 911.26 -8218.00

44 CVPH1 -1038.26 4600.00 144 VCC1 -1038.26 -6400.00 244 S68 1046.26 -8190.00

45 CVPH2 -1038.26 4490.00 145 VCC1 -1038.26 -6510.00 245 S69 911.26 -8162.00

46 CVNL1 -1038.26 4380.00 146 VCC1 -1038.26 -6620.00 246 S70 1046.26 -8134.00

47 CVNL2 -1038.26 4270.00 147 VCC1 -1038.26 -6730.00 247 S71 911.26 -8106.00

48 CVPL1 -1038.26 4160.00 148 SF VCC1 -1038.26 -6840.00 248 S72 1046.26 -8078.00

49 CVPL2 -1038.26 4050.00 149 SF VCC2 -1038.26 -6950.00 249 S73 911.26 -8050.00

50 DVSS -1038.26 3940.00 150 SF VCC3 -1038.26 -7060.00 250 S74 1046.26 -8022.00

51 BWS1 -1038.26 3830.00 151 SF VCC4 -1038.26 -7170.00 251 S75 911.26 -7994.00

52 DVCC2 -1038.26 3720.00 152 VSS -1038.26 -7280.00 252 S76 1046.26 -7966.00

53 BWS0 -1038.26 3610.00 153 VSS -1038.26 -7390.00 253 S77 911.26 -7938.00

54 DVSS -1038.26 3500.00 154 VSS -1038.26 -7500.00 254 S78 1046.26 -7910.00

55 PSX -1038.26 3390.00 155 VSS -1038.26 -7610.00 255 S79 911.26 -7882.00

56 DVCC2 -1038.26 3280.00 156 VCC2 -1038.26 -7720.00 256 S80 1046.26 -7854.00

57 SSEL -1038.26 3170.00 157 VCC2 -1038.26 -7830.00 257 S81 911.26 -7826.00

58 DVSS -1038.26 3060.00 158 VCC2 -1038.26 -7940.00 258 S82 1046.26 -7798.00

59 C86 -1038.26 2950.00 159 VCC2 -1038.26 -8050.00 259 S83 911.26 -7770.00

60 DVCC2 -1038.26 2840.00 160 VSTBY -1038.26 -8160.00 260 S84 1046.26 -7742.00

61 CSEG -1038.26 2730.00 161 DVSS -1038.26 -8270.00 261 S85 911.26 -7714.00

62 DVSS -1038.26 2620.00 162 VS -1038.26 -8380.00 262 S86 1046.26 -7686.00

63 SCLEG1 -1038.26 2510.00 163 VS -1038.26 -8490.00 263 S87 911.26 -7658.00

64 DVCC2 -1038.26 2400.00 164 VS -1038.26 -8600.00 264 S88 1046.26 -7630.00

65 SCLEG0 -1038.26 2290.00 165 VS -1038.26 -8710.00 265 S89 911.26 -7602.00

66 DVSS -1038.26 2180.00 166 VSS -1038.26 -8820.00 266 S90 1046.26 -7574.00

67 RSEL -1038.26 2070.00 167 VSS -1038.26 -8930.00 267 S91 911.26 -7546.00

68 DVCC2 -1038.26 1960.00 168 VSS -1038.26 -9040.00 268 S92 1046.26 -7518.00

69 ECS -1038.26 1850.00 169 VSS -1038.26 -9150.00 269 S93 911.26 -7490.00

70 ESK -1038.26 1740.00 170 VSS -1038.26 -9260.00 270 S94 1046.26 -7462.00

71 EDI -1038.26 1630.00 171 VSS -1038.26 -9370.00 271 S95 911.26 -7434.00

72 EDO -1038.26 1520.00 172 DUMMY -1038.26 -9480.00 272 S96 1046.26 -7406.00

73 DVSS -1038.26 1410.00 173 DUMMY -675.30 -9596.26 273 S97 911.26 -7378.00

74 /RD

(

)

-1038.26 1300.00 174 DUMMY -630.30 -9461.26 274 S98 1046.26 -7350.00

75 /WR

(

)

-1038.26 1190.00 175 S1 -585.30 -9596.26 275 S99 911.26 -7322.00

76 D7 -1038.26 1080.00 176 S2 -540.30 -9461.26 276 S100 1046.26 -7294.00

77 D6 -1038.26 970.00 177 S3 -495.30 -9596.26 277 S101 911.26 -7266.00

78 D5 -1038.26 860.00 178 S4 -450.30 -9461.26 278 S102 1046.26 -7238.00

79 D4 -1038.26 750.00 179 S5 -405.30 -9596.26 279 S103 911.26 -7210.00

80 D3 -1038.26 640.00 180 S6 -360.30 -9461.26 280 S104 1046.26 -7182.00

81 D2 -1038.26 530.00 181 S7 -315.30 -9596.26 281 S105 911.26 -7154.00

82 D1 -1038.26 420.00 182 S8 -270.30 -9461.26 282 S106 1046.26 -7126.00

83 D0 -1038.26 310.00 183 S9 -225.30 -9596.26 283 S107 911.26 -7098.00

84 /CS -1038.26 200.00 184 S10 -180.30 -9461.26 284 S108 1046.26 -7070.00

85 RS -1038.26 90.00 185 S11 -135.30 -9596.26 285 S109 911.26 -7042.00

86 SO -1038.26 -20.00 186 S12 -90.30 -9461.26 286 S110 1046.26 -7014.00

87 SI -1038.26 -130.00 187 S13 -45.30 -9596.26 287 S111 911.26 -6986.00

88 SCL -1038.26 -240.00 188 S14 -0.30 -9461.26 288 S112 1046.26 -6958.00

89 DVSS -1038.26 -350.00 189 S15 44.70 -9596.26 289 S113 911.26 -6930.00

90 RGB25 -1038.26 -460.00 190 S16 89.70 -9461.26 290 S114 1046.26 -6902.00

91 RGB24 -1038.26 -570.00 191 S17 134.70 -9596.26 291 S115 911.26 -6874.00

92 RGB23 -1038.26 -680.00 192 S18 179.70 -9461.26 292 S116 1046.26 -6846.00

93 RGB22 -1038.26 -790.00 193 S19 224.70 -9596.26 293 S117 911.26 -6818.00

94 RGB21 -1038.26 -900.00 194 S20 269.70 -9461.26 294 S118 1046.26 -6790.00

95 RGB20 -1038.26 -1010.00 195 S21 314.70 -9596.26 295 S119 911.26 -6762.00

96 RGB15 -1038.26 -1120.00 196 S22 359.70 -9461.26 296 S120 1046.26 -6734.00

97 RGB14 -1038.26 -1230.00 197 S23 404.70 -9596.26 297 S121 911.26 -6706.00

98 RGB13 -1038.26 -1340.00 198 S24 449.70 -9461.26 298 S122 1046.26 -6678.00

99 RGB12 -1038.26 -1450.00 199 S25 494.70 -9596.26 299 S123 911.26 -6650.00

100 RGB11 -1038.26 -1560.00 200 S26 539.70 -9461.26 300 S124 1046.26 -6622.00

★

Preliminary Product Information S16789EJ2V0PM 7

PD161606

Table 2–1. Pad Coordinate (2/3)

PIN No. PIN NAME X

301 S125 911.26 -6594.00 401 S225 911.26 -3794.00 501 S325 911.26 -994.00

302 S126 1046.26 -6566.00 402 S226 1046.26 -3766.00 502 S326 1046.26 -966.00

303 S127 911.26 -6538.00 403 S227 911.26 -3738.00 503 S327 911.26 -938.00

304 S128 1046.26 -6510.00 404 S228 1046.26 -3710.00 504 S328 1046.26 -910.00

305 S129 911.26 -6482.00 405 S229 911.26 -3682.00 505 S329 911.26 -882.00

306 S130 1046.26 -6454.00 406 S230 1046.26 -3654.00 506 S330 1046.26 -854.00

307 S131 911.26 -6426.00 407 S231 911.26 -3626.00 507 S331 911.26 -826.00

308 S132 1046.26 -6398.00 408 S232 1046.26 -3598.00 508 S332 1046.26 -798.00

309 S133 911.26 -6370.00 409 S233 911.26 -3570.00 509 S333 911.26 -770.00

310 S134 1046.26 -6342.00 410 S234 1046.26 -3542.00 510 S334 1046.26 -742.00

311 S135 911.26 -6314.00 411 S235 911.26 -3514.00 511 S335 911.26 -714.00

312 S136 1046.26 -6286.00 412 S236 1046.26 -3486.00 512 S336 1046.26 -686.00

313 S137 911.26 -6258.00 413 S237 911.26 -3458.00 513 S337 911.26 -658.00

314 S138 1046.26 -6230.00 414 S238 1046.26 -3430.00 514 S338 1046.26 -630.00

315 S139 911.26 -6202.00 415 S239 911.26 -3402.00 515 S339 911.26 -602.00

316 S140 1046.26 -6174.00 416 S240 1046.26 -3374.00 516 S340 1046.26 -574.00

317 S141 911.26 -6146.00 417 S241 911.26 -3346.00 517 S341 911.26 -546.00

318 S142 1046.26 -6118.00 418 S242 1046.26 -3318.00 518 S342 1046.26 -518.00

319 S143 911.26 -6090.00 419 S243 911.26 -3290.00 519 S343 911.26 -490.00

320 S144 1046.26 -6062.00 420 S244 1046.26 -3262.00 520 S344 1046.26 -462.00

321 S145 911.26 -6034.00 421 S245 911.26 -3234.00 521 S345 911.26 -434.00

322 S146 1046.26 -6006.00 422 S246 1046.26 -3206.00 522 S346 1046.26 -406.00

323 S147 911.26 -5978.00 423 S247 911.26 -3178.00 523 S347 911.26 -378.00

324 S148 1046.26 -5950.00 424 S248 1046.26 -3150.00 524 S348 1046.26 -350.00

325 S149 911.26 -5922.00 425 S249 911.26 -3122.00 525 S349 911.26 -322.00

326 S150 1046.26 -5894.00 426 S250 1046.26 -3094.00 526 S350 1046.26 -294.00

327 S151 911.26 -5866.00 427 S251 911.26 -3066.00 527 S351 911.26 -266.00

328 S152 1046.26 -5838.00 428 S252 1046.26 -3038.00 528 S352 1046.26 -238.00

329 S153 911.26 -5810.00 429 S253 911.26 -3010.00 529 S353 911.26 -210.00

330 S154 1046.26 -5782.00 430 S254 1046.26 -2982.00 530 S354 1046.26 -182.00

331 S155 911.26 -5754.00 431 S255 911.26 -2954.00 531 S355 911.26 -154.00

332 S156 1046.26 -5726.00 432 S256 1046.26 -2926.00 532 S356 1046.26 -126.00

333 S157 911.26 -5698.00 433 S257 911.26 -2898.00 533 S357 911.26 -98.00

334 S158 1046.26 -5670.00 434 S258 1046.26 -2870.00 534 S358 1046.26 -70.00

335 S159 911.26 -5642.00 435 S259 911.26 -2842.00 535 S359 911.26 -42.00

336 S160 1046.26 -5614.00 436 S260 1046.26 -2814.00 536 S360 1046.26 -14.00

337 S161 911.26 -5586.00 437 S261 911.26 -2786.00 537 S361 911.26 14.00

338 S162 1046.26 -5558.00 438 S262 1046.26 -2758.00 538 S362 1046.26 42.00

339 S163 911.26 -5530.00 439 S263 911.26 -2730.00 539 S363 911.26 70.00

340 S164 1046.26 -5502.00 440 S264 1046.26 -2702.00 540 S364 1046.26 98.00

341 S165 911.26 -5474.00 441 S265 911.26 -2674.00 541 S365 911.26 126.00

342 S166 1046.26 -5446.00 442 S266 1046.26 -2646.00 542 S366 1046.26 154.00

343 S167 911.26 -5418.00 443 S267 911.26 -2618.00 543 S367 911.26 182.00

344 S168 1046.26 -5390.00 444 S268 1046.26 -2590.00 544 S368 1046.26 210.00

345 S169 911.26 -5362.00 445 S269 911.26 -2562.00 545 S369 911.26 238.00

346 S170 1046.26 -5334.00 446 S270 1046.26 -2534.00 546 S370 1046.26 266.00

347 S171 911.26 -5306.00 447 S271 911.26 -2506.00 547 S371 911.26 294.00

348 S172 1046.26 -5278.00 448 S272 1046.26 -2478.00 548 S372 1046.26 322.00

349 S173 911.26 -5250.00 449 S273 911.26 -2450.00 549 S373 911.26 350.00

350 S174 1046.26 -5222.00 450 S274 1046.26 -2422.00 550 S374 1046.26 378.00

351 S175 911.26 -5194.00 451 S275 911.26 -2394.00 551 S375 911.26 406.00

352 S176 1046.26 -5166.00 452 S276 1046.26 -2366.00 552 S376 1046.26 434.00

353 S177 911.26 -5138.00 453 S277 911.26 -2338.00 553 S377 911.26 462.00

354 S178 1046.26 -5110.00 454 S278 1046.26 -2310.00 554 S378 1046.26 490.00

355 S179 911.26 -5082.00 455 S279 911.26 -2282.00 555 S379 911.26 518.00

356 S180 1046.26 -5054.00 456 S280 1046.26 -2254.00 556 S380 1046.26 546.00

357 S181 911.26 -5026.00 457 S281 911.26 -2226.00 557 S381 911.26 574.00

358 S182 1046.26 -4998.00 458 S282 1046.26 -2198.00 558 S382 1046.26 602.00

359 S183 911.26 -4970.00 459 S283 911.26 -2170.00 559 S383 911.26 630.00

360 S184 1046.26 -4942.00 460 S284 1046.26 -2142.00 560 S384 1046.26 658.00

361 S185 911.26 -4914.00 461 S285 911.26 -2114.00 561 S385 911.26 686.00

362 S186 1046.26 -4886.00 462 S286 1046.26 -2086.00 562 S386 1046.26 714.00

363 S187 911.26 -4858.00 463 S287 911.26 -2058.00 563 S387 911.26 742.00

364 S188 1046.26 -4830.00 464 S288 1046.26 -2030.00 564 S388 1046.26 770.00

365 S189 911.26 -4802.00 465 S289 911.26 -2002.00 565 S389 911.26 798.00

366 S190 1046.26 -4774.00 466 S290 1046.26 -1974.00 566 S390 1046.26 826.00

367 S191 911.26 -4746.00 467 S291 911.26 -1946.00 567 S391 911.26 854.00

368 S192 1046.26 -4718.00 468 S292 1046.26 -1918.00 568 S392 1046.26 882.00

369 S193 911.26 -4690.00 469 S293 911.26 -1890.00 569 S393 911.26 910.00

370 S194 1046.26 -4662.00 470 S294 1046.26 -1862.00 570 S394 1046.26 938.00

371 S195 911.26 -4634.00 471 S295 911.26 -1834.00 571 S395 911.26 966.00

372 S196 1046.26 -4606.00 472 S296 1046.26 -1806.00 572 S396 1046.26 994.00

373 S197 911.26 -4578.00 473 S297 911.26 -1778.00 573 S397 911.26 1022.00

374 S198 1046.26 -4550.00 474 S298 1046.26 -1750.00 574 S398 1046.26 1050.00

375 S199 911.26 -4522.00 475 S299 911.26 -1722.00 575 S399 911.26 1078.00

376 S200 1046.26 -4494.00 476 S300 1046.26 -1694.00 576 S400 1046.26 1106.00

377 S201 911.26 -4466.00 477 S301 911.26 -1666.00 577 S401 911.26 1134.00

378 S202 1046.26 -4438.00 478 S302 1046.26 -1638.00 578 S402 1046.26 1162.00

379 S203 911.26 -4410.00 479 S303 911.26 -1610.00 579 S403 911.26 1190.00

380 S204 1046.26 -4382.00 480 S304 1046.26 -1582.00 580 S404 1046.26 1218.00

381 S205 911.26 -4354.00 481 S305 911.26 -1554.00 581 S405 911.26 1246.00

382 S206 1046.26 -4326.00 482 S306 1046.26 -1526.00 582 S406 1046.26 1274.00

383 S207 911.26 -4298.00 483 S307 911.26 -1498.00 583 S407 911.26 1302.00

384 S208 1046.26 -4270.00 484 S308 1046.26 -1470.00 584 S408 1046.26 1330.00

385 S209 911.26 -4242.00 485 S309 911.26 -1442.00 585 S409 911.26 1358.00

386 S210 1046.26 -4214.00 486 S310 1046.26 -1414.00 586 S410 1046.26 1386.00

387 S211 911.26 -4186.00 487 S311 911.26 -1386.00 587 S411 911.26 1414.00

388 S212 1046.26 -4158.00 488 S312 1046.26 -1358.00 588 S412 1046.26 1442.00

389 S213 911.26 -4130.00 489 S313 911.26 -1330.00 589 S413 911.26 1470.00

390 S214 1046.26 -4102.00 490 S314 1046.26 -1302.00 590 S414 1046.26 1498.00

391 S215 911.26 -4074.00 491 S315 911.26 -1274.00 591 S415 911.26 1526.00

392 S216 1046.26 -4046.00 492 S316 1046.26 -1246.00 592 S416 1046.26 1554.00

393 S217 911.26 -4018.00 493 S317 911.26 -1218.00 593 S417 911.26 1582.00

394 S218 1046.26 -3990.00 494 S318 1046.26 -1190.00 594 S418 1046.26 1610.00

395 S219 911.26 -3962.00 495 S319 911.26 -1162.00 595 S419 911.26 1638.00

396 S220 1046.26 -3934.00 496 S320 1046.26 -1134.00 596 S420 1046.26 1666.00

397 S221 911.26 -3906.00 497 S321 911.26 -1106.00 597 S421 911.26 1694.00

398 S222 1046.26 -3878.00 498 S322 1046.26 -1078.00 598 S422 1046.26 1722.00

399 S223 911.26 -3850.00 499 S323 911.26 -1050.00 599 S423 911.26 1750.00

400 S224 1046.26 -3822.00 500 S324 1046.26 -1022.00 600 S424 1046.26 1778.00

★

Preliminary Product Information S16789EJ2V0PM

PD161606

Table 2–1. Pad Coordinate (3/3)

PIN No. PIN NAME X

601 S425 911.26 1806.00 701 S525 911.26 4606.00 801 S625 911.26 7406.00

602 S426 1046.26 1834.00 702 S526 1046.26 4634.00 802 S626 1046.26 7434.00

603 S427 911.26 1862.00 703 S527 911.26 4662.00 803 S627 911.26 7462.00

604 S428 1046.26 1890.00 704 S528 1046.26 4690.00 804 S628 1046.26 7490.00

605 S429 911.26 1918.00 705 S529 911.26 4718.00 805 S629 911.26 7518.00

606 S430 1046.26 1946.00 706 S530 1046.26 4746.00 806 S630 1046.26 7546.00

607 S431 911.26 1974.00 707 S531 911.26 4774.00 807 S631 911.26 7574.00

608 S432 1046.26 2002.00 708 S532 1046.26 4802.00 808 S632 1046.26 7602.00

609 S433 911.26 2030.00 709 S533 911.26 4830.00 809 S633 911.26 7630.00

610 S434 1046.26 2058.00 710 S534 1046.26 4858.00 810 S634 1046.26 7658.00

611 S435 911.26 2086.00 711 S535 911.26 4886.00 811 S635 911.26 7686.00

612 S436 1046.26 2114.00 712 S536 1046.26 4914.00 812 S636 1046.26 7714.00

613 S437 911.26 2142.00 713 S537 911.26 4942.00 813 S637 911.26 7742.00

614 S438 1046.26 2170.00 714 S538 1046.26 4970.00 814 S638 1046.26 7770.00

615 S439 911.26 2198.00 715 S539 911.26 4998.00 815 S639 911.26 7798.00

616 S440 1046.26 2226.00 716 S540 1046.26 5026.00 816 S640 1046.26 7826.00

617 S441 911.26 2254.00 717 S541 911.26 5054.00 817 S641 911.26 7854.00

618 S442 1046.26 2282.00 718 S542 1046.26 5082.00 818 S642 1046.26 7882.00

619 S443 911.26 2310.00 719 S543 911.26 5110.00 819 S643 911.26 7910.00

620 S444 1046.26 2338.00 720 S544 1046.26 5138.00 820 S644 1046.26 7938.00

621 S445 911.26 2366.00 721 S545 911.26 5166.00 821 S645 911.26 7966.00

622 S446 1046.26 2394.00 722 S546 1046.26 5194.00 822 S646 1046.26 7994.00

623 S447 911.26 2422.00 723 S547 911.26 5222.00 823 S647 911.26 8022.00

624 S448 1046.26 2450.00 724 S548 1046.26 5250.00 824 S648 1046.26 8050.00

625 S449 911.26 2478.00 725 S549 911.26 5278.00 825 S649 911.26 8078.00

626 S450 1046.26 2506.00 726 S550 1046.26 5306.00 826 S650 1046.26 8106.00

627 S451 911.26 2534.00 727 S551 911.26 5334.00 827 S651 911.26 8134.00

628 S452 1046.26 2562.00 728 S552 1046.26 5362.00 828 S652 1046.26 8162.00

629 S453 911.26 2590.00 729 S553 911.26 5390.00 829 S653 911.26 8190.00

630 S454 1046.26 2618.00 730 S554 1046.26 5418.00 830 S654 1046.26 8218.00

631 S455 911.26 2646.00 731 S555 911.26 5446.00 831 S655 911.26 8246.00

632 S456 1046.26 2674.00 732 S556 1046.26 5474.00 832 S656 1046.26 8274.00

633 S457 911.26 2702.00 733 S557 911.26 5502.00 833 S657 911.26 8302.00

634 S458 1046.26 2730.00 734 S558 1046.26 5530.00 834 S658 1046.26 8330.00

635 S459 911.26 2758.00 735 S559 911.26 5558.00 835 S659 911.26 8358.00

636 S460 1046.26 2786.00 736 S560 1046.26 5586.00 836 S660 1046.26 8386.00

637 S461 911.26 2814.00 737 S561 911.26 5614.00 837 S661 911.26 8414.00

638 S462 1046.26 2842.00 738 S562 1046.26 5642.00 838 S662 1046.26 8442.00

639 S463 911.26 2870.00 739 S563 911.26 5670.00 839 S663 911.26 8470.00

640 S464 1046.26 2898.00 740 S564 1046.26 5698.00 840 S664 1046.26 8498.00

641 S465 911.26 2926.00 741 S565 911.26 5726.00 841 S665 911.26 8526.00

642 S466 1046.26 2954.00 742 S566 1046.26 5754.00 842 S666 1046.26 8554.00

643 S467 911.26 2982.00 743 S567 911.26 5782.00 843 S667 911.26 8582.00

644 S468 1046.26 3010.00 744 S568 1046.26 5810.00 844 S668 1046.26 8610.00

645 S469 911.26 3038.00 745 S569 911.26 5838.00 845 S669 911.26 8638.00

646 S470 1046.26 3066.00 746 S570 1046.26 5866.00 846 S670 1046.26 8666.00

647 S471 911.26 3094.00 747 S571 911.26 5894.00 847 S671 911.26 8694.00

648 S472 1046.26 3122.00 748 S572 1046.26 5922.00 848 S672 1046.26 8722.00

649 S473 911.26 3150.00 749 S573 911.26 5950.00 849 S673 911.26 8750.00

650 S474 1046.26 3178.00 750 S574 1046.26 5978.00 850 S674 1046.26 8778.00

651 S475 911.26 3206.00 751 S575 911.26 6006.00 851 S675 911.26 8806.00

652 S476 1046.26 3234.00 752 S576 1046.26 6034.00 852 S676 1046.26 8834.00

653 S477 911.26 3262.00 753 S577 911.26 6062.00 853 S677 911.26 8862.00

654 S478 1046.26 3290.00 754 S578 1046.26 6090.00 854 S678 1046.26 8890.00

655 S479 911.26 3318.00 755 S579 911.26 6118.00 855 S679 911.26 8918.00

656 S480 1046.26 3346.00 756 S580 1046.26 6146.00 856 S680 1046.26 8946.00

657 S481 911.26 3374.00 757 S581 911.26 6174.00 857 S681 911.26 8974.00

658 S482 1046.26 3402.00 758 S582 1046.26 6202.00 858 S682 1046.26 9002.00

659 S483 911.26 3430.00 759 S583 911.26 6230.00 859 S683 911.26 9030.00

660 S484 1046.26 3458.00 760 S584 1046.26 6258.00 860 S684 1046.26 9058.00

661 S485 911.26 3486.00 761 S585 911.26 6286.00 861 S685 911.26 9086.00

662 S486 1046.26 3514.00 762 S586 1046.26 6314.00 862 S686 1046.26 9114.00

663 S487 911.26 3542.00 763 S587 911.26 6342.00 863 S687 911.26 9142.00

664 S488 1046.26 3570.00 764 S588 1046.26 6370.00 864 S688 1046.26 9170.00

665 S489 911.26 3598.00 765 S589 911.26 6398.00 865 S689 911.26 9198.00

666 S490 1046.26 3626.00 766 S590 1046.26 6426.00 866 S690 1046.26 9226.00

667 S491 911.26 3654.00 767 S591 911.26 6454.00 867 DUMM

911.26 9254.00

668 S492 1046.26 3682.00 768 S592 1046.26 6482.00 868 DUMM

1046.26 9282.00

669 S493 911.26 3710.00 769 S593 911.26 6510.00 869 DUMM

764.70 9596.26

670 S494 1046.26 3738.00 770 S594 1046.26 6538.00 870 S691 719.70 9461.26

671 S495 911.26 3766.00 771 S595 911.26 6566.00 871 S692 674.70 9596.26

672 S496 1046.26 3794.00 772 S596 1046.26 6594.00 872 S693 629.70 9461.26

673 S497 911.26 3822.00 773 S597 911.26 6622.00 873 S694 584.70 9596.26

674 S498 1046.26 3850.00 774 S598 1046.26 6650.00 874 S695 539.70 9461.26

675 S499 911.26 3878.00 775 S599 911.26 6678.00 875 S696 494.70 9596.26

676 S500 1046.26 3906.00 776 S600 1046.26 6706.00 876 S697 449.70 9461.26

677 S501 911.26 3934.00 777 S601 911.26 6734.00 877 S698 404.70 9596.26

678 S502 1046.26 3962.00 778 S602 1046.26 6762.00 878 S699 359.70 9461.26

679 S503 911.26 3990.00 779 S603 911.26 6790.00 879 S700 314.70 9596.26

680 S504 1046.26 4018.00 780 S604 1046.26 6818.00 880 S701 269.70 9461.26

681 S505 911.26 4046.00 781 S605 911.26 6846.00 881 S702 224.70 9596.26

682 S506 1046.26 4074.00 782 S606 1046.26 6874.00 882 S703 179.70 9461.26

683 S507 911.26 4102.00 783 S607 911.26 6902.00 883 S704 134.70 9596.26

684 S508 1046.26 4130.00 784 S608 1046.26 6930.00 884 S705 89.70 9461.26

685 S509 911.26 4158.00 785 S609 911.26 6958.00 885 S706 44.70 9596.26

686 S510 1046.26 4186.00 786 S610 1046.26 6986.00 886 S707 -0.30 9461.26

687 S511 911.26 4214.00 787 S611 911.26 7014.00 887 S708 -45.30 9596.26

688 S512 1046.26 4242.00 788 S612 1046.26 7042.00 888 S709 -90.30 9461.26

689 S513 911.26 4270.00 789 S613 911.26 7070.00 889 S710 -135.30 9596.26

690 S514 1046.26 4298.00 790 S614 1046.26 7098.00 890 S711 -180.30 9461.26

691 S515 911.26 4326.00 791 S615 911.26 7126.00 891 S712 -225.30 9596.26

692 S516 1046.26 4354.00 792 S616 1046.26 7154.00 892 S713 -270.30 9461.26

693 S517 911.26 4382.00 793 S617 911.26 7182.00 893 S714 -315.30 9596.26

694 S518 1046.26 4410.00 794 S618 1046.26 7210.00 894 S715 -360.30 9461.26

695 S519 911.26 4438.00 795 S619 911.26 7238.00 895 S716 -405.30 9596.26

696 S520 1046.26 4466.00 796 S620 1046.26 7266.00 896 S717 -450.30 9461.26

697 S521 911.26 4494.00 797 S621 911.26 7294.00 897 S718 -495.30 9596.26

698 S522 1046.26 4522.00 798 S622 1046.26 7322.00 898 S719 -540.30 9461.26

699 S523 911.26 4550.00 799 S623 911.26 7350.00 899 S720 -585.30 9596.26

700 S524 1046.26 4578.00 800 S624 1046.26 7378.00 900 DUMM

-630.30 9461.26

901 DUMM

-675.30 9596.26

★

Preliminary Product Information S16789EJ2V0PM 9

PD161606

3. PIN FUNCTIONS

3.1 Power Supply System Pins

Symbol Pin Name Pad No. I/O Function

VCC1 Logic power supply 144 to 147 − This is the power supply for the logic circuit.

When VSTBY = H, the power supply voltage input from this pin is

directly used as the power supply voltage of the internal logic circuit.

When VSTBY = L, the voltage output to the SF_VCC1 pin is used as

the logic power supply voltage, so connect this pin to the SF_VCC1

pin. For details, refer to Figure 3−1.

VCC2 CPU/RGB interface power

supply

156 to 159 − This is the power supply pin for the CPU/RGB interface.

VCC3 Gate interface power supply 16 to 19 − This is the power supply pin for the gate driver interface.

VS Driver power supply 24 to 27,

162 to 165

− This is the power supply pin for the driver circuit.

VSC

- power supply 38 to 41 − This is the power supply pin for the

- circuit.

VSS Ground 20 to 23,

28 to 33,

140 to 143,

152 to 155,

166 to 171

− This is the ground pin for the logic circuit, logic interface circuit,

source driver circuit, gate control circuit, and power supply control

circuit.

SF_VCC1 Internal logic power supply

generation amplifier output

148 to 151 Output When VSTBY = L, connect a capacitor between this pin and VSS. For

details, refer to Figure 3−1.

VSTBY Logic power supply generation

control

160 Input Select the existence of voltage supply of power supply for logic

circuits.

VSTBY = L: With no voltage supply necessity for VCC1

VSTBY = H: VCC1 needs to be voltage supplied

DVSS Mode setting 50, 54, 58, 62,

66, 73, 89,

136, 161

− Pull-down power supply pin for mode setting.

DVCC2 Mode setting 52, 56, 60, 64,

68, 135

− Pull-up power supply pin for mode setting.

Preliminary Product Information S16789EJ2V0PM

PD161606

Figure 3−1. Supplies of Power Supply

CPU/RGB

Interface circuit

CPU/RGB

Interface circuit

On-chip power supply

gate Dr interface circuit

On-chip power supply

gate Dr interface circuit

VCC2

VCC1

SF_VCC1

VSTBY

Regulator OFF

1.7 to 2.5 V

Open

1.7 to 2.35 V

IC internal logic circuit power supply

VCC3

2.5 to 3.3 V

VCC2

VCC1

SF_VCC1

VSTBY

Regulator ON

[When using IC regulator for logic circuit]

Usage conditions: VCC2 = 2.5 to 3.3 V, VCC3 = 1.7 to 3.3 V

[When not using IC regulator for logic circuit]

Usage conditions: VCC1 = 1.7 to 2.5 V, VCC2 = 1.7 to 3.3 V, VCC3 = 1.7 to 3.3 V, VCC1≤VCC2

VCC3

2.5 to 3.3 V

Preliminary Product Information S16789EJ2V0PM 11

PD161606

3.2 Logic System Pins (1/2)

Symbol Pin Name Pad No. I/O Function

This pin selects the bus width of the RGB interface.

BWS0,

BWS1

RGB interface bus width

selection

53,

Input

PSX CPU interface mode

selection

55 Input This pin selects the mode of the CPU interface.

L: Parallel interface

H: Serial interface

/CS Chip select 84 Input This pin is used for chip select signals. When /CS = active level, the chip is

active and can perform data I/O operations including command and data

I/O.

CSEG Chip select polarity

selection

61 Input This selects active level of chip select (/CS).

CSEG = L: Low level

CSEG = H: High level

/RESET Reset 111 Input When /RESET is L, an internal reset is performed. The reset operation is

executed at the /RESET signal level. Be sure to perform reset via this pin

at power application.

RSEL Reset switch 67 Input Switches the effective range for hard reset for the registers.

/RD

(E)

Read (Enable) 74 Input When i80 series parallel data transfer (/RD) has been selected, the signal

at this pin is used to enable read operations. Data is output to the data bus

only when this pin is low.

When M68 series parallel data transfer (E) has been selected, the signal at

this pin is used to enable read/write operations.

/WR

(R, /W)

Write

(Read/write)

75 Input When i80 series parallel data transfer (/WR) has been selected, the signal

at this pin is used to enable write operations.

When M68 series parallel data transfer (R,/W) has been selected, this pin

is used to determine the direction of data transfer.

L: Write

H: Read

C86 Select interface 59 Input This pin is used to switch between interface modes (i80 series CPU or M68

series CPU).

L: Selects i80 series CPU mode

H: Selects M68 series CPU mode

D0 to D7

Data bus 83 to 76 I/O These pins comprise 8-bit bi-directional data.

When the chip is not selected, D0 to D7 are in high impedance mode.

SI Serial input 87 Input This pin is data input of serial interface.

SO Serial output 86 Output This pin is data output of serial interface.

SCL Serial clock 88 Input This pin is clock input of serial interface.

Remark /xxx indicates active low signal.

Hard reset Command reset

L Don’t perform reset for

registers.

Perform reset for registers.

H Perform reset for registers. Perform reset for registers.

BWS1 BWS0 RGB interface bus width

L L 18 bits

L H 16 bits

H L 6 bits

H H Setting prohibited

Preliminary Product Information S16789EJ2V0PM

PD161606

(2/2)

Symbol Pin Name Pad No. I/O Function

SCLEG0 SCL data I/O edge

select

65 Input Selects the serial clock edge for data I/O via the serial interface.

For details, refer to Table 5−5.

SCLEG1 SCL polarity select 63 Input Selects the active level of the serial clock (SCL) for the serial interface.

SCLEG1 = L: Low level (high-level start)

SCLEG1 = H: High level (low-level start)

SSEL Serial interface mode

select

57 Input Selects the serial interface mode.

SSEL = L: Serial interface 1

SSEL = H: Serial interface 2

RS Data/command select 85 Input This pin is used in serial interface 1.

When parallel data transfer has been selected, this pin is usually

connected to the least significant bit of the standard CPU address bus

and is used to distinguish between data from display data and

commands.

RS = L: Indicates that data from D0 to D7 is commands.

RS = H: Indicates that data from D0 to D7 is display data.

HSYNC Horizontal sync signal 108 Input This is the horizontal sync signal of the RGB interface.

VSYNC Vertical sync signal 109 Input This is the vertical sync signal of the RGB interface.

DOTCLK Dot clock 110 Input This is the dot clock signal of the RGB interface.

RGB00 to RGB05,

RGB10 to RGB15,

RGB20 to RGB25

Data bus 107 to 102,

101 to 96,

95 to 90

Input These pins are RGB interface data signal.

OSC2SEL Oscillation signal select 137 Input This is the oscillation signal selection pin.

L: Selects CR internal oscillator.

H: Selects external resistor connected oscillator.

OSC2IN 138 Input

OSC2OUT

Oscillation signal

139 Output

These are the oscillation signal pins.

OSCEL = H: Connect a resistor between the OSCIN pin and

OSCOUT pin.

For the resistance values to be used as a guide, refer to the electrical

characteristics.

OSCEL = L: Leave OSCIN and OSCOUT open.

★

Preliminary Product Information S16789EJ2V0PM 13

PD161606

3.3 Driver Pins

Symbol Pin Name Pad No. I/O Function

S1 to S720 Source output 175 to 204,

207 to 866,

870 to 899

Output These pins are source output pins.

CVPH1, CVPH2,

CVPL1, CVPL2,

CVNH1, CVNH2,

CVNL1, CVNL2

Reference power

supply pin for

correction power

supply

44, 45,

48, 49,

42, 43,

46, 47

− Operational amplifier output pins for

-correction.

Normally a capacitor of 1

F or greater is connected to these pins.

Leave these pins open when not using amplifier for

- correction.

3.4 Pins for Gate Driver Control Internal Power Supply

Symbol Pin Name Pad No. I/O Function

GCLK Gate driver CLK output 3 Output This is the CLK output to the gate driver.

GSTB Gate driver STB output 2 Output Connect this pin to the STVR pin of the gate driver.

GOE1 Gate driver OE1 output 7 Output This is the OE1 output pin to the gate driver.

GOE2 Gate driver OE2 output 6 Output This is the OE2 output pin to the gate driver.

VCOUT Square wave signal output 4 Output Outputs the square wave signal for common modulation of VP-P

voltage 0 V to VCC3.

GCS Chip select for gate driver

interface

9 Output This is chip select for the gate driver serial interface.

GSCLK Serial clock for gate driver

interface

10 Output This is the serial clock for the gate driver serial interface.

GSO Serial data output for gate

driver interface

8 Output This is the serial data output for the gate driver serial interface.

GRESET Reset output for gate driver

interface

12 Output This is the reset output for the gate driver serial interface.

DCCLK Boost clock output 11 Output Outputs the DC/DC converter boost clock.

EQ Equalize control 5 Output Equalize control pin.

VCOM_EQ1 to

VCOM_EQ4

VCOM pin for equalize

control

34 to 37 Input Pin used for equalize control.

Preliminary Product Information S16789EJ2V0PM

PD161606

3.5 E2PROM Control Pins

Symbol Pin Name Pad No. I/O Function

ECS Chip select for

E2PROM interface

69 Output This is the chip select for the E2PROM interface.

E2PROM is made active by outputting ECS = H, following which data

transmission is performed.

Connect this pin to CS (chip select pin) of the E2PROM.

ESK Serial clock for

E2PROM interface

70 Output This is the CLK for the E2PROM interface.

Data is output from EDO to the E2PROM at the rising edge of ESK.

Connect this pin to CLK (shift clock pin) of the E2PROM

EDI Serial data input for

E2PROM interface

71 Input This is the data input for the E2PROM interface.

This pin is used for E2PROM data read.

Connect this pin to DOUT (data out pin) of the E2PROM

EDO Serial data output for

E2PROM interface

72 Output This is the data output for the E2PROM.

Data is output to E2PROM.

Connect this pin to DIN (data in pin) of the E2PROM.

3.6 Test or Other Pins

Symbol Pin Name Pad No. I/O Function

TOUT0 to TOUT17 Test output 132 to 115 Output This is output pin when IC is in test mode.

Normally, leave it open.

TIN0 to TIN2 Test input 114 to 112,

Input This is input pin when IC is in test mode.

Normally, leave it open or connected it to VSS.

TOSC1IN Test input 134 Input This is input pin when IC is in test mode.

Normally, leave it open or connected it to VSS.

TOSC1SEL Test input 133 Input This is input pin when IC is in test mode.

Normally, leave it open or connected it to VSS.

DUMMY Dummy 1, 13 to 15,

172 to 174,

205, 206,

867 to 869,

900, 901

− Dummy pin

Preliminary Product Information S16789EJ2V0PM 15

PD161606

4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS

The I/O circuit types of each pin and recommended connection of unused pins are described below.

(1/2)

Recommended Connection of Unused Pins

Pin Name Input Type I/O Power Supply

Parallel Interface Serial Interface

Note

BWS0, BWS1 Schmitt trigger Input VCC2 Mode setting pin O

PSX Schmitt trigger

Input VCC2 Mode setting pin O

/CS Schmitt trigger

Input VCC2 Connect this pin to VCC2 and VSS when CSEG = L and

CSEG = H, respectively.

−

CSEG Schmitt trigger

Input VCC2 Mode setting pin O

/RESET Schmitt trigger

Input VCC2 Always reset on power application −

RSEL Schmitt trigger

Input VCC2 Mode setting pin O

/RD (E) Schmitt trigger Input VCC2 − Connect to VCC2 or VSS −

/WR (R,/W) Schmitt trigger Input VCC2 − − −

D0 to D7 Schmitt trigger

I/O VCC2 − Leave open −

C86 Schmitt trigger Input VCC2 Mode setting pin Connect to VCC2 or VSS O

SI, SCL Schmitt trigger Input VCC2 Connect to VCC2 or VSS − −

SO − Output VCC2 Leave open −

SCLEG0, SCLEG1 Schmitt trigger Input VCC2 Connect to VCC2 or VSS Mode setting pin O

SSEL Schmitt trigger

Input VCC2 Connect to VCC2 or VSS Mode setting pin O

RS Schmitt trigger

Input VCC2 Register setting pin −

HSYNC Schmitt trigger

Input VCC2 Connect to VCC2 or VSS −

VSYNC Schmitt trigger

Input VCC2 Connect to VCC2 or VSS −

DOTCLK Schmitt trigger

Input VCC2 Connect to VCC2 or VSS −

RGB00 to RGB05,

RGB10 to RGB15,

RGB20 to RGB25

Schmitt trigger Input VCC2 Leave this pin open.

The unused pins are as follows.

·Unused pins in case of 6-bit interface: RGB10 to RGB15,

RGB20 to RGB25

·Unused pins in case of 16-bit interface: RGB00, RGB20

−

OSC2IN − Input VCC2 Leave open −

OSC2OUT − Output VCC2 Leave open −

OSC2SEL Schmitt trigger

Input VCC2 Connect to VSS −

Note O: Connect to VCC2 or VSS, depending on the mode selected.

Preliminary Product Information S16789EJ2V0PM

PD161606

(2/2)

Recommended Connection of Unused Pins

Pin Name Input Type I/O Power Supply

Parallel Interface Serial Interface

Note

GCLK − Output VCC3 Leave open −

GSTB − Output VCC3 Leave open −

GOE1 − Output VCC3 Leave open −

GOE2 − Output VCC3 Leave open −

VCOUT − Output VCC3 Leave open −

GCS − Output VCC3 Leave open −

GSCLK − Output VCC3 Leave open −

GSO − Output VCC3 Leave open −

GRESET − Output VCC3 Leave open −

DCCLK − Output VCC3 Leave open −

EQ − Output VCC3 Leave open −

VCOM_EQ − Input VS Leave open −

ECS − Output VCC2 Leave open −

ESK − Output VCC2 Leave open −

EDI Schmitt trigger Input VCC2 Leave open −

EDO − Output VCC2 Leave open −

S1 to S720 − Output VS Leave open −

VSTBY Schmitt trigger Input VCC2 Mode setting pin O

TOUT0 to TOUT17 − Output VCC2 Leave open −

TIN0 to TIN2 Schmitt trigger Input VCC2 Leave open or Connect to VSS −

TOSC1IN Schmitt trigger Input VCC2 Leave open or Connect to VSS −

TOSC1SEL Schmitt trigger Input VCC2 Leave open or Connect to VSS −

Note O: Connect to VCC2 or VSS, depending on the mode selected.

Preliminary Product Information S16789EJ2V0PM 17

PD161606

5. DESCRIPTION OF FUNCTIONS

5.1 Interface

5.1.1 Selection of interface type

The

PD161606 can transfer data using the RGB interface (18/16/6-bit), i80/M68 parallel interface (8-bit), or serial

interface (8-bit), or serial interface (8-bit). The modes listed in the following table can be selected by setting the PSX, BWS0,

BWS1, and SSEL pins. The i80/M68 parallel interface allows writing and reading to/from both data RAM and registers. The

serial interface allows writing to both display data RAM and registers, and reading of registers. The RGB interface allows

display data input.

Table 5–1.

PSX SSEL BWS0 BWS1 Mode /CS RS /RD

(E)

/WR

(R,/W) C86

SI,

SCLK SI RGB00 to RGB25

L L RGB

18-bit RGB00 to RGB25

H L RGB

16-bit

RGB00 to RGB25

(RGB00, RGB20 is

open)

L X

L H

8-bit

parallel

RGB

6-bit

/CS RS /RD

(E)

/WR

(R,/W) C86

X Note1 X Note1

RGB00 to RGB05

(RGB10 to RGB15,

RGB20 to RGB25 is

open)

L L RGB

18-bit RGB00 to RGB25

H L RGB

16-bit

RGB00 to RGB25

(RGB00, RGB20 is

open)

L H

8-bit

Serial1

RGB

6-bit

/CS RS

X Note1 R,/W X Note1 Hi-Z

Note2 SI,

SCL SI

RGB00 to RGB05

(RGB10 to RGB15,

RGB20 to RGB25 is

open)

L L RGB

18-bit RGB00 to RGB25

H L RGB

16-bit

RGB00 to RGB25

(RGB00, RGB20 is

open)

L H

8-bit

Serial2

RGB

6-bit

/CS X Note1 X Note1 X Note1 X Note1 Hi-Z

Note2 SI,

SCL SI

RGB00 to RGB05

(RGB10 to RGB15,

RGB20 to RGB25 is

open)

Other the above Setting prohibited

Notes1. Connect to VCC2 or VSS.

2. Hi-Z: High impedance. Leave open.

Preliminary Product Information S16789EJ2V0PM

PD161606

5.1.2 RGB interface

The

PD161606 inputs display data from the DOTCLK, HSYNC, VSYNC, RGB00 to RGB05, RGB10 to RGB15, and RGB20

to RGB25 pins. The horizontal interval back porch is set with R75, and the vertical interval back porch with R76.

6-bit, 16-bit, and 18-bit as the data bus width for the RGB interface.

Selection is performed with the BWS0 and BWS1 pins.

When the 6-bit bus width is selected, the back porch, HSYNC width, etc., must be controlled in units of 3 DOTCLK.

Table 5−2. Data Bus Width Selection

BWS1 BWS0 Data Bus Width

L L 18-bit

L H 16-bit

H L 6-bit

The operation sequence is as follows (when DCKEG = L, HSEG = L, VSEG = L).

Figure 5−1 shows the timing chart for when the 16-bit or 18-bit bus width is selected.

Start

↓

VSYNC = 0, HSYNC = 0 → 1: Vertical back porch count reset, line count reset

↓

VSYNC = 1, HSYNC = 0 → 1: Vertical back porch count +1

↓

The value of Vertical back porch counter is subtracted from the value (tVBP) set to the back porch of Vertical period.

tVBP − Vertical back porch count number = not 0

↓ = 0

HSYNC = 0, DOTCLK = 0 → 1: Horizontal back porch count reset

↓

HSYNC = 1, DOTCLK = 0 → 1: Horizontal back porch count+1

↓

The value of horizontal back porch counter is subtracted from the value (tHBP) set to the back porch of horizontal period.

tHBP − horizontal back porch count number = not 0

↓ = 0

It is taking in about the first data at the rising edge of the next DOTCLK.

↓

Data is taken in by 240 clocks (data is disregarded after 241 clocks).

↓

The data taken in by HSYNC = 1→0 is latched to the output stage.

↓

VSYNC = 0

≠ 0

Remark As for low active and DOTCLK, VSYNC and HSYNC latch data by the rising edge.

Preliminary Product Information S16789EJ2V0PM 19

PD161606

Figure 5–1. RGB Interface Timing Chart

(DCKEG = H, HSEG = H, VSEG = L)

VSYNC

HSYNC

RGB

to RGB

RGB

to RGB

RGB

to RGB

RGB

to RGB

RGB

to RGB

RGB

to RGB

RGB

to RGB

RGB

to RGB

RGB

to RGB

Invalid

Invalid Invalid

Invalid

1st line Last line

1 line period

1st pixel

2nd pixel Last pixel

Last pixel

= vertical back porch period

= horizontal back porch period

HSYNC

DCK

1 pixel period

VSS

VSH

1234

HSS

HSH

123

Preliminary Product Information S16789EJ2V0PM

PD161606

The relationships between the input data and the various source output pins for each bus width are as follows.

Figure 5−2. Relationship between Input Data and Source Output (16-/18-bit Bus Width)

[16-/18-bit bus width]

Source output S1 S2 S3 S4 S5 S6 S7 S8

Data bus RGB20 to

RGB25 Note2

RGB10 to

RGB15

RGB00 to

RGB05 Note1

RGB20 to

RGB25 Note2

RGB10 to

RGB15

RGB00 to

RGB05 Note1

RGB20 to

RGB25 Note2

RGB10 to

RGB15

Receiving

order

1st pixel 2nd pixel 3rd pixel

S715 S716 S717 S718 S718 S720

RGB20 to

RGB25 Note2

RGB10 to

RGB15

RGB00 to

RGB05 Note1

RGB20 to

RGB25 Note2

RGB10 to

RGB15

RGB00 to

RGB05 Note1

239th pixel 240th pixel

Source output S1 S2 S3 S4 S5 S6 S7 S8

Data bus RGB00 to

RGB05 Note1

RGB10 to

RGB15

RGB20 to

RGB25 Note2

RGB00 to

RGB05 Note1

RGB10 to

RGB15

RGB20 to

RGB25 Note2

RGB00 to

RGB05 Note1

RGB10 to

RGB15

Receiving

order

240th pixel 239th pixel 238th pixel

S715 S716 S717 S718 S718 S720

RGB00 to

RGB05 Note1

RGB10 to

RGB15

RGB20 to

RGB25 Note2

RGB00 to

RGB05 Note1

RGB10 to

RGB15

RGB20 to

RGB25 Note2

2nd pixel 1st pixel

Notes 1. When the 16-bit bus width is selected, RGB01 to RGB05 are used.

When the 16-bit width is selected, data input to RGB00 need not be performed, but amp output is performed for

data input to RGB05, because this is regarded as data input.

2. When the 16-bit bus width is selected, RGB21 to RGB25 are used.

When the 16-bit width is selected, data input to RGB20 need not be performed, but amp output is performed for

data input to RGB25, because this is regarded as data input.

Preliminary Product Information S16789EJ2V0PM 21

PD161606

Figure 5−3. Relationship between Input Data and Source Output (6-bit bus width)

[6-bit bus width]

Source output S1 S2 S3 S4 S5 S6 S7 S8

Data bus RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

Receiving

order

1st pixel 2nd pixel 3rd pixel

S715 S716 S717 S718 S718 S720

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

239th pixel 240th pixel

Source output S1 S2 S3 S4 S5 S6 S7 S8

Data bus RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

Receiving

order

240th pixel 239th pixel 238th pixel

S715 S716 S717 S718 S718 S720

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

RGB00 to

RGB05

2nd pixel 1st pixel

The

PD161606 contains on-chip partial RAM (3-bit/1-pixel). In addition to the data input form the RGB interface, the

partial RAM area specified by registers R15 to R22 can also be displayed, by setting the R0 register, OSD = 1.

Preliminary Product Information S16789EJ2V0PM

PD161606

[Example when using RGB Interface]

10 / 23 [TUE]

10:35

10 / 23 [TUE]

10:35

Partial display data RAM

R15: Partial RAM display area 1

start Y address

R16: Partial RAM display area 1

line count

R19: Partial RAM display area 2

start Y address

R20: Partial RAM display area 2

line count

RGB interface input data

Actually display screen

i80/M68 interface

It rewrites by serial interface

Display data RAM area

RGB interface

through display mode

access area

RGB interface

start line

(Setting by R60 register)

RGB interface

end line

(Setting by R61 register)

<1> Be sure to input data for each frame as the data input from the RGB interface.

<2> When switching to the partial mode, input at least 1 frame’s worth of data after issuing the mode switching command.

<3> When switching to the stand-by mode, input 1 frame’s worth of data in the case of stand-by mode1, and input 4

frame’s worth of data in the case of stand-by mode 2.

Mode transition flows

(1) Normal display mode

↓

To partial display mode

(display clock: internal

oscillation)

(2) Partial display mode

↓

Normal display mode

(display clock: DOTCLK)

(3) Normal display mode

↓

To stand-by mode

(4) Stand-by mode

↓

To normal display mode

(stand-by release)

DTY = 1 Data input start STBY = 1 Data input start

↓ ↓ ↓ ↓

Wait time 1

(partial display mode transition)

DTY = 0 Wait time 1 (STBSEL = 0)

Wait time 2 (STBSEL = 1)

(stand-by mode transition)

STBY = 0

↓ ↓ ↓ ↓

Data input stop

“Normal display mode”

“Normal display mode” Data input stop

“Stand-by mode”

“Normal display mode”

Wait time 1: Please secure sufficient time equal to 1 frame or more.

Wait time 2: Please secure sufficient time equal to 4 frames or more.

Preliminary Product Information S16789EJ2V0PM 23

PD161606

5.1.3 i80/M68 parallel interface

When the parallel interface has been selected, setting the C86 pin as either H or L enables a direct connection to an i80

series or M68 series CPU (Refer to following table).

Table 5–3.

C86 Mode /RD (E) /WR (R, /W) D7 to D0

H M68 series CPU E R, /W D7 to D0

L i80 series CPU /RD /WR D7 to D0

The data bus signal is identified according to the combination of the RS, /RD (E), and /WR (R, /W) signals.

Table 5–4.

Common M68 series CPU i80 series CPU

RS R, /W /RD /WR

Function

H H L H Read display data

H L H L Write display data

L H L H Read command

L L H L Write command

Preliminary Product Information S16789EJ2V0PM

PD161606

(1) i80 series parallel interface

When i80 series parallel data transfer has been selected, data is written to the

PD161606 at L period of the /WR signal.

The data is output to the data bus when the /RD signal is L.

Figure 5−4. i80 Series Interface Data Bus Status

/CS

(CSEG = L)

/WR

/RD

Data write Data read

Valid data

(2) M68 series parallel interface

When M68 series parallel data transfer has been selected, data is written at the H period of the E signal when the R,/W

signal is L. In a data read operation, data is output at the rising edge of the E signal in a period when the R,/W signal is H.

The data bus is released (Hi-Z) at the falling edge of the E signal.

Figure 5−5. M68 Series Interface Data Bus Status

/CS

(CSEG = L)

R,/W

Data write Data read

Valid data

Preliminary Product Information S16789EJ2V0PM 25

PD161606

5.1.4 Serial interface

The serial interface can be selected from serial interface mode 1 and serial interface mode 2 through serial mode

selection (SSEL). These mode are described in sections 5.1.4 (1) and 5.1.4 (2).

This serial interface supports SPI. The settings are described in section 5.1.4 (3).

(1) Serial interface mode 1

In serial interface mode 1, the data to be input can be specified either as “register number/register data” or “display data

(RAM data)” through input to the RS pin. The concrete details are as follows.

For the register number and register data input sequences, refer to Figure 5−9.

RS Pin Input Level Data Input from Serial Interface

Low-level Register number/register data

High-level Display data

(2) Serial interface mode 2

In serial interface mode 2, the 1st byte transfer sets the serial interface operation specification registers (A7 to A0) by the

1st byte transfer, and specifies whether the transfer data of 2nd byte is “register number”, “register data”, or “display data

(RAM data)”. During the 2nd byte transfer, the data specified with the 1st byte is transferred.

The serial interface operation specification registers are as follows.

Table5−5. Serial Interface Operation Specification Registers

Number Bit name Function

A7 − −

A6 Register/RAM data select This bit sets whether the D7 to D0 data is data for the

PD161606’s registers or for

its RAM.

0: D7 to D0 are data for the

PD161606’s registers.

1: D7 to D0 are data for the

PD161606’s RAM.

A5 Read/write select This bit selects whether the D7 to D0 data transfer is a read operation or a write

operation. However, a read operation is possible only for the

PD161606’s

registers.

For the read operation timing chart, refer to

0: D7 to D0 = Write operation

1: D7 to D0 = Read operation

A4 − −

A3 − −

A2 − −

A1 − −

A0 Command/data select This bit selects whether the D7 to D0 data is the data specifying the register

number of the command register, or the setting data for the command register.

0: D7 to D0 = register number

1: D7 to D0 = register setting value

Preliminary Product Information S16789EJ2V0PM

PD161606

Therefore, as shown in the following timing chart, in serial interface mode 2, after the chip select signal becomes active,

access to the serial interface operation specification register is always performed.

Figure 5−6. Serial Interface Mode 2 Timing Chart

A6A7

Serial interface operation specification transfer

Read or write selection

Command & data transfer

Display data (RAM data) transfer

A5 A4 A3 A2 A1 A0

/CS

SCL

D7 D6 D5 D4 D3 D2 D1 D0

Therefore, to perform write to a register, for example, 2-byte transfer is performed until a series of settings have been

completed. Also note that during 4-byte transfer performing access to a register, and during 2-byte transfer performing

display data (RAM) write, chip select must be kept active.

Figure 5−7. When Performing Register Setting in Serial Interface Mode 2

A7 A6 A5

Serial interface operation specification transfer

Specification of transfer of the register number value

at the next transfer

Command & data transfer

Serial interface operation specification transfer

Specification of transfer of the register data value

at the next transfer

Command & data transfer

A4 A3 A2 A1 A0

/CS

SCL

1st byte 2nd byte

3rd byte 4th byte

D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0

/CS

SCL

D7 D6 D5 D4 D3 D2 D1 D0

Preliminary Product Information S16789EJ2V0PM 27

PD161606

(3) SPI

When the serial interface is selected, serial data input (SI) and serial clock input (SCL) can be accepted if the chip is in

active status, but the relationship between the I/O data and the valid edges of the serial clock at this time, and the active

level of the serial clock can be set with the SCLEG0 and SCLEG1 pins.

Table 5−6. Relationship between Serial Clock and Data

Pin name

SCLEG1 SCLEG0

Active level of serial clock Serial data load timing Serial data output timing

L L Low-level Rising edge of serial clock Falling edge of serial clock

L H Low-level Falling edge of serial clock Rising edge of serial clock

H L High-level Falling edge of serial clock Rising edge of serial clock

H H High-level Rising edge of serial clock Falling edge of serial clock

An operation example when the active level of the serial clock is set to low level, data is output at the falling edge of the

serial clock, and data is input at the rising edge of the serial clock, is described below.

Serial data is read in the sequence of D7 first, then D6 to D0, in synchronization with the rising edge of the serial clock

from the serial input pin. This data is converted into parallel data and processed in synchronization with the rising edge of

the 8th serial clock.

Whether the serial input data is display data or a register setting is judged from the RS input in the case of serial interface

mode 1. If RS = H, the data is display data, and if RS = L, it is register number/register data. In the case of serial

interface mode 2, this is judged from the data of the A6 operation specification bit. If A6 = H, the data is display data, and

if A6 = L, it is register number/register data. Next, the serial interface signal chart is shown.

Figure 5−8. Serial Interface Signal Chart

"↑" in the above figure indications the data read timing.

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6

D7 D6 D5

D5 D4 D3 D1D2 D0

D4 D3 D2 D1 D0

/CS

SI (SCLEG0 = L)

SI (SCLEG0 = H)

SCL (SCLEG1 = H)

SCL (SCLEG1 = L)

Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings.

2. Display data RAM read is not possible.

3. When using SCL wiring, take care concerning the possible effects of terminating reflection and noise from

external sources. Our recommends checking operation with the actual device.

Preliminary Product Information S16789EJ2V0PM

PD161606

5.1.5 Chip select

The

PD161606 has a chip select pin (/CS). The CPU parallel interface and serial interface can be used only when /CS

= L. When the chip select pin is inactive, D0 to D17 are set to high impedance (invalid) and input of RS, /RD, or /WR is not

active.

Therefore, keep the chip select pin active for 1 cycle period of data transfer (until a read/write operation has been

completed once in the parallel interface mode).

It is not necessary to keep the chip select signal active when successively transferring data. It may be non-active

between data transfer operations.

However, note that it is necessary to continue making chip selection active during "a register specification + register

value setup" and transmission of "higher rank 8-bit+ low rank 8-bit of RAM" of 16-bit in the case of a serial interface.

5.1.6 Access to display data RAM and internal registers

Figures 5−9 to 5−13 show write accesses to the display data RAM and read/write accesses to internal registers 8-bit

parallel interface modes and serial interface mode.

When the CPU accessed the

PD161606, the CPU only has to satisfy the standard requirement of the cycle time (tCYC)

and can transfer data at high speeds. Usually, it is not necessary for the CPU to take WAIT time into consideration.

Preliminary Product Information S16789EJ2V0PM 29

PD161606

Figure 5−9. Read/Write in 8-Bit Parallel Interface Mode

<8-bit Parallel Interface>

<1> Write to Display data RAM

Display data RAM

Display data

RAM

Display data

RAM

Display data

RAM

Display data RAM Display data RAM

<3> Write to Register

Command Data

<4> Read of Register

<2> Read of Display data RAM

/CS

D7 to D5: Invalid data, D4: D4-bit of RAM, D3: D3-bit of RAM, D2: D2-bit of RAM, D1: D1-bit of RAM, D0: D0-bit of RAM

/WR

/CS

/RD

/CS

/WR

/RD

D7: IX7 to D0: IX0 D7: D7 of Register to D0: D0 of Register

/CS

/WR

/RD

D7-D0

Cautions 1. While setting the writing to a register, set it the fixed input of the low level to RS pin.

The register write interval is the “register number specification” + “register value setting” interval.

2. While setting the writing to display data RAM, set it the fixed input of the high level to RS pin.

The display data RAM write interval is the “1-pixel data transfer interval”

Preliminary Product Information S16789EJ2V0PM

PD161606

Figure 5−10. Read/Write in 8-bit Serial Interface

(Serial Interface Mode1)

/CS

<8-bit Serial interface mode1>

<1> Write to display data RAM

(SCLEG0 = L, SCLEG1 = L)

Display RAM data Display RAM data

(SCLEG0 = L, SCLEG1 = H)

(SCLEG0 = H, SCLEG1 = L)

(SCLEG0 = H, SCLEG1 = H)

R,/W

SCL

12345678 12345678

/CS

R,/W

SCL

12345678 12345678

/CS

R,/W

SCL

12345678 12345678

/CS

R,/W

SCL

12345678 12345678

SI D3 D2 D1 D0D7 D6 D5 D4D3 D2 D1 D0D7 D6 D5 D4

D3 D2 D1 D0D7 D6 D5 D4D3 D2 D1 D0D7 D6 D5 D4

Preliminary Product Information S16789EJ2V0PM 31

PD161606

Figure 5−11. Read/Write in 8-bit Serial Interface

(Serial Interface Mode1)

/CS

R,/W

SCL

12345678 910111213141516

/CS

R,/W

SCL

12345678 910111213141516

/CS

R,/W

SCL

12345678 910111213141516

/CS

R,/W

SCL

12345678 910111213141516

SI D3 D2 D1 D0D7 D6 D5 D4IX3 IX2 IX1 IX0IX7 IX6 IX5 IX4

D3 D2 D1 D0D7 D6 D5 D4IX3 IX2 IX1 IX0IX7 IX6 IX5 IX4

<2> Write to Register

(SCLEG0 = L, SCLEG1 = L)

(SCLEG0 = H, SCLEG1 = L)

Command Data

(SCLEG0 = L, SCLEG1 = H)

(SCLEG0 = H, SCLEG1 = H)

Preliminary Product Information S16789EJ2V0PM

PD161606

Figure 5−12. Read/Write in 8-bit Serial Interface

(Serial Interface Mode1)

/CS

R,/W

SCL

12345678 910111213141516

/CS

R,/W

SCL

12345678 910111213141516

/CS

R,/W

SCL

12345678 910111213141516

/CS

R,/W

SCL

12345678 910111213141516

D2 D1D4 D3

X D7 D6 D5

D2 D1D4 D3D6 D5

XD7

XD7 D6 D5 D4 D3 D2 D1

D2 D1

D7X

IX3 IX2 IX1 IX0IX7 IX6 IX5 IX4

D6 D5 D4 D3

IX3 IX2 IX1 IX0IX

IX6 IX5 IX4

<3> Read of Register

(SCLEG0 = L, SCLEG1 = L)

(SCLEG0 = H, SCLEG1 = L)

Command

Data

Command

Data

Command

Data

Command

Data

(SCLEG0 = L, SCLEG1 = H)

(SCLEG0 = H, SCLEG1 = H)

Cautions 1. During 16-bit transfer of the “register number specification + register value setting”, chip select must

be maintained active.

2. When performing register write, keep the output to the RS pin low level during the “register number

specification + register value setting” interval.

3. When performing display data RAM write, keep the output to the RS pin high level during the 1-pixel

data transfer interval.

Preliminary Product Information S16789EJ2V0PM 33

PD161606

Figure 5−13. Read/Write in 8-bit Serial Interface

(Serial Interface Mode2)

/CS

SCL

12345678 910111213141516

/CS

SCL

12345678 910111213141516

/CS

SCL

12345678 910111213141516

/CS

SCL

12345678 910111213141516

/CS

SCL

12345678 910111213141516

/CS

SCL

12345678 910111213141516

/CS

SCL

12345678 910111213141516

/CS

SCL

12345678 910111213141516

A7 A6

Serial interface operatoin specification transfer Command & data transfer

Serial interface operatoin specification transfer

Command & data transfer

A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0

D4 D3

A7 A6 A5 A4 A3 A2 A1 A0

SO D7XD6D5

D2 D1

D4 D3D6 D5SO X D7

SO X D7 D6 D5 D4 D3 D2 D1

<2> Read of Register

(SCLEG0 = L, SCLEG1 = L)

(SCLEG0 = H, SCLEG1 = L)

Data

(SCLEG0 = L, SCLEG1 = H)

(SCLEG0 = H, SCLEG1 = H)

<1> Write to Register

(SCLEG0 = L, SCLEG1 = L)

<8-bit Serial interface mode2>

(SCLEG0 = H, SCLEG1 = L)

(SCLEG0 = L, SCLEG1 = H)

(SCLEG0 = H, SCLEG1 = H)

Caution During 16-bit transfer of the “serial interface operation specification transfer + command & data

transfer”, chip select must be maintained active.

Preliminary Product Information S16789EJ2V0PM

PD161606

5.1.7

PD161645 control serial interface

This is the 16-bit serial interface for performing control for the

PD161645. The transfer operation is as follows.

This interface performs batch transfer of 16-bit data. The data format for the

PD161645 consists of the command in

the first byte of transfer data, and the data to be set in the second byte. Transfer is performed MSB first.

The transfer start trigger is data write to the control registers for the

PD161645. When data is written to control

registers, GCS, GS0, and GSCLK output automatically starts. Following input of the reset command, the

PD161645

checks the data of the odd bytes to be transferred against the command, and checks the data of the even bytes against

the data for the command.

Perform write to the shift register following the completion of transfer. Thus secure an interval of at least 250

s between

write operations to registers for the

PD161645. Transfer data when performing data write during transfer cannot be

guranteed.

Figure 5−14.

PD161645 Control Serial Interface Timing Chart

/CS

GSO

GSCLK

Command (first 8-bit data) Data set as a command

(2nd byte data)

345678910111213141516

IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 D7 D6 D5 D4 D3 D2 D1 D0

Preliminary Product Information S16789EJ2V0PM 35

PD161606

5.2 Partial Display RAM

The RAM holding the dots for display has a configuration of 115,200bits (240 X 5 bits) X 96 bits. Any pixel can be

accessed by specifying the X address and Y address.

Figure 5−15 shows the configuration of the display data RAM.

The partial display RAM has a 5-bit configuration, and bits D0 to D2 are the display data bits. Bits D3 and D4 are used

for the OSD function, and are enabled when this function is selected. Figure 5−16 shows the operation when the OSD

function is enabled.

Figure 5−15. Display RAM/Bit Configuration

RAM bit D4 D3 D2 D1 D0

Display data Function α1 α2

R data G data B data

Pixel 1 pixel

Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8

LCD panel

Figure 5−16. Transmittance when α Blending Function is Selected

OSD function α1 α2 Display RAM data transmittance

Invalid x x Transmittance 0% (base image 100%)

Valid 0 0 Transmittance 0% (base image 100%)

Valid 0 1 Transmittance 50% (base image 50%)

Valid 1 0 Transmittance 75% (base image 25%)

Valid 1 1 Transmittance 100% (base image 0%)

Remark x: Don’t care

5.2.1 X address circuit

An X address of the display data RAM is specified by using the X address register (R6) as shown in Figure 5−18.

The specified X address is incremented by one each time display data is written or read.

In the X address increment mode, the X address is incremented up to EFH. If more display data is written or read, the Y

address is incremented, and the X address returns to 00H.

The relationship between the X address and source output can be inverted by the ADX flag of control register 1 as shown

in Figure 5−18. After switched ADX, the input data can be rotated 90 degrees and displayed by changing the ADR function

and address increment direction between X and Y.

Preliminary Product Information S16789EJ2V0PM

PD161606

5.2.2 Y address circuit

The Y address of the display data RAM is specified by using the Y address register (R7) as shown in Figure 5−18.

The Y address is incremented each by one when one each time display is written or read and X address is incremented

to last address.

When the Y address has been incremented up to 5FH and the X address up to the final address, if further display data is

read or written, the X and Y addresses return to 00H.

As shown in Figure 5−18, the relationship between the Y address and gate output can be inverted by the ADR flag of the

control register. The data written to the display can be rotated 90 degrees and output by changing the ADX function and

address increment direction between X and Y.

Table 5−7. Data Access Control (R5) Settings

INC Setting

0 During data access, addresses are continuously incremented in the X direction.

1 During data access, addresses are continuously incremented in the Y direction.

Figure 5−17. Example of 90-degree Rotation

ADX = 0, ADR = 1

Y address increment (INC = 1)

ADX = 0, ADR = 0

X address increment (INC = 0)

Display image

Preliminary Product Information S16789EJ2V0PM 37

PD161606

Figure 5−18.

PD161606 RAM Addressing

1) ADX=0

ADC=0 S1 S2 S3 S4 S5 S6 --- --- S715 S716 S717 S718 S719 S720

ADC=1 S720 S719 S718 S717 S716 S715 --- --- S6 S5 S4 S3 S2 S1

X-address --- ---

Column address 000H 001H 002H 003H 004H 005H --- --- 2CAH 2CBH 2CCH 2CDH 2CEH 2CFH

D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0

ADY=0 ADY=1

00H 5FH

01H 5EH

56H 59H

57H 58H Display area

58H 57H

59H 56H

5EH 01H

5FH 00H

2) ADX=1

ADC=0 S1 S2 S3 S4 S5 S6 --- --- S715 S716 S717 S718 S719 S720

ADC=1 S720 S719 S718 S717 S716 S715 --- --- S6 S5 S4 S3 S2 S1

X-address --- ---

Column address 2CFH 2CEH 2CDH 2CCH 2CBH 2CAH --- --- 005H 004H 003H 002H 001H 000H

D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0

ADY=0 ADY=1

00H 5FH

01H 5EH

56H 59H

57H 58H Display area

58H 57H

59H 56H

5EH 01H

5FH 00H

EEH EFH

239th Pixel

001H

2nd Pixel 240th Pixel

Source output

000H

EFH

1st Pixel

Y-address

240th Pixel 239th Pixel 2nd Pixel

Y-address

000HEEH 001H

1st Pixel

Preliminary Product Information S16789EJ2V0PM

PD161606

5.2.3 Arbitrary address area access (window access mode (WAS))

With the

PD161606, any area of the display RAM selected by the MIN., X/Y address registers (R8 and R10) and MAX.,

X/Y address registers (R9 and R11) can be accessed.

First, select the area to be accessed by using the MIN.·X/Y address registers and MAX.·X/Y address registers. When

WAS of data access control register (R5) is set to 1, the window access mode is then selected. The address scanning

setting is also valid in this mode, in the same manner as when data is normally written to the display RAM. In addition,

data can be written from any address by specifying the X address register (R6) and Y address register (R7).

Figure 5−19. Example of Incrementing Address when in Window Access Mode

Start point

End point

5FH

00H

EFH

00H

MIN. X address

MIN. Y address

MAX. Y address

MAX. X address

Cautions 1. When using the window access mode, the relationship between the start point and end point

shown in the table below must be established.

Item Address Relationship

X address 00H ≤ MIN.·X address ≤ X address (R6) ≤ MAX.·X address ≤ EFH

Y address 00H ≤ MIN.·Y address ≤ Y address (R7) ≤ MAX.·Y address ≤ 5FH

2. If invalid address data is set as the MIN./MAX. address, operation is not guarateed.

Preliminary Product Information S16789EJ2V0PM 39

PD161606

Example of Sequence in Window Access Mode

The settings of the MIN. X address register (R8), MIN. Y address register (R10), MAX. X address register (R9), and MAX.

Y address register (R11) van be performed in any order.

Data access control register (R5)

MIN.

Data

Writing complete?

Sets start point.

Ye s

(WAS = 1)

Sets end point.

Sets window access mode.

.X address register (R8)

MIN. .Y address register (R10)

MAX. .X address register (R9)

MAX. .Y address register (R11)

X address register (R6)

Y address register (R7)

Write display data

Start

End

Preliminary Product Information S16789EJ2V0PM

PD161606

5.3 Oscillator

The

PD161606 allows selection of the on-chip oscillator (OSC2SEL = L: CR on-chip type) or an external oscillator

(OSC2SEL = H: R external) as the oscillator generating the display clock by setting the OSC2SEL pin.

Moreover, the on-chip oscillator contains two oscillation circuits. One of these oscillation circuits (OSC2) is used to

generate the liquid crystal display output timing, while the other oscillation circuit (OSC1) is used when executing frame

frequency calibration.

D4 bit of R1 (OSC1OFF) ← 0

D3 bit of R1 (OSC2OFF) ← 0

↓

Internal oscillation start

WAIT time: T.B.D.

s (Oscillation stabilization time wait)

D0 bit of R45 (OC) ← 1 Calibration start

↓ It is WAIT about the time for one line of frame frequency to set up.

D0 bit of R45 (OC) ← 0 Calibration stop

↓ WAIT time: T.B.D.

s(Calibration processing time)

D4 bit of R1 (OSC1OFF) ← 1 Oscillation circuit stop for calibrations

Since the oscillation circuit for calibrations comes to unnecessary after calibration execution, in order to lower power

consumption, suspend an oscillation ("1" is set to OSC1OFF of D4 bit of R1). In addition, when set calibration again once

performing a calibration, start oscillation operation again.

Moreover, the frame frequency by which the calibration was carried out is eliminated by command reset. Therefore, when

command reset is input, set a calibration again.

When selecting an external oscillator (OSCSEL = H), connect a T.B.D. Ω resistor to the OSCIN pin and the OSCOUT pin.

When the internal oscillator is selected, leave both pins unconnected.

Cautions 1. If DIVSL (R46), HCKSL (R46), LNSEL (R50) are changed from their initial values, calibration is

prohibited.

2. When an external oscillator is selected, calibration is prohibited.

Preliminary Product Information S16789EJ2V0PM 41

PD161606

5.4 Display Timing Generator

The display timing generator generates the timing signals for the internal timing of the source driver and for the gate

driver.

Horizontal interval

The timing of the following signals is controlled by register setting.

·GCLK

·GSTB

·GOE1

·EQ

·Amplifier drive period

In addition, a timing chart is shown next page.

Preliminary Product Information S16789EJ2V0PM

PD161606

Figure 5−20. Display Driving Signal Timing Chart (RGB interface: 16/18-bit batch transfer, line inversion)

16, 18-bit Mode display timing chart <line inversion, 720 output, VSYNC width = 1H, non-dummy line>

(1) HSYNC unit (Horizon period back porch (R75) = 3H)

*VSEG = L, HSEG = L, DCKEG = L

*Display CLK address value turns into a value which counted DOTCLK.

*When [ all ] it puts in 245 CLK or more in 1H period, it is added after display CLK address(Hcnt) value 244 address.

HSYNC tHSW (MIN. 1 DOTCLK)

tHS (MIN. 245 DOTCLK)

DOTCLK

tHBP (MIN. 3 DOTCLK)

RGB Data Invalid Invalid

Hcnt

GCLK

Polarity reversal is possible

GSTB-GCLK (MIN. 4 DOTCLK)

GSTB

GOE1

*At the time of a display = H. It changes with the time of standby, or 59DR1 (GOE2ON) commands.

GOE2

S1 to S720

VCOUT

Gn OUT

Gn+1 OUT

245 1

240230

-89012345-- #226 227 228 2 29 230 231 23 2 238 239 240233 234 235 236 237 241 242 243 244 01 423 56789

78946

67-

5123 222 227 228 2 29 230 231 23 2 233 234

#224 225 226 239 240235 236 237 23 8 123456789

Hi-Z

GOST[7:0] GOED[7:0]

EQST[7:0] EQED[7:0]

APST[7:0] APED[7:0]

Hi-Z

Equalize drive period Amplifier drive period

r-resistance direct drive period

GCED[7:0]

* The MIN. value of EQST, APST, and GOST is set to 1.

* The MIN. value of GCED is set to 2.

* When the position of a standup and falling is the same, an

output serves as L fixation.

Preliminary Product Information S16789EJ2V0PM 43

PD161606

Figure 5−21. Display Driving Signal Timing Chart (RGB interface: 6-bit batch transfer, line inversion)

6 bit Mode display timing chart <line inversion, 720 output, VSYNC width = 1H, non-dummy line>

* VSYNC and HSYNC operate for every 3 DOTCLK at the time of 6bit Mode.

(1) HSYNC unit (Horizon period back porch (R75) = 3H)

* VSEG = L, HSEG = L, DCKEG = L

Display CLK address value (Hcnt) turns into a value which counted DOTCLK.

HSYNC tHSW (MIN. 3 DOTCLK)

tHS (MIN. 735 DOTCLK)

DOTCLK

CLK

(Internal CLK)

RGB Data Invalid Invalid

Hcnt

GCLK

Polarity reversal is possible

GSTB

GOE1

*At the time of a display = H. It changes with the time of standby, or 59DR1 (GOE2ON) commands.

GOE2

S1 to S720

VCOUT

Gn OUT

Gn+1 OUT

11 12

D2 D3

910

D2 D3 D1 D2 D3 D1 D2 D3 D1

567

D1D1 D2 D3 D1 D2

D1 D2

123

D3D3

10 11

D3 D1 D2 D3D3 D1 D2

D1 D2 D3 D2D1 D2 D3 D1 D2 D3

013

D1 D2 D2 D3

D1D3D2 D3 D1 D2 D2

76244 0 1 2241 242 243 411 238 239 240

D2 D3

D1 D2 D3 D3 D1

D2 D3

23-- 1

237

D3 D1D1

4567

D2 D3 D1D1 D2

924067

D2 D3

236 238 239

D1 D2

845

735720 730

Hi-Z

GOST[5:0] GOED[5:0]

EQST[5:0] EQED[5:0]

APST[5:0] APED[5:0]

Hi-Z

Equalize drive period Amplifier drive period r-resistance direct drive period

GCED[5:0]

tHBP (MIN. 9 Dotclk)

Preliminary Product Information S16789EJ2V0PM

PD161606

Figure 5−22. Display Driving Signal Timing Chart (partial display, line inversion)

Display timing chart (Partial display)

(1) HCNT unit

*Display CLK address value (Hcnt) turns into a value which counted DOTCLK.

* Horizontal, perpendicular address: MIN. setup

CLK

Hcnt

GCLK

Polarity reversal is possible

GSTB

GOE1

*At the time of a display = H. It changes with the time of stand-by, or 59DR1 (GOE2ON) commands.

GOE2

S1 to S720

VCOUT

Gn OUT

Gn+1 OUT

1110 1211107645 89321029286789 2712345029 25 2612 22 23 2412

Hi-Z

PGOST[7:0] PGOED[7:0]

PEQST[7:0] PEQED[7:0]

PAPST[7:0] PAPED[7:0]

Hi-Z

Equalize drive period Amplifier drive period r-resistance direct drive period

PGCED[7:0]

* The MIN. value of EQST, APST, and GOST is set to 1.

* The MIN. value of GCED is set to 2.

* When the position of a standup and falling is the same, an output

serves as L fixation.

Preliminary Product Information S16789EJ2V0PM 45

PD161606

5.5

- Curve Correction Circuit

The

 PD161606 has an on-chip

- curve correction power supply circuit. If the internal

- curve correction matches the

LCD characteristics, no external parts are required. This circuit incorporates one

- curve correction resistor and adjusts

- Inclination and amplitude by switching between positive and negative polarity according to register settings.

Figure 5−23.

- Curve Correction Circuit



Amplitude adjustment

(fixed)

Amplitude adjustment

(fixed)

Amplitude adjustment

(fixed)

Amplitude adjustment

(fixed)

Amplitude adjustment

Inclination adjustment

Fine tunig adjustment 64 gray-scale

-register switch φφ

φφ

-register switch



Preliminary Product Information S16789EJ2V0PM

PD161606

5.5.1 Amplitude adjustment with internal amplifier

Amplitude adjustment can select two ways, the method of adjusting with internal amplifier, and the method of adjusting

by internal resistance. Each register of R101 (GPH [5:0]), R102 (GNH [5:0]), R103 (GPL [5:0]), and R104 (GNL [5:0])

performs adjustment with amplifier. Refer to Figure 5−24.

Figure 5−24. Amplitude Adjustment 1

(This figure is a circuit by the side of positive-polarity. Use GPH reading it as GNH, GPL to GNL, VPH to VNH, and

VPL to VNL if negative-polarity side's reading)

…

VD127

to VD64

VD63

to VD0 D/A

GPL [5:0]

GPH [5:0]

D/A

VPH

VPL

SS1

Figure 5−25. Relationship of TFT Drive Voltage (Normally White)

VPH

VNH

VPL

VNL

SS1

Positive polarity Negative polarity

White

Black

Drive Level Setting Register

VPH Positive polarity, black Contrast value setting register 1 R101

VNH Negative polarity, white Contrast value setting register 2 R102

VPL Negative polarity, white Contrast value setting register 3 R103

VNL Positive polarity, black Contrast value setting register 4 R104

Preliminary Product Information S16789EJ2V0PM 47

PD161606

The value of each amplifier output can be expressed as follows and the value of β can be set as shown in Table 5−8 and

5−9 by using the contrast value registers (R101, R102, R103, and R104)

VNL, VPL, VNH, VPH = (β ÷ 129) x VS

Caution The usable range in which each output level of VPH, VNH, VPL, and VNL can be set depends on the

curve.

Table 5−8.

- Contrast Value Setting and Electronic Volume Register β Setting 1 (VPH, VNL)

R101 VPH5 VPH4 VPH3 VPH2 VPH1 VPH0

R102 VNH5 VNH4 VNH3 VNH2 VNH1 VNH0

β value Setting or

Status Setting

00H 0 0 0 0 0 0 65

01H 0 0 0 0 0 1 66

02H 0 0 0 0 1 0 67

03H 0 0 0 0 1 1 68

3EH 1 1 1 1 1 0 127

3FH 1 1 1 1 1 1 128

Table 5−9.

- Contrast Value Setting and Electronic Volume Register β Setting 2 (VPL, VNL)

R103 VPL5 VPL4 VPL3 VPL2 VPL1 VPL0

R104 VNL5 VNL4 VNL3 VNL2 VNL1 VNL0

β value Setting or

Statement Setting

00H 0 0 0 0 0 0 1

01H 0 0 0 0 0 1 2

02H 0 0 0 0 1 0 3

03H 0 0 0 0 1 1 4

3EH 1 1 1 1 1 0 63

3FH 1 1 1 1 1 1 64

Preliminary Product Information S16789EJ2V0PM

PD161606

5.5.2 Amplitude adjustment by built-in resistance

The 4-bit data set as registers R105 and R109 sets amplitude adjustment by built-in resistance. Refer to Figure 5−26.

Figure 5−26. Amplitude Adjustment

Voltage

Scale Data

V0RP[3:0]

V63

VDR

VSR

SS1

(V0RP[3:0])

0000 5R

VDRP

10R

15R

20R

25R

30R

35R

40R

45R

50R

55R

60R

65R

70R

75R

80R

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

V0RN[3:0]

(V0RN[3:0])

0000 5R

VDNP

10R

15R

20R

25R

30R

35R

40R

45R

50R

55R

60R

65R

70R

75R

80R

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Preliminary Product Information S16789EJ2V0PM 49

PD161606

5.5.3 Inclination adjustment

Internal resistance also adjusts inclination adjustment. R106 and R110 register set adjustment. Refer to Figure 5−27.

Figure 5–27. Inclination Adjustment

V63

VGR4

V59

Voltage 

ScaleData

VLR

VGR5

VGR6

VHR 

VGR7

V61

V60

V62

VHRP[3:0]

(VLRP[3:0])

0000 2R

VHRP

10R

12R

14R

16R

18R

20R

22R

24R

26R

28R

30R

32R

10R

12R

14R

16R

18R

20R

22R

24R

26R

28R

30R

32R

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

V0R4P[2:0]

(V0R7P[2:0])

000 8R

VDR4(7)P

16R

24R

32R

40R

48R

56R

64R

001

010

011

100

101

110

111

V0R4N[2:0]

(V0R7N[2:0])

000 8R

VDR4(7)N

16R

24R

32R

40R

48R

56R

64R

001

010

011

100

101

110

111

V0R5P[2:0]

(V0R6P[2:0])

000 4R

VDR5(6)P

12R

16R

20R

24R

28R

32R

001

010

011

100

101

110

111

V0R5N[2:0]

(V0R6N[2:0])

000 4R

VDR5(6)N

12R

16R

20R

24R

28R

32R

001

010

011

100

101

110

111

VHRN[3:0]

(VLRN[3:0])

0000

VHRN

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Preliminary Product Information S16789EJ2V0PM

PD161606

5.5.4 Fine tuning adjustment

Internal resistance also sets fine tuning. Please adjust by R107, R108, R111, and R112 register. Refer to Figure 5−28.

Figure 5–28. Fine Tuning

V63

V20

V43

V55

VGR0

VGR1



VGR2

VGR3

R0:VGR0=R1:VGR1=R2:VGR2

=R3:VGR3=R:R'=1:1

Default

r00

r01

r04



Default:ON

VGRnP[2:0]

0 0 0 60R

VGR0P

56R

52R

48R

44R

40R

36R

32R

001

010

011

100

101

110

111

60R

VGR1P

56R

52R

48R

44R

40R

36R

32R

VGR2P

36R

40R

44R

48R

52R

56R

64R

32R

VGR3P

36R

40R

44R

48R

52R

56R

64R

VGRnN[2:0]

000 60R

VGR0N

56R

52R

48R

44R

40R

36R

32R

001

010

011

100

101

110

111

60R

VGR1N

56R

52R

48R

44R

40R

36R

32R

VGR2N

36R

40R

44R

48R

52R

56R

64R

32R

VGR3N

36R

40R

44R

48R

52R

56R

64R

Preliminary Product Information S16789EJ2V0PM 51

PD161606

5.6 Partial Display Function

The

PD161606 contains a partial display function. When this function is used, the display control clock becomes the

internal oscillation clock, and the display image shows only the data written to the partial display RAM. Moreover, the

partial non-display area displays the partial non-display area color set with the R23 register. Refer to Figure 5−29.

Table5−10 shows a comparison of the regular operation and the partial display operation.

Table 5−10. Comparison of Regular Operation and Partial Display Operation

Regular Operation Partial Display Operation

Display control clock DOTCLK, HDYNC, VSYNC Internal oscillation clock

Partial RAM display Displayed only when OSD function is enabled Always displayed.

OSD function Enabled. α1 bit and α2 bit settings are enabled. Disabled. Regardless of the α1 bit and α2 bit

settings, the data written to the partial RAM is

always enabled.

Display outside partial

RAM display

Input data displayed via RGB interface Partial non-display area color set with R23 is

displayed.

Figure 5−29. Partial Display

i80/M68 interface

It rewtite by the

serial interface

Data RAM display area

Partial non-display area

Color set by R23

R17, R18: Partial RAM display area 1

display start line

R21, R22: Partial RAM display area 2

display start line

10 / 23 [TUE] 10 : 35

Partial display data RAM

R15: Partial RAM display area 1

start Y address

R16: Partial RAM display area 1

line count

R19: Partial RAM display area 2

start Y address

R20: Partial RAM display area 2

line count

RGB interface input data

Actually display screen

10 / 23 [TUE] 10 : 35

"Invalid"

Preliminary Product Information S16789EJ2V0PM

PD161606

5.7 Stand-by

The

 PD161606 has a stand-by function that allows two types of operation as stand-by operation, either of which can be

selected.

5.7.1 Stand-by mode 1

Stand-by mode 1 is selected by setting STBSEL (R0, D2) = 0.

By setting control register 1 (R0): STBY = 1, white display is performed, and during the frame dummy line interval, all

gate outputs are set to ON and the panel charge is discharged. By setting the control register (R24): DCON = 0 after all

gate outputs have become ON, regulator OFF and DC/DC converter OFF are executed, and by setting R1: OSC2OFF = 1,

full stand-by mode is entered after the internal oscillator stops.

<Stand-by sequence>

STBY bit of R0= 1

↓

(WAIT in one frame period)

↓

DCON bit of R24= 0

↓

OSC2OFF bit of R1 = 1

The transition from the stand-by mode to the regular mode is the opposite sequence from the stand-by sequence, and is

executed in the order of OSC2OFF = 0, DCON = 1, and STBY = 0.

Figure 5–30. Outline of Operation during Stand-by Mode 1 Execution

Stand-by command exectuion (STBY = 1)

Sourse output → OFF level output start

(white level when VCOUT = L)

VCOUTn → VSS level output

Operation of stand-by command execution

GOE2 output → VSS level output

Source output → VSS level output

After an one-frame end

Remark In the stand-by mode (STBY = 1), display data RAM access, display data RAM hold, and register access are

possible even during DC/DC converter OFF and internal oscillation stop, as long as power is supplied to VCC1,

VCC2, and VCC3 (including when power is supplied to VCC1 from SF_VCC1).

Preliminary Product Information S16789EJ2V0PM 53

PD161606

5.7.2 Stand-by mode 2

Stand-by mode 2 is selected by setting STVSEL (R0, D2) = 1.

By setting control register 1 (R0): STBY = 1, white display starts. After white output has been performed until the next

frame after STBY = 1 has been set, GO21 = Low is executed for 2 frames. Then the source output becomes VSS level.

After the source output becomes VSS level, by setting control register (R24): DCON = 0, regulator OFF and DC/DC

converter OFF are executed, and by setting R1: OSC2OFF, the full stand-by mode is entered after the internal oscillator

stops.

<Stand-by sequence>

STBY bit of R0= 1

↓

(WAIT in four frame period)

↓

DCON bit of R24= 0

↓

OSC2OFF bit of R1 = 1

The transition from the stand-by mode to the regular mode is the opposite sequence from the stand-by sequence, and is

executed in the order of OSC2OFF = 0, DCON = 1, and STBY = 0.

The outline of the operation during stand-by mode 2 execution is shown on the next page.

Preliminary Product Information S16789EJ2V0PM

PD161606

Figure 5−31. Outline of Operation during Stand-by Mode 2 Execution

Stand-by command execution (STBY = 1)

Source output → OFF level output start

(White display)

VCOUTn → Inverted operation

White

output

1st frame

2nd frame

3rd and 4th frame

5th frame

GOE1 = Low output

Source output → V

level

VCOUT → V

level

Remark In the stand-by mode (STBY = 1), display data EAM access, display data RAM hold, and register access are

possible even during DC/DC converter OFF and internal oscillation stop, as long as power is supplied to VCC1,

VCC2, and VCC3 (including when power is supplied to VCC1 from SF_VCC1).

Preliminary Product Information S16789EJ2V0PM 55

PD161606

(1) Stand-by sequence

As power supply control, the example of a sequence at the time of performing an internal sequence is shown.

PD161606 stand-by set

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 stand-by mode set

(R0 Register)

X X X X 1 X X X

↓

The electric charge of the panel is discharge. It

will become white display if it is normally white

panel.

X: Set in accordance with the usage conditions.

1 frame time wait (in case stand-by mode 1)

(In stand-by mode 2, 4 frames time wait)

R24

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 1 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply OFF setting

(R24 Register)

0 X X X X X X 0

↓

The Power OFF completed !

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R24

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 internal oscillation OFF setting

(R1 Register)

X X X X 1 X X X

↓

Oscillation stop

(Stand-by status)

X: Set in accordance with the usage conditions.

Preliminary Product Information S16789EJ2V0PM

PD161606

(2) Stand-by release sequence

As power supply control, the example of a sequence at the time of performing an internal sequence is shown.

PD161606 stand-by mode release

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 internal oscillation ON setting

(R1 Register)

X X X X 0 X X X

↓

Oscillation start

X: Set in accordance with the usage conditions.

R24

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 1 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply ON setting

(R24 Register)

0 X X X X X X 1

↓

Power ON after time set to PUPT0/PUPT1 of R33

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 stand-by mode release

(R0 Register)

X X X X 0 X X X

↓

Complete return to regular mode!

X: Set in accordance with the usage conditions.

Preliminary Product Information S16789EJ2V0PM 57

PD161606

6. POWER SUPPLY INJECTION/INTERCEPTION

An example of powering injection/interception a chip set for TFT-LCD panel driving using the

PD161606 is shown

below.

6.1

PD161606 Power Supply Injection Setting Sequence Example

Hard reset

PD161606 register.

↓

Reset

PD161606 register

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 0 0 1 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 command reset

(R3 register)

0 0 0 0 0 0 0 1

↓

Start

PD161606 internal oscillation

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 internal oscillation ON setting

(R1 register)

X X X 0 0 X X X

↓

Oscillation start

X: Set in accordance with the usage conditions.

Reset

PD161645 register

R25

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 0 1 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 command reset

(R34 register)

X 1 X X X X X X

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

Set

PD161606

Rxx The setting order Rxx to Rxx are any order

to Rxx RS D15 D14 D13 D12 D11 D10 D9 D8

X X X X X X X X

D7 D6 D5 D4 D3 D2 D1 D0

PD161606

setting

(Perform this setting is required.)

X X X X X X X X

↓ X: Set in accordance with the usage conditions.

Set

PD161606 horizontal interval timing

Rxx The setting order Rxx to Rxx are any order

to Rxx RS D15 D14 D13 D12 D11 D10 D9 D8

X X X X X X X X

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 horizontal interval timing setting

X X X X X X X X

X: Set in accordance with the usage conditions.

Preliminary Product Information S16789EJ2V0PM

PD161606

Calibration

R45

D15 D14 D13 D12 D11 D10 D9 D8

0 0 1 0 1 1 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 power supply setting

(R45 register)

X X X X X X X X

↓ X: Set in accordance with the usage conditions.

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 calibration internal oscillation OFF

setting

(R1 register)

X X X 1 0 X X X

↓ X: Set in accordance with the usage conditions.

Power supply setting

R25

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 0 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R25 register)

0 0 X X X X 1 0

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R26

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 0 1 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R26 register)

0 0 0 0 0 1 0 1

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R27

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 0 1 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R27 register)

0 X X X X X X 1

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R28

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 1 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R28 register)

0 X X X X X X X

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

Preliminary Product Information S16789EJ2V0PM 59

PD161606

R29

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 1 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R29 register)

0 0 0 X X X X X

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R30

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 1 1 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R30 register)

0 0 0 X X X 0 0

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R31

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 1 1 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R31 register)

X X X X X X X X

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R32

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 1 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R32 register)

0 0 0 X X X X X

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R33

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 1 0 0 0 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R33 register)

0 0 1 0 1 1 1 1

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

R24

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 1 1 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply setting

(R24 register)

0 X X X X X X 1

↓

Power ON after time set to PUPT0/PUPT1 of R33

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

Preliminary Product Information S16789EJ2V0PM

PD161606

Display data input start

Data input start by the RGB interface

↓

Display start setting

R59

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 1 1 1 0 1 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 GOE1, GOE2 signal setting

(R59 register)

0 0 0 0 0 0 0 1

↓

After 1-frame time, all whites or all blacks are displayed.

RS D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 display setting

(R0 register)

0 0 X 0 0 0 0 0

↓

RAM data display start

X: Set in accordance with the usage conditions.

Regular RAM data display through DISP1, DISP0 cancellation

Preliminary Product Information S16789EJ2V0PM 61

PD161606

6.2

PD161606 Power Supply Interception Setting Sequence Example

PD161606 to the stand-by mode

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 stand-by mode setting

(R0 register)

X X X X 1 X X X

↓

Discharge of the electric charge of panel is carried

out. It will become white display if it is normally

white panel.

X: Set in accordance with the usage conditions.

1 frame time wait

(In stand-by mode 2, 4 frames times wait)

R24

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 1 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

PD161645 power supply OFF setting

(R24 register)

0 X X X X X X 0

↓

X: Set in accordance with the usage conditions.

T.B.D.

s MIN. wait

RS D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 1

D7 D6 D5 D4 D3 D2 D1 D0

PD161606 power supply OFF setting

(R1 register)

X X X X 1 X X X

↓

Oscillation stop

(Stand-by status)

X: Set in accordance with the usage conditions.

Preliminary Product Information S16789EJ2V0PM

PD161606

7. E2PROM INTERFACE

The

PD161606 builds in the interface function to E2PROM corresponding to the micro-wire interface.

However, the capacity of E2PROM corresponds 4k-bit article.

7.1 The

PD161606 and E2PROM Connection

Connection with E2PROM is made as shown in the following figure.

ECS

ESK

LCD

Controller/

Driver IC

Microwire

PROM

EDO

EDI

CLK

DIN

DOUT

LCD controller side signal

Pin Function

ECS Chip select signal over E2PROM.

With outputting ECS = 1, E2PROM is made into an active state and data is transmitted after that.

It connects with CS (chip select pin) of E2PROM.

ESK Clock signal over E2PROM.

In falling of ESK, data is outputted from EDO to E2PROM.

It connects with CLK (shift clock pin) of E2PROM.

EDO Data output pin.

Data is outputted to E2PROM.

It connects with DIN (data in pin) of E2PROM

EDI Data input pin.

It is used for reading of the data of E2PROM.

It connects with DOUT (data out pin) of E2PROM.

Preliminary Product Information S16789EJ2V0PM 63

PD161606

7.2 Each Operation

The

PD161606 can perform writing of register data, reading of a register date and elimination of E2PROM data to

E2PROM. Selection of each operation is performed using R118 register.

R118 Register

E2OPC2 E2OPC1 E2OPC0 E2PROM Command

0 0 0 Setting prohibited

0 0 1 EPSAVE: Writing to E2PROM

0 1 0 MASKON: Permission of the writing and elimination to E2PROM

0 1 1 MASKOF: Prohibition of the writing and elimination to E2PROM

1 0 0 EPCLR: All area elimination of E2PROM

1 0 1 EPWALL: FFH is written in all the area of E2PROM

1 1 0 EPREAD: Reading from E2PROM

1 1 1 Setting prohibited

In addition, explain each operation below.

[E2PROM read command: Reading from E2PROM]

From the "E2PROM address" set as "the E2PROM reading start address register (R124)", it reads in order of "index" + "a

PD161606. In addition, reading operation is continuously performed until it reads the reading end ID (FFFFH or 7FFFH).

When FFFFH or 7FFFH are not read, reading operation is stopped if reading exceeds 128 times.

Command input R124: Setting of reading start address

R118: E2PROM read execution (06H)

↓

E2PROM read

↓

Writing to IR register

↓

reads FFFF

Completion

↓

Completion of processing

★

Preliminary Product Information S16789EJ2V0PM

PD161606

[EPSAVE command: Writing of the data to E2PROM]

The register data of the

PD161606, data is written in the E2PROM address based on R119 (E2PROM address) and

R120 (IR data).

Elimination/writing permission and

command input

R118: Elimination/writing permission carry out (MASKON command = 02H)

↓

EWEN issue To elimination/writing permission state

↓

E2PROM writing address specification It writes in R119 and is specification of address.

↓ Remark Since increment is not carried out, it is required.

Writing index specification of E2PROM The index which wants to write in R120 is set up.

↓ (As for the data of an index, the register value in

PD161606 is written in.)

The data transmission command input

to E2PROM

R118: Data transmission execution to E2PROM (EPSAVE command = 01H)

↓

Wait It is wait time in order to write in ROM. It is needed.

Insert wait time after confirming the specification of E2PROM used.

Completion

↓

Elimination/writing protected and

command input

R118: Elimination/writing protected execution (03H)

↓

EWDS It passes elimination/writing protected.

↓

About the data of E2PROM, they are elimination or the disposal for making it not

rewrite carelessly.

Completion of processing

Preliminary Product Information S16789EJ2V0PM 65

PD161606

[MASKON command: Writing/elimination permission to E2PROM]

Elimination/writing to E2PROM are permitted.

Command input R118 = 02H

↓

EWEN <Erase write enable> To an elimination/writing permission state

↓

Completion of processing

[MASKOF: Writing protected to E2PROM]

Elimination/writing to E2PROM are protected (Reading of data is possible).

Command input R118 = 03H

↓

EWDS <Erase write disable> It passes elimination/writing protected.

↓

Completion of processing

Preliminary Product Information S16789EJ2V0PM

PD161606

[EPCLR command: E2PROM elimination] :

The data of E2PROM is initialized.

Elimination/writing permission and

command input

R118 = 02H

↓

EWEN To elimination/writing permission state

↓

ERAL <Erase All> All data elimination of E2PROM

↓

E2PROM elimination and command

input

R118 = 04H

↓

Wait

↓

After a command input (CS = L → H) in order to access ROM, ERAL is

needed wait time like a data write.

Insert wait time after confirming the specification of E2PROM used.

Completion of processing

↓

Elimination/write-protected and

command input

R118 = 03H

↓

EWDS It passes elimination/write-protected.

↓

Completion of processing

Preliminary Product Information S16789EJ2V0PM 67

PD161606

[EPWALL] :

"Index = 7FH"+ "Data = FFH" is written in all the data of E2PROM.

At the time of E2PROM initialization, it reads to all E2PROM data, an end command (R127) is written and the infinite loop

of reading by the noise etc. is prevented.

Elimination/writing permission and

command input

R118 = 02H

↓

EWEN To elimination/writing permission state

↓

EPWALL command input R118 = 05H

↓

WRAL <Erase All> “Index = 7FH (R127) “+ “Data = FFH“ is written in to all the data of E2PROM.

↓

Wait

After a command input (CS = L → H) in order to access ROM, WRAL is

needed wait time like a data write.

Insert wait time after confirming the specification of E2PROM used.

↓

Elimination/write-protected and

command input

R118 = 03H

↓

EWDS It passes elimination/write-protected.

↓

Completion of processing

Preliminary Product Information S16789EJ2V0PM

PD161606

8. RESET

If the /RESET input becomes L or the reset command is input, the internal timing generator is initialized. The reset

command will also initialize each register to its default value. These default values are listed in the table below. When the

RSEL pin is set to High-level, initialization is performed up to the reset command range by setting /RESET input to Low-

level.

(1/3)

Control register 1 R0 X O 80H

Control register 2 R1 X O 18H

RGB interface register R2 X O 00H

Command reset register R3 X O 00H

Output amplitude power supply setup register for 8-color

display register

R4 X O 0FH

Data access control register R5 X O 00H

X address register R6 X O 00H

Y address register R7 X O 00H

MIN. ⋅X address register R8 X O 00H

MAX. ⋅X address register R9 X O EFH

MIN. ⋅Y address register R10 X O 00H

MAX. ⋅Y address register R11 X O 5FH

Partial RAM display area 1 start Y address register R15 X O 00H

Partial RAM display area 1 line count register R16 X O 00H

Partial RAM data display area 1 start line register R17 X O 00H

Partial RAM data display area 1 start line register R18 X O 01H

Partial RAM display area 2 start Y address register R19 X O 00H

Partial RAM display area 2 line count register R20 X O 00H

Partial RAM data display area 2 start line register R21 X O 00H

Partial RAM data display area 2 start line register R22 X O 01H

Partial OFF area color register R23 X O 07H

Power supply control register 1 R24 X O 00H

Power supply control register 2 R25 X O 00H

Power supply control register 3 R26 X O 00H

Power supply control register 4 R27 X O 00H

Power supply control register 5 R28 X O 00H

Gate scan setting register R29 X O 00H

Common setting register R30 X O 00H

Common amplitude setting register R31 X O 00H

Common center voltage setting register R32 X O 00H

Power supply rising select register R33 X O 00H

Power supply command reset register 5 R34 X O 00H

Remark O: Default value set, X: Default value not set

Note In the case of reset via the /RESET pin, only internal counters are initialized. At power application, be sure to

perform reset via the /RESET pin.

Preliminary Product Information S16789EJ2V0PM 69

PD161606

(2/3)

Calibration register R45 X O 00H

Partial display/horizontal interval clock setting register R46 X O 00H

Gate scan line count select register R50 X O 2BH

Line count specify during line inversion register R51 X O 00H

Partial display OFF area gate scan cycle set register R52 X O 00H

GOE1 output control register R59 X O 01H

DCCLK frequency set register R65 X O 00H

Horizontal back porch set register R75 X O 03H

Vertical back porch set register R76 X O 01H

Dummy line control select register R77 X O 00H

GCLK, GSTB polarity select register R78 X O 00H

GCLK inversion timing set register R79 X O 10H

Equalize interval start position set register R80 X O 01H

Equalize interval end position set register R81 X O 15H

Amplifier drive start position set register R82 X O 18H

Amplifier drive end position set register R83 X O B8H

GOE1 start position set register R86 X O 18H

GOE1 end position set register R87 X O E8H

Partial mode GCLK inversion timing set register R88 X O 03H

Partial mode equalize interval start position set register R89 X O 01H

Partial mode equalize interval end position set register R90 X O 03H

Partial mode amplifier drive start position set register R91 X O 04H

Partial mode amplifier drive end position set register R92 X O 15H

Partial mode GOE1 start position set register R93 X O 05H

Partial mode GOE1 end

osition set re

iste

R94 X O 1BH

Bias adjustment register 1 R95 X O 12H

Bias adjustment register 2 R96 X O 22H

- adjustment register R100 X O 0FH

- adjustment register R101 X O 35H

- adjustment register R102 X O 30H

- adjustment register R103 X O 16H

- adjustment register R104 X O 1CH

- adjustment register R105 X O 37H

Remark O: Default value set, X: Default value not set

Note In the case of reset via the /RESET pin, only internal counters are initialized. At power application, be sure to

perform reset via the /RESET pin.

Preliminary Product Information S16789EJ2V0PM

PD161606

(3/3)

- adjustment register R106 X O 67H

- adjustment register R107 X O 70H

- adjustment register R108 X O 07H

- adjustment register R109 X O 00H

- adjustment register R110 X O 00H

- adjustment register R111 X O 95H

- adjustment register R112 X O 33H

- adjustment register R113 X O 70H

- adjustment register R114 X O 07H

- adjustment register R115 X O 00H

- adjustment register R116 X O 00H

NW/NB polarity select register R117 X O 00H

E2PROM OPC setting R118 X O 00H

E2PROM writing address specification R119 X O 00H

E2PROM writing register address specification R120 X O 00H

E2PROM products information register R121 X O 00H

E2PROM products information register R122 X O 00H

E2PROM products information register R123 X O 00H

E2PROM reading address specification R124 X O 00H

E2PROM OSC divide register R125 X O 01H

PD161645 OSC divide register R126 X O 00H

E2PROM read stop register R127 X O FFH

Remark O: Default value set, X: Default value not set

Note In the case of reset via the /RESET pin, only internal counters are initialized. At power application, be sure to

perform reset via the /RESET pin.

Cautions 1. Whether reset is performed via the /RESET pin or the reset command, the contents of the display

RAM are held.

However, the RAM contents are undefined immediately following power application.

2. Calibration setting time tcal is set to the following value using the reset command.

tcal = 1/fOSC x 30

Preliminary Product Information S16789EJ2V0PM 71

PD161606

9. COMMAND

9.1 Command List

(1/9)

D7 DISP1 This command performs the same output as when all data is 1, independently of the internal RAM

data (white display in the case of normally white).

This command is executed, after it has been transferred, when the next line is output.

0: Normal operation

1: Ignores data of RAM and outputs all data as 1.

DISP1 takes precedence over DISP0. When DISP1 = H, DISP0 = H is ignored.

D6 DISP0 This command performs the same output as when all data is 0, independently of the internal RAM

data (black display in the case of normally white).

This command is executed, after it has been transferred, when the next line is output.

0: Normal operation

1: Ignores data of RAM and outputs all data as 0.

D5 INV This command selects a line reversal function and a frame reversal function.

Execution in the mode set by this command is from the timing which gate scan at the time of

command execution ends to 360 lines, and the following scan starts.

0: Line inversion

1: frame inversion

D4 DTY Selects the partial function. Execution of the mode selected with this command starts after gate scan

during command execution completes 360 lines and the next scan starts.

0: Normal display mode

1: Partial display mode

D3 STBY This bit selects the stand-by function. When the stand-by function is selected, a display OFF

operation is executed, the amplifiers, and oscillator at each output stage are stopped.

After executing the stand-by function using this bit, set the regulator for gate power supply Block to

OFF and set the DC/DC converter to OFF. For the sequence, refer to the preliminary product

information machine.

Note that when releasing stand-by, perform the opposite operation, i.e., after setting the DC/DC

converter to ON and setting the regulators to ON, set to 0 on this bit and execute the normal

operation command.

0: Normal operation

1: Stand-by function

D2 STBSEL Stand-by mode is chosen from two kinds of operation (Stand-by mode 1, Stand-by mode 2).

Refer to 5.7 Stand-by for details of operation.

0: Stand-by mode 1

1: Stand-by mode 2

D1 OSD Selects the OSD function. Execution of the mode selected with this command starts after gate scan

during command execution completes 360 lines and the next scan starts.

This command becomes invalid at the time of partial display mode.

0: Normal display mode

1: OSD display mode

D0 GSM Sets output of the gate scanning signal during partial display.

If this bit is set to 1, the gate scan of the lines set in the partial non-display area is it carries out for

every frame cycle set up by R52 register.

0: Normal mode

1: Gate scanning in partial non-display area is determined with the setting value to the setting value

of R52

Preliminary Product Information S16789EJ2V0PM

PD161606

(2/9)

D7 ADX Addressing of X address is inverted. For more details, refer to Figure 5−18.

D6 ADY Addressing of Y address is inverted. For more details, refer to Figure 5−18.

D5 ADC The direction of a column address.

The direction of a sauce driver output can be select. For more details, refer to Figure 5−16.

D4 OSC1OFF This is oscillator circuit stop bit for calibration. This command is stop when in stand-by mode.

0: Oscillator operation

1: Oscillator stop

D3 OSC2OFF This is oscillator circuit stop bit for LCD display. Regardless of setup of this bit, oscillation for LCD

display is stop at the time of stand-by.

0: Oscillator operation

1: Oscillator stop

D2 COLOR Switches the 260K color mode and 8 colors mode. Execution of the mode selected with this

command starts after gate scan during command execution completes 360 lines and the next scan

starts.

0: 262,144 colors

1: 8 colors

D1 LTS Selects set time of calibration.

The calibration function adjusts the frame frequency by setting time of one line. This command can

select the set time of aline form the following.

0: 1-line time = tcal

1: 1-line time = tcal x 2

(tcal: Calibration set time = 1 ÷ Frame frequency ÷ Number of displayed lines)

D0 BGR In addition to changing the sequence of RGB data during RAM write, switches the relationship

between the data input from RGB interface and the RGB data of the source output. (The R and B

data are switched.)

0: Normal operation

1: Switch R and B data and perform write.

D6 DCKEG Selects the DOTCLK active level.

0: High active

1: Low active

D5 VSEG Selects the VSYNC active level.

0: High active

1: Low active

D4 HSEG Selects the HSYNC active level.

0: High active

1: Low active

Source output

(n = 1, 4, 7, ….)

Sn Sn+1 Sn+2

Data bus RGB05 to RGB00 RGB15 to RGB10 RGB25 to RGB20

RAM D2 D1 D0

Source output

(n = 1, 4, 7, ….)

Sn Sn+1 Sn+2

Data bus RGB25 to RGB20 RGB15 to RGB10 RGB05 to RGB00

RAM D2 D1 D0

Preliminary Product Information S16789EJ2V0PM 73

PD161606

(3/9)

R3 D0 RES Command reset function. Be sure to execute this bit after power ON.

Command reset automatically clears this bit following execution (CRES = 1). Therefore, it is not

necessary to set 0 (select normal operation) again by software. Moreover, since the time required

for the value of this bit to change (1 → 0) following command reset execution is extremely short, it

is not necessary to secure time until the command is set following command reset setting.

0: Normal operation

1: Command reset

D3 DSELPH When the 8 colors mode is selected, sets the positive side black data drive method.

0: Inverter drive

1: Amplifier drive

D2 DSELNH When the 8 colors mode is selected, sets the positive side black data drive method.

0: Inverter drive

1: Amplifier drive

D1 DESLPL When the 8 colors mode is selected, sets the positive side black data drive method.

0: Inverter drive

1: Amplifier drive

D0 DSELNL When the 8 colors mode is selected, sets the positive side black data drive method.

0: Inverter drive

1: Amplifier drive

D4 WAS Window access mode setting

When the window access mode is set, the address is incremented/decremented only in the range

set by the MIN. ⋅X address setting register (R8), MAX. ⋅X address setting register (R9), MIN. ⋅Y

address setting register (R10), and MAX. ⋅Y address setting register (R11).

0: Normal operation

1: Window access mode

D2 INC This bit selects the direction in which the address is to be incremented.

0: Increments X address

1: Increments Y address

R6 D7 to D0 XAn This register sets the X address of the display RAM.

Set a value between 00H and EFH.

R7 D6 to D0 YAn This register sets the Y address of the display RAM.

Set a value between 00H and 5FH.

R8 D7 to D0 XMINn Sets the minimum value of the X address in the window access mode.

The X address is incremented up to the maximum value set by the MAX. ⋅X address register (R9),

and then initialized to the address value set by this command.

Set this register to 00H to EFH.

R9 D7 to D0 XMAXn Sets the maximum value of the X address in the window access mode.

The X address is incremented up to the maximum value set by the MIN. ⋅X address register (R8),

and then initialized to the address value set by this command.

Set this register to 00H to EFH.

R10 D6 to D0 YMINn Sets the minimum value of the Y address in the window access mode.

The Y address is incremented up to the maximum value set by the MAX. ⋅Y address register (R11),

and then initialized to the address value set by this command.

Set 00H to 5FH.

R11 D6 to D0 YMAXn Sets the maximum value of the Y address in the window access mode.

The Y address is incremented up to the address value set by this command, and then initialized to

the minimum address value set by the MIN. ⋅Y address register (R10).

Set 00H to 5FH.

Preliminary Product Information S16789EJ2V0PM

PD161606

(4/9)

R15 D6 to D0 P1SLn This is the start Y address register (00H to 5FH) of partial RAM data display area 1.

During partial display or OSD display, the RAM data display area extends up to the line set with

this command and the line count register (R16) of the partial RAM data display area 1.

R16 D6 to D0 P1AWn This is the line count register (00H to 60H) of partial RAM data display area 1.

During partial display or OSD display, the RAM data display area is from to the line set with this

command and the start Y address register (R15) of partial RAM data display area 1.

R17 D0 P1DLn Sets the display start line of partial RAM data display area 1 (00H to 168H).

The display start line of area 1 is specified with R17 and R18.

Perform settings so as to preserve the following relationship.

R17.R18+R16≤R21.R22

R18 D7 to D0 P1DLn Sets the display start line of partial RAM display area 1.

R19 D6 to D0 P2STn This is the start Y address register (00H to 5FH) of partial RAM data display area 2.

During partial display or OSD display, the RAM data display area extends up to the line set with

this command and the line count register (R20) of partial RAM data display area 2.

R20 D6 to D0 P2AWn This is the line count register (00H to 60H) of partial RAM data display area 2.

During partial display or OSD display, the RAM data display area is from to the line set with this

command and the start Y address register (R19) of partial RAM data display area 2.

R21 D0 P2DLn Sets the display start line of partial RAM data display area 2 (00H to 168H).

The display start line of area 1 is specified with R21 and R22.

Perform settings so as to preserve the following relationship.

R17.R18+R16≤R21.R22

R22 D7 to D0 P2DLn Sets the display start line of partial RAM display area 2.

R23 D2,

D1,

PGR,

PGC,

PGB

Partial OFF display color register

Sets the screen color for areas other than the partial display area, during partial display (R0: DTY

= 1). One color can be selected from among 8 colors (1 bit each for R, G, and B) and be set as

the off color.

The relationships between each color data and this register’s bits are as follows. These

relationships do not depend on the ADC value. Following transfer, this command is executed

from the timing at which the next line data is output.

PGR: OFF of R = 0, ON = 1

PGG: OFF of G = 0, ON = 1

PGB: OFF of B = 0, ON = 1

R21 R22 Start line

00H 00H Setting prohibited

00H 01H 1st line

01H 67H 359th line

01H 68H 360th line

R17 R18 Start line

00H 00H Setting prohibited

00H 01H 1st line

01H 67H 359th line

01H 68H 360th line

Preliminary Product Information S16789EJ2V0PM 75

PD161606

When registers R24 to R34 are written to, the serial interface for

PD161645 control is started and data transfer starts.

(5/9)

D6 RGONR For details, refer to the