Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope suitable for surface VDS Drain-source voltage 55 V
mounting. The device features very IDDrain current 7.5 A
low on-state resistance and has Ptot Total power dissipation 1.8 W
integral zener diodes giving ESD TjJunction temperature 150 ˚C
protection. It is intended for use in RDS(ON) Drain-source on-state 80 mΩ
automotive and general purpose resistance VGS = 5 V
switching applications.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ-55V
±VGS Gate-source voltage - - 10 V
IDDrain current (DC) Tsp = 25 ˚C - 7.5 A
IDDrain current (DC) On PCB in Fig.2 - 3.5 A
Tamb = 25 ˚C
IDDrain current (DC) On PCB in Fig.2 - 2.2 A
Tamb = 100 ˚C
IDM Drain current (pulse peak value) Tsp = 25 ˚C - 40 A
Ptot Total power dissipation Tsp = 25 ˚C - 8.3 W
Ptot Total power dissipation On PCB in Fig.2 - 1.8 W
Tamb = 25 ˚C
Tstg, TjStorage & operating temperature - - 55 150 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCElectrostatic discharge capacitor Human body model - 2 kV
voltage (100 pF, 1.5 kΩ)
d
g
s
4
123
April 1998 1 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-sp From junction to solder point Mounted on any PCB 12 15 K/W
Rth j-amb From junction to ambient Mounted on PCB of Fig.18 - 70 K/W
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
Tj = 150˚C 0.6 - - V
Tj = -55˚C - - 2.3 V
IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA
Tj = 150˚C - - 100 µA
IGSS Gate source leakage current VGS = ±5 V - 0.02 1 µA
Tj = 150˚C - - 5 µA
±V(BR)GSS Gate source breakdown voltage IG = ±1 mA 10 - - V
RDS(ON) Drain-source on-state VGS = 5 V; ID = 5 A - 65 80 mΩ
resistance Tj = 150˚C - - 148 mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 25 V; ID = 5 A; Tj = 25˚C 4 8 - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 500 650 pF
Coss Output capacitance - 110 135 pF
Crss Feedback capacitance - 60 85 pF
td on Turn-on delay time VDD = 30 V; ID = 7 A; - 10 15 ns
trTurn-on rise time VGS = 5 V; RG = 10 Ω; - 30 50 ns
td off Turn-off delay time - 30 45 ns
tfTurn-off fall time Tj = 25˚C - 30 40 ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = -55 to 175˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain Tsp = 25˚C - - 7.5 A
current
IDRM Pulsed reverse drain current Tsp = 25˚C - - 40 A
VSD Diode forward voltage IF = 5 A; VGS = 0 V - 0.85 1.1 V
trr Reverse recovery time IF = 5 A; -dIF/dt = 100 A/µs; - 38 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.2 - µC
April 1998 2 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WDSS Drain-source non-repetitive ID = 2.5 A; VDD ≤ 25 V; - - 30 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tsp = 25 ˚C
energy
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
sp
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
sp
); conditions: V
GS
≥
5 V
Fig.3. Safe operating area. T
sp
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
0 20 40 60 80 100 120 140
Tmb / C
PD% Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1 10 100
0.1
1
10
100
VDS/V
RDS(ON) = VDS/ID
DC
ID/A
tp =
1 us
10us
100 us
1 ms
10ms
100ms
0 20 40 60 80 100 120 140
Tmb / C
ID% Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1.0E-06 0.0001 0.01 1 100
0.01
0.1
1
10
100 Zth/ (K/W)
t/s
0.5
0.2
0.1
0.05
0.02 D =
t
p
t
p
T
T
P
t
D
April 1998 3 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
Fig.5. Typical output characteristics, T
j
= 25 ˚C
.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 ˚C
.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
; conditions: V
DS
= 25 V; parameter T
j
Fig.8. Typical transconductance, T
j
= 25 ˚C
.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 5 A; V
GS
= 5 V
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0246810
0
10
20
30
40
ID/A
VDS/V
VGS/V = 10 5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
7
6
0 5 10 15 20
5
6
7
8
9
10
11
12
13
14
15
gfs/S
ID/A
5 10152025
70
75
80
85
90
95
100
105
110
115 RDS(ON)/mOhm
44.2
4.4
4.6
4.8 5
ID/A
BUK98XX-55
-100 -50 0 50 100 150 200
0.5
1
1.5
2
2.5
Tmb / degC
Rds(on) normalised to 25degC
a
012345
0
5
10
15
20
ID/A
VGS/V
Tj/C = 150 25
BUK98xx-55
-100 -50 0 50 100 150 200
0
0.5
1
1.5
2
2.5
Tj / C
VGS(TO) / V
max.
typ.
min.
April 1998 4 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 7 A; parameter V
DS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
sp
); conditions: I
D
= 2.5 A
Fig.16. Avalanche energy test circuit.
0 0.5 1 1.5 2 2.5 3
1E-05
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction
2% typ 98%
0 0.5 1 1.5 2
0
10
20
30
40
IF/A
VSDS/V
Tj/V = 150 25
0.01 0.1 1 10 100
0
.1
.2
.3
.4
.5
.6
.7
.8
.9
1
Thousands pF
VDS/V
Ciss
Coss
Crss
20 40 60 80 100 120 140
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
024681012
0
1
2
3
4
5
6
VDS/V
QG/nC
VDS = 14V
VDS = 44V
L
T.U.T.
VDD
RGS R 01
VDS
-ID/100
+
-
shunt
VGS
0
WDSS =0.5 ⋅LID
2⋅BVDSS/(BVDSS −VDD)
April 1998 5 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
Fig.17. Switching test circuit.
RD
T.U.T.
VDD
RG
VDS
+
-
VGS
0
April 1998 6 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
PRINTED CIRCUIT BOARD
Dimensions in mm.
Fig.18. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35
µ
m thick).
36
60
9
10
4.6
18
4.5
7
15
50
April 1998 7 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
Fig.19. SOT223 surface mounting package.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".
6.7
6.3
3.1
2.9
4
123
2.3
1.05
0.85 0.80
0.60
4.6
3.7
3.3 7.3
6.7
B
A
0.10
0.02
13
16
max
1.8
max
10
max
0.32
0.24
(4x) B
M
0.1
AM0.2
April 1998 8 Rev 1.100
Philips Semiconductors Product specification
TrenchMOS transistor BUK9880-55
Logic level FET
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
April 1998 9 Rev 1.100
