SEMICONDUCTOR TECHNICAL DATA The MC74VHCT374A is an advanced high speed CMOS octal flip-flop with 3-state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings. The VHCT374A input and output (when disabled) structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. * * * * * * * * * * * DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-04 DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-02 High Speed: fmax = 140MHz (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5V to 5.5V Operating Range Low Noise: VOLP = 1.6V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 276 FETs or 69 Equivalent Gates M SUFFIX 20-LEAD SOIC EIAJ PACKAGE CASE 967-01 ORDERING INFORMATION MC74VHCTXXXADW SOIC MC74VHCTXXXADT TSSOP MC74VHCTXXXAM SOIC EIAJ PIN ASSIGNMENT LOGIC DIAGRAM 2 5 6 9 12 15 16 19 3 D0 4 D1 7 D2 8 D3 13 D4 14 D5 17 D6 18 D7 11 CP DATA INPUTS OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS INPUTS L L L H OUTPUT CP D Q L, H, X H L X X H L No Change Z 6/97 Motorola, Inc. 1997 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 10 11 CP GND 1 FUNCTION TABLE OE OE 1 REV 0 MC74VHCT374A IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III III IIIIIIIIIIIIII IIIIII III MAXIMUM RATINGS* Symbol Value Unit DC Supply Voltage - 0.5 to + 7.0 V Vin DC Input Voltage - 0.5 to + 7.0 V Vout DC Output Voltage - 0.5 to + 7.0 - 0.5 to VCC + 0.5 V IIK Input Diode Current - 20 mA IOK Output Diode Current (VOUT < GND; VOUT > VCC) 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature - 65 to + 150 _C VCC Parameter Outputs in 3-State High or Low State SOIC Packages TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. v v * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII IIII IIIIIIII IIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIII III IIII IIII IIII IIIIIII IIIIIII IIII IIIIIIII IIIIIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II III III IIII IIIIIII IIIIIII IIII IIII IIII IIII II II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII III III IIII IIIIIII IIIIIII IIII IIII IIII IIIIII II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage Vin DC Input Voltage Vout DC Output Voltage TA Operating Temperature tr, tf Input Rise and Fall Time Min Max Unit 4.5 5.5 V 0 5.5 V 0 0 5.5 VCC V - 40 + 85 _C 0 20 ns/V Outputs in 3-State High or Low State VCC =5.0V 0.5V DC ELECTRICAL CHARACTERISTICS S b l Symbol P Parameter T Test C Conditions di i VCC V TA = 25C Min VIH Minimum High-Level Input Voltage 4.5 to 5.5 VIL Maximum Low-Level Input Voltage 4.5 to 5.5 VOH Minimum High-Level Output Voltage Vin = VIH or VIL IOH = - 50A 4.5 4.4 IOH = - 8mA 4.5 3.94 Maximum Low-Level Output Voltage Vin = VIH or VIL IOL = 50A 4.5 IOL = 8mA VOL Typ TA = - 40 to 85C Max 2.0 Min Max 2.0 0.8 4.5 U i Unit V 0.8 4.4 V V 3.80 0.0 0.1 0.1 4.5 0.36 0.44 V Maximum Input Leakage Current Vin = 5.5 V or GND 0 to 5.5 0.1 1.0 A IOZ Maximum 3-State Leakage Current Vin = VIL or VIH Vout = VCC or GND 5.5 0.25 2.5 A ICC Maximum Quiescent Supply Current Vin = VCC or GND 5.5 4.0 40.0 A Iin MOTOROLA 2 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHCT374A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII IIII IIIIIIII IIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II IIIIIIII IIIIIII IIII IIIIIII IIIIIII IIII III IIII III IIII IIII II III III IIII IIIIIII IIIIIII IIII IIII IIII IIII II II IIII IIIIIII IIIIIII IIII III IIII III IIII IIII III III IIII IIIIIII IIIIIII IIII IIII IIII IIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIII IIII III IIII III IIII IIII IIII IIIIIIII IIIIIIIII IIIIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II IIIIIIIII IIIIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II IIII IIIIIIII IIIIIIIII IIII III IIII III IIII II IIII IIIIIIII IIIIIIIII IIII III IIII III IIIIII DC ELECTRICAL CHARACTERISTICS Symbol Parameter VCC V Test Conditions ICCT Quiescent Supply Current Per Input: VIN = 3.4V Other Input: VCC or GND IOPD Output Leakage Current VOUT = 5.5V TA = 25C Min TA = - 40 to 85C Typ Max Min Max Unit 5.5 1.35 1.50 mA 0 0.5 5.0 A AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25C S b l Symbol P Parameter T Test C Conditions di i Min Typ 90 85 140 130 TA = - 40 to 85C Max Min Max U i Unit fmax Maximum Clock Frequency (50% Duty Cycle) VCC = 5.0 0.5V CL = 15pF CL = 50pF tPLH, tPHL Maximum Propagation Delay, CP to Q VCC = 5.0 0.5V CL = 15pF CL = 50pF 4.1 5.6 9.4 10.4 1.0 1.0 10.5 11.5 ns tPZL, tPZH Output Enable Time, OE to Q VCC = 5.0 0.5V RL = 1k CL = 15pF CL = 50pF 6.5 7.3 10.2 11.2 1.0 1.0 11.5 12.5 ns tPLZ, tPHZ Output Disable Time OE to Q VCC = 5.0 0.5V RL = 1k CL = 50pF 7.0 11.2 1.0 12.0 ns Output to Output Skew VCC = 5.0 0.5V (Note NO TAG) CL = 50pF 1.0 1.0 ns 10 10 pF tOSLH, tOSHL Cin Cout Maximum Input Capacitance 4 Maximum Three-State Output Capacitance (Output in High-Impedance State) 9 80 95 MHz pF Typical @ 25C, VCC = 5.0V CPD P Power Dissipation Di i i Capacitance C i (N (Note NO TAG) pF F 25 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per flip-flop). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25C S b l Symbol P Parameter Typ Max U i Unit VOLP Quiet Output Maximum Dynamic VOL 1.2 1.6 V VOLV Quiet Output Minimum Dynamic VOL -1.2 -1.6 V VIHD Minimum High Level Dynamic Input Voltage 2.0 V VILD Maximum Low Level Dynamic Input Voltage 0.8 V TIMING REQUIREMENTS (Input tr = tf = 3.0ns) TA = 25C S b l Symbol P Parameter T Test C Conditions di i Typ TA = - 40 to 85C Limit Limit U i Unit tw Minimum Pulse Width, CP VCC = 5.0 0.5 V 6.5 8.5 ns tsu Minimum Setup Time, D to CP VCC = 5.0 0.5 V 2.5 2.5 ns th Minimum Hold Time, D to CP VCC = 5.0 0.5 V 2.5 2.5 ns VHC Data - Advanced CMOS Logic DL203 -- Rev 1 3 MOTOROLA MC74VHCT374A SWITCHING WAVEFORMS 3V 3V OE 1.5V 1.5V CP GND GND tW 1/fmax tPLH Q tPZL tPLZ tPZH tPHZ HIGH IMPEDANCE 1.5V Q VOL +0.3V tPHL VOH 1.5V Q VOL VOH -0.3V 1.5V HIGH IMPEDANCE Figure 1. Figure 2. VALID 3V 1.5V D GND th tsu 3V CP 1.5V GND Figure 3. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. 1 k OUTPUT CL* * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 4. Figure 5. EXPANDED LOGIC DIAGRAM D0 3 D1 4 D Q D C CP OE D2 7 Q D3 8 D C Q D4 13 D C Q D5 14 D C Q D6 17 D C Q D7 18 D C Q D C Q C 11 1 2 Q0 MOTOROLA 5 Q1 6 Q2 9 Q3 4 12 Q4 15 Q5 16 Q6 19 Q7 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHCT374A OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 20 11 -B- 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) T A M B S DIM A B C D F G J K M P R J S F R X 45 _ C -T- G 18X SEATING PLANE MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M K DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A 20X 0.15 (0.006) T U K REF 0.10 (0.004) S M T U S V S K K1 2X L/2 20 IIII IIII IIII 11 J J1 B -U- L PIN 1 IDENT SECTION N-N 1 10 0.25 (0.010) N 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M A -V- N F DETAIL E -W- C D G H DETAIL E 0.100 (0.004) -T- SEATING DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ PLANE VHC Data - Advanced CMOS Logic DL203 -- Rev 1 5 MOTOROLA MC74VHCT374A OUTLINE DIMENSIONS M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 967-01 ISSUE O 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D VIEW P e A c A1 b 0.13 (0.005) M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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