Rev. 1.5 9/13 Copyright © 2013 by Silicon Laboratories Si8460/61/62/63
Not Recommended
for New Designs
Si8460/61/62/63
LOW POWER SIX-CHANNEL DIGITAL ISOLATOR
Features
Applications
Safety Regulatory Approvals
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in a 16-pin narrow-
body SOIC package.
High-speed operation
DC to 150 Mbp s
No start-up initialization required
Wide Operating Supply Voltage:
2.70–5.5 V
Wide Operating Supply Voltage:
2.70–5.5V
Ultra low power (typical)
5 V Operation:
< 1.6 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
2.70 V Op e ra tio n:
< 1.4 mA per channel at 1 Mbps
< 4 mA per channel at 100 Mbps
High electromagnetic immunity
Up to 2500 VRMS isolation
60-year life at rated working
voltage
Precise timing (typica l)
<10 ns worst case
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
Transient Immunity 25 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS-compliant packages
SOIC-16 narrow body
Industrial automation systems
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communications systems
UL 1577 recognized
Up to 2500 VRMS for 1 minute
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
Ordering Information:
See page 29.
Si8460/61/62/63
2 Rev. 1.5
Not Recommended
for New Designs
Si8460/61/62/63
Rev. 1.5 3
Not Recommended
for New Designs
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.1. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . .27
3.2. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Si8460/61/62/63
4 Rev. 1.5
Not Recommended
for New Designs
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Operating Temperature* TA150 Mbps, 15 pF, 5 V –40 25 125 °C
Supply Voltage VDD1 2.70 — 5.5 V
VDD2 2.70 — 5.5 V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Unit
Storage Temperature2TSTG –65 — 150 °C
Ambient Temperature Under Bia s TA–40 — 125 °C
Supply Voltage (Revision A)3VDD1, VDD2 –0.5 — 5.75 V
Supply Voltage (Revision B)3VDD1, VDD2 –0.5 — 6.0 V
Input Voltage VI–0.5 — VDD + 0.5 V
Output Voltage VO–0.5 — VDD + 0.5 V
Output Current Drive Channel IO——10mA
Lead Solder Temperature (10 s) — — 260 °C
Maximum Isolation Voltage (1 s) — — 3600 VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "5. Ordering Guide" on page 29 for more information.
Si8460/61/62/63
Rev. 1.5 5
Not Recommended
for New Designs
Table 3. Electrical Characteristics
(VDD1 =5V±10%, V
DD2 =5V±10%, T
A= –40 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakag e Curr en t IL——±10µA
Output Impedance1ZO—85—
DC Supply Current (All inputs 0 V or at Supply)
Si8460Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
3.3
7.7
3.5
2.6
5.0
11.6
5.3
mA
Si8461Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.1
3.4
7.1
4.5
3.2
5.1
10.7
6.8
mA
Si8462Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.5
3.0
6.5
5.0
3.8
4.5
9.8
8.3
mA
Si8463Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.8
2.8
6.0
6.0
4.2
4.2
9.0
9.0
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
6 Rev. 1.5
Not Recommended
for New Designs
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8460Ax, Bx
VDD1
VDD2
—
—4.7
4.0 7.1
6.0 mA
Si8461Ax, Bx
VDD1
VDD2
—
—4.7
4.5 7.1
6.8 mA
Si8462Ax, Bx
VDD1
VDD2
—
—4.7
4.3 7.1
6.5 mA
Si8463Ax, Bx
VDD1
VDD2
—
—4.7
4.7 7.1
7.1 mA
10 Mb ps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—4.7
5.5 7.1
7.7 mA
Si8461Bx
VDD1
VDD2
—
—5.0
5.7 7.2
8mA
Si8462Bx
VDD1
VDD2
—
—5.2
5.4 7.3
7.6 mA
Si8463Bx
VDD1
VDD2
—
—5.5
5.5 7.7
7.7 mA
Table 3. Electrical Characteristics (Continued)
(VDD1 =5V±10%, V
DD2 =5V±10%, T
A= –40 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
Rev. 1.5 7
Not Recommended
for New Designs
100 Mb ps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—5.0
28.8 7.5
36 mA
Si8461Bx
VDD1
VDD2
—
—9.0
25 11.3
30 mA
Si8462Bx
VDD1
VDD2
—
—13.3
20.8 16.6
26 mA
Si8463Bx
VDD1
VDD2
—
—17.2
17.2 21.5
21.5 mA
Timing Characteristics
Si846xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si846xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — 1.5 2.5 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
Table 3. Electrical Characteristics (Continued)
(VDD1 =5V±10%, V
DD2 =5V±10%, T
A= –40 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
8 Rev. 1.5
Not Recommended
for New Designs
Figure 1. Propagation Delay Timing
All Models
Output Rise Time trCL=15pF
See Figure 1 —3.85.0ns
Output Fall Time tfCL=15pF
See Figure 1 —2.83.7ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Start-up Time3tSU —1540µs
Table 3. Electrical Characteristics (Continued)
(VDD1 =5V±10%, V
DD2 =5V±10%, T
A= –40 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V
Si8460/61/62/63
Rev. 1.5 9
Not Recommended
for New Designs
Table 4. Electrical Characteristics
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—85—
DC Supply Current (All inputs 0 V or at supply)
Si8460Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
3.3
7.7
3.5
2.6
5.0
11.6
5.3
mA
Si8461Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.1
3.4
7.1
4.5
3.2
5.1
10.7
6.8
mA
Si8462Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.5
3.0
6.5
5.0
3.8
4.5
9.8
8.3
mA
Si8463Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.8
2.8
6.0
6.0
4.2
4.2
9.0
9.0
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminate d with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. S tart-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
10 Rev. 1.5
Not Recommended
for New Designs
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8460Ax, Bx
VDD1
VDD2
—
—4.7
4.0 7.1
6.0 mA
Si8461Ax, Bx
VDD1
VDD2
—
—4.7
4.5 7.1
6.8 mA
Si8462Ax, Bx
VDD1
VDD2
—
—4.7
4.3 7.1
6.5 mA
Si8463Ax, Bx
VDD1
VDD2
—
—4.7
4.7 7.1
7.1 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—4.7
5.5 7.1
7.7 mA
Si8461Bx
VDD1
VDD2
—
—5.0
5.7 7.2
8.0 mA
Si8462Bx
VDD1
VDD2
—
—5.2
5.4 7.3
7.6 mA
Si8463Bx
VDD1
VDD2
—
—5.5
5.5 7.7
7.7 mA
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminate d with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. S tart-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
Rev. 1.5 11
Not Recommended
for New Designs
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—4.8
20 7.2
25 mA
Si8461Bx
VDD1
VDD2
—
—7.4
17.7 9.3
22.1 mA
Si8462Bx
VDD1
VDD2
—
—10.2
15 12.8
18.8 mA
Si8463Bx
VDD1
VDD2
—
—12.7
12.7 15.9
15.9 mA
Timing Characteristics
Si846xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL,tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si846xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — 1.5 2.5 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition M in Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminate d with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. S tart-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
12 Rev. 1.5
Not Recommended
for New Designs
All Models
Output Rise Time trCL=15pF
See Figure 1 —4.36.1ns
Output Fall Time tfCL=15pF
See Figure 1 —3.04.3ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Start-up Time3tSU —1540µs
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition M in Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminate d with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. S tart-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
Rev. 1.5 13
Not Recommended
for New Designs
Table 5. Electrical Characteristics1
(VDD1 = 2.7 0 V, VDD2 = 2.70 V, TA= –4 0 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 2.3 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance2ZO—85—
DC Supply Current (All inputs 0 V or at supply)
Si8460Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
3.3
7.7
3.5
2.6
5.0
11.6
5.3
mA
Si8461Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.1
3.4
7.1
4.5
3.2
5.1
10.7
6.8
mA
Si8462Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.5
3.0
6.5
5.0
3.8
4.5
9.8
8.3
mA
Si8463Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.8
2.8
6.0
6.0
4.2
4.2
9.0
9.0
mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be ap propriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
14 Rev. 1.5
Not Recommended
for New Designs
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8460Ax, Bx
VDD1
VDD2
—
—4.7
4.0 7.1
6.0 mA
Si8461Ax, Bx
VDD1
VDD2
—
—4.7
4.5 7.1
6.8 mA
Si8462Ax, Bx
VDD1
VDD2
—
—4.7
4.3 7.1
6.5 mA
Si8463Ax, Bx
VDD1
VDD2
—
—4.7
4.7 7.1
7.1 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—4.7
5.5 7.1
7.7 mA
Si8461Bx
VDD1
VDD2
—
—5.0
5.7 7.2
8.0 mA
Si8462Bx
VDD1
VDD2
—
—5.2
5.4 7.3
7.6 mA
Si8463Bx
VDD1
VDD2
—
—5.5
5.5 7.7
7.7 mA
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.7 0 V, VDD2 = 2.70 V, TA= –4 0 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be ap propriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
Rev. 1.5 15
Not Recommended
for New Designs
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—4.8
15.8 7.2
19.8 mA
Si8461Bx
VDD1
VDD2
—
—6.7
14.2 8.4
17.8 mA
Si8462Bx
VDD1
VDD2
—
—8.7
12.2 10.9
15.3 mA
Si8463Bx
VDD1
VDD2
—
—10.5
10.5 13.1
13.1 mA
Timing Characteristics
Si846xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL,tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew3tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si846xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — 1.5 2.5 ns
Propagation Delay Skew3tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.7 0 V, VDD2 = 2.70 V, TA= –4 0 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be ap propriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
16 Rev. 1.5
Not Recommended
for New Designs
All Models
Output Rise Time trCL=15pF
See Figure 1 —4.86.5ns
Output Fall Time tfCL=15pF
See Figure 1 —3.24.6ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Start-up Time4tSU —1540µs
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 130 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5- 2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 Vpeak for basic insulation working voltage.
UL
The Si84xx is certified under UL1577 component recognition prog ram. For more details, see File E257455.
Rated up to 2500 VRMS isolation voltage for basic insulation.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 29.
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.7 0 V, VDD2 = 2.70 V, TA= –4 0 to 125 °C; applies to narrow-body SOIC package)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be ap propriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Si8460/61/62/63
Rev. 1.5 17
Not Recommended
for New Designs
Table 7. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
NB SOIC-16
Nominal Air Gap (Clearance)1L(IO1) 3.9 min mm
Nominal External Tracking (Creepage)1L(IO2) 3.9 min mm
Minimum Inter n al Ga p (In te rna l Cleara nce ) 0.008 mm
Tracking Resistance
(Proof Tracking Index) PTI IEC60112 600 VRMS
Erosion Depth ED 0.019 mm
Resistance (Input-Output)2RIO 1012
Capacitance (Input-Output)2CIO f=1MHz 2.0 pF
Input Capacitance3CI4.0 pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “6. Pa ckage Outline:
16-Pin Narrow Body SOIC”. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16
package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the
clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter Test Condition Specification
Basic Isolation Group Material Group I
Installation Classification
Rated Mains Voltages < 150 VRMS I-IV
Rated Mains Voltages < 300 VRMS I-III
Rated Mains Voltages < 400 VRMS I-II
Rated Mains Voltages < 600 VRMS I-II
Si8460/61/62/63
18 Rev. 1.5
Not Recommended
for New Designs
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter Symbol Test Condition Characteristic Unit
Maximum Working Insulation Voltage VIORM 560 V peak
Input to Output Test Voltage VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm=1 sec,
Partial Discharge < 5 pC) 1050
V peak
Transient Overvoltage VIOTM t = 60 sec 4000 V peak
Pollution Degree (DIN VDE 0110, Table 1) 2
Insulation Resistance at TS, VIO =500V RS>109
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter Symbol Test Condition Min Typ Max Unit
NB SOIC-16
Case Temperature TS— — 150 °C
Safety input, output, or
supply current ISJA = 105 °C/W (NB SOIC-16),
VI=5.5V, T
J=150°C, T
A=25°C — — 215 mA
Device Power Dissipation2PD— — 415 mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2.
2. The Si846x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Si8460/61/62/63
Rev. 1.5 19
Not Recommended
for New Designs
Figure 2. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 11. Thermal Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
NB SOIC-16
IC Junction-to- Air T herm a l
Resistance JA —105—°C/W
020015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
430
300
360
215
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
Si8460/61/62/63
20 Rev. 1.5
Not Recommended
for New Designs
2. Functional Description
2.1. Theory of Operation
The operation of an Si846x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si846x channel is shown in
Figure 3.
Figure 3. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 4 for more details.
Figure 4. Modulation Scheme
RF
OSCILLATOR
MODULATOR DEMODULATOR
A B
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Input Signal
Output Signal
Modulation Signal
Si8460/61/62/63
Rev. 1.5 21
Not Recommended
for New Designs
2.2. Eye Diagram
Figure 5 illustrates an eye-diagram taken on an Si8460. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8460 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 5. Eye Diagram
Si8460/61/62/63
22 Rev. 1.5
Not Recommended
for New Designs
2.3. Device Operation
Device behavior during startup, normal operation, and shutdown is shown in Table 12.
Table 12. Si846x Logic Operation Table
VI
Input1,2 VDDI
State1,3,4 VDDO
State1,3,4 VO Output1,2 Comments
HP P H
Normal operation.
LP P L
X5UP P L Upon transition of VDDI from unpowered to powered, VO
returns to the same state as VI in less than 1 µs.
X5P UP Undetermined Upon transition of VDDO from unpowered to powered, V O
returns to the same state as VI within 1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diod e if its source has adequate current.
Si8460/61/62/63
Rev. 1.5 23
Not Recommended
for New Designs
2.4. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance
(creepage/clear ance). I f a com ponent, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 16 and Table 7 on page 17 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.)
requirements before starting an y des ign tha t uses a digital isolator.
The following sections detail the recommended bypass and decoupling components necessary to ensure robust
overall performance and reliability for systems using the Si84xx digital isolators.
2.4.1. Supply Bypass
Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically
quiet environments. However, digital isolators are commonly used in hazardous environments with excessively
noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass
capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as
close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is
recommended that the designer add 50 to 100 resistors in series with t he VDD supply voltage source and 50 to
300 resistors in series with the digital inputs/outputs (see Figure 6). For more deta ils, see "3. Errata and Design
Migration Guidelines" on page 27.
All components upstream or downstream of the isolator should be properly decoup led as well. If these component s
are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing
damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300 resistors protect
the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are
exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended
Operating Conditions,” on page 4.
2.4.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
2.4.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination
of the value of the on-chip series termination resistor and cha nnel resist ance of the output driver FET. When driving
loads where transmission line effect s will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in
mind the recommendations described in “2.4.1. Supply Bypass” above.
Figure 6. Recommended Bypass Components for the Si84xx Digital Isolator Family
VDD1 VDD2
GND1 GND2
50 – 300 50 – 300
Input/OutputInput/Output
C2 C3
1 F1 F
R1 (50 – 100 )
V Source 1
A1 B1
50 – 300
50 – 300
Ax Bx
C1
R2 (50 – 100 )
V Source 2
C4
0.1 F0.1 F
Si8460/61/62/63
24 Rev. 1.5
Not Recommended
for New Designs
2.5. Typical Performance Characteristics
The typical performance ch ar acteristics depicted in the following diagrams ar e for info rma tio n pur poses o nly. Refer
to Tables 3, 4, and 5 for actual specification limits.
Figure 7. Si8460 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 8. Si8461 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 9. Si8462 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 10. Si8460 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 11. Si8461 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 12. Si8462 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
0
5
10
15
20
25
30
35
40
45
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (M b p s)
Cur r en t (mA)
5V
3.3V
2.70V
0
5
10
15
20
25
30
35
40
45
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (M b p s)
Cur r en t (mA)
5V
3.3V
2.70V
0
5
10
15
20
25
30
35
40
45
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (M b p s)
Cur r en t (mA)
5V
3.3V
2.70V
0
5
10
15
20
25
30
35
40
45
0 102030405060708090100110120130140150
Data Rate (M b p s)
Cur r en t (mA)
5V
3.3V
2.70V
0
5
10
15
20
25
30
35
40
45
0 102030405060708090100110120130140150
Data Rate (M b p s)
Cur r en t (mA)
5V
2.70V
3.3V
0
5
10
15
20
25
30
35
40
45
0 102030405060708090100110120130140150
Data Rate (M b p s)
Cur r en t (mA)
5V
3.3V
2.70V
Si8460/61/62/63
Rev. 1.5 25
Not Recommended
for New Designs
Figure 13. Si8463 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Figure 14. Propagation Delay vs. Temperature
0
5
10
15
20
25
30
35
40
45
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (M b p s)
Cur r en t (mA)
5V
3.3V
2.70V
5
6
7
8
9
10
-40 -20 0 20 40 60 80 100 120
Temperature (Degrees C)
Delay (ns )
Risi ng Edge
Falling Edge
Si8460/61/62/63
26 Rev. 1.5
Not Recommended
for New Designs
Figure 15. Si84xx Time-Dependent Dielectric Breakdown
Si8460/61/62/63
Rev. 1.5 27
Not Recommended
for New Designs
3. Errata and Design Migration Guidelines
When using the new Si846x products, or when migrating from Silicon Labs' legacy isolators, designers must
consider and ad h ere to the fo llow i ng requir em e nts.
3.1. Power Supply Bypass Capacitors (Revision A and Revision B)
When using the Si846x isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on
both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V
supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins
(VDD1, VDD2) of the isolator device.
3.1.1. Resolution
For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 23. Additionally, refer to "5.
Ordering Guide" on page 29 for current ordering information.
3.2. Latch Up Immunity (Revision A Only)
Latch up immunity generally exceeds ± 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latch-up
immunity. To increase latch-up immunity on these pins, 100 of equivalent resistance must be included in series
with all of the pins listed in Table 13. The 100 equivalent resistance can be comprised of the source driver's
output resistance and a series termination resistor.
3.2.1. Resolution
This issue has been corrected with Revision B of the device. Refer to "5. Ordering Guide" on page 29 for more
information.
Table 13. Affected Ordering Part Numbers (Revision A Only)
Affected Ordering Part Numbers* Device
Revision Pin# Name Pin Type
SI8460SV-A-IS/IS1, SI8461SV-A-IS/IS1,
SI8462SV-A-IS/IS1, SI8463SV-A-IS/IS1 A
2 A1 Input
6 A5 Input or Output
10 B6 Input or Output
14 B2 Output
*Note: SV = Spee d Grade/Isolation Rating (AA, AB, BA, BB).
Si8460/61/62/63
28 Rev. 1.5
Not Recommended
for New Designs
4. Pin Descriptions
Name SOIC-16 Pin# Type Description
VDD1 1 Supply Side 1 power supply.
A1 2 Digital Input Side 1 digital input.
A2 3 Digital Input Side 1 digital input.
A3 4 Digital Input Side 1 digital input.
A4 5 Digital I/O Side 1 digital input or output.
A5 6 Digital I/O Side 1 digital input or output.
A6 7 Digital I/O Side 1 digital input or output.
GND1 8 Ground Side 1 ground.
GND2 9 Ground Side 2 ground.
B6 10 Digital I/O Side 2 digital input or output.
B5 11 Digital I/O Side 2 digital input or output.
B4 12 Digital I/O Side 2 digital input or output.
B3 13 Digital Output Side 2 digital output.
B2 14 Digital Output Side 2 digital output.
B1 15 Digital Output Side 2 digital output.
VDD2 16 Supply Side 2 power supply.
VDD1
A1
A3
A4
GND1
A2
VDD2
B2
B1
B4
B3
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR RF
RCVR
RF
XMITR RF
RCVR
RF
XMITR RF
RCVR
RF
XMITR RF
RCVR
Si8460
A5
RF
XMITR RF
RCVR
B5
B6A6 RF
XMITR RF
RCVR
VDD1
A1
A3
A4
GND1
A2
VDD2
B2
B1
B4
B3
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR RF
RCVR
RF
XMITR RF
RCVR
RF
XMITR RF
RCVR
Si8461
RF
XMITR RF
RCVR
A5 B5
RF
XMITR
RF
RCVR B6
A6
RF
XMITR RF
RCVR
VDD1
A1
A3
A4
GND1
A2
VDD2
B2
B1
B4
B3
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR RF
RCVR
RF
XMITR RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
Si8462
RF
XMITR RF
RCVR
A5 B5
B6A6
RF
XMITR RF
RCVR
VDD1
A1
A3
A4
GND1
A2
VDD2
B2
B1
B4
B3
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR RF
RCVR
RF
XMITR RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
Si8463
RF
XMITR RF
RCVR
A5 B5
B6A6
RF
XMITR
RF
RCVR
Si8460/61/62/63
Rev. 1.5 29
Not Recommended
for New Designs
5. Ordering Guide
These devices are not recommended for new designs. Please see the Si866x data sheet for replacement options.
Table 14. Ordering Guide for Valid OPNs1
Ordering Part
Number
(OPN)
Alternative Part
Number (APN) Number of
Inputs VDD1
Side
Number of
Inputs VDD2
Side
Maximum
Data Rate
(Mbps)
Isolation
Rating Package Type
Revision B Devices2
Si8460AA-B-IS1 Si8660BA-B-IS1 6 0 1
1 kVrms NB SOIC-16
Si8460BA-B-IS1 Si8660BA-B-IS1 6 0 150
Si8461AA-B-IS1 Si8661AB-B-IS1 5 1 1
Si8461BA-B-IS1 Si8661BB-B-IS1 5 1 150
Si8462AA-B-IS1 Si8662AB-B-IS1 4 2 1
Si8462BA-B-IS1 Si8662BB-B-IS1 4 2 150
Si8463AA-B-IS1 Si8663AB-B-IS1 3 3 1
Si8463BA-B-IS1 Si8663BB-B-IS1 3 3 150
Si8460AB-B-IS1 Si8660AB-B-IS1 6 0 1
2.5 kVrms NB SOIC-16
Si8460BB-B-IS1 Si8660BB-B-IS1 6 0 150
Si8461AB-B-IS1 Si8661AB-B-IS1 5 1 1
Si8461BB-B-IS1 Si8661BB-B-IS1 5 1 150
Si8462AB-B-IS1 Si8662AB-B-IS1 4 2 1
Si8462BB-B-IS1 Si8662BB-B-IS1 4 2 150
Si8463AB-B-IS1 Si8663AB-B-IS1 3 3 1
Si8463BB-B-IS1 Si8663BB-B-IS1 3 3 150
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C according to
the JEDEC industry standard classifications and peak solder temperature.
2. Revision A and Revision B devices are supported for existing designs.
Si8460/61/62/63
30 Rev. 1.5
Not Recommended
for New Designs
Revision A Devices2
Si8460AA-A-IS1 Si8660BA-B-IS1 6 0 1
1 kVrms NB SOIC-16
Si8460BA-A-IS1 Si8660BA-B-IS1 6 0 150
Si8461AA-A-IS1 Si8661AB-B-IS1 5 1 1
Si8461BA-A-IS1 Si8661BB-B-IS1 5 1 150
Si8462AA-A-IS1 Si8662AB-B-IS1 4 2 1
Si8462BA-A-IS1 Si8662BB-B-IS1 4 2 150
Si8463AA-A-IS1 Si8663AB-B-IS1 3 3 1
Si8463BA-A-IS1 Si8663BB-B-IS1 3 3 150
Si8460AB-A-IS1 Si8660AB-B-IS1 6 0 1
2.5 kVrms NB SOIC-16
Si8460BB-A-IS1 Si8660BB-B-IS1 6 0 150
Si8461AB-A-IS1 Si8661AB-B-IS1 5 1 1
Si8461BB-A-IS1 Si8661BB-B-IS1 5 1 150
Si8462AB-A-IS1 Si8662AB-B-IS1 4 2 1
Si8462BB-A-IS1 Si8662BB-B-IS1 4 2 150
Si8463AB-A-IS1 Si8663AB-B-IS1 3 3 1
Si8463BB-A-IS1 Si8663BB-B-IS1 3 3 150
Table 14. Ordering Guide for Valid OPNs1
Ordering Part
Number
(OPN)
Alternative Part
Number (APN) Number of
Inputs VDD1
Side
Number of
Inputs VDD2
Side
Maximum
Data Rate
(Mbps)
Isolation
Rating Package Type
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C according to
the JEDEC industry standard classifications and peak solder temperature.
2. Revision A and Revision B devices are supported for existing designs.
Si8460/61/62/63
Rev. 1.5 31
Not Recommended
for New Designs
6. Package Outline: 16-Pin Narrow Body SOIC
Figure 16 illustrates the package details for the Si846x in a 16-pin narrow-body SOIC (SO-16). Table 15 lists the
values for the dimensions shown in the illustration.
Figure 16. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 15. Package Diagram Dimensions
Dimension Min Max
A — 1.75
A1 0.10 0.25
A2 1.25 —
b 0.31 0.51
c 0.17 0.25
D 9.90 BSC
E 6.00 BSC
E1 3.90 BSC
e 1.27 BSC
L 0.40 1.27
L2 0.25 BSC
Si8460/61/62/63
32 Rev. 1.5
Not Recommended
for New Designs
h 0.25 0.50
θ0° 8°
aaa 0.10
bbb 0.20
ccc 0.10
ddd 0.25
Notes:
1. All dimensions shown are in millime ters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012,
Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Table 15. Package Diagram Dimensions (Continued)
Dimension Min Max
Si8460/61/62/63
Rev. 1.5 33
Not Recommended
for New Designs
7. Land Pattern: 16-Pin Narrow Body SOIC
Figure 17 illustrates the recommended land pattern details for the Si846x in a 16-pin narrow-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 17. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 16. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Si8460/61/62/63
34 Rev. 1.5
Not Recommended
for New Designs
8. Top Marking: 16-Pin Narrow Body SOIC
8.1. 16-Pin Narrow Body SOIC Top Marking
8.2. Top Marking Explanation
Line 1 Marking: Base Part Number
Ordering Options
(See Ordering Guide for more
information).
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (6, 5, 4, 3, 2, 1)
Y = # of reverse channels (3, 2, 1, 0)
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV
Line 2 Marking: Circle = 1.2 mm Diameter “e3” Pb-Free Symbol
YY = Year
WW = Work Week Assigned by the Asse m bly Hous e. Corr es po n ds to the
year and work week of the mold date.
TTTTTT = Mfg code Manufacturing Code from Assembly Purchase Or der
form.
Circle = 1.2 mm diameter “e3” Pb-Free Symbol.
Si84XYSV
YYWWTTTTTT
e3
Si8460/61/62/63
Rev. 1.5 35
Not Recommended
for New Designs
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated all specs to reflect latest silicon.
Added "3. Errata and Design Migration Guidelines"
on page 27.
Added "8. Top Marking: 16-Pin Narrow Body SOIC"
on page 34.
Revision 0.2 to Revision 1.0
Updated document to reflect availability of Revision
B silicon.
Updated Tables 3,4, and 5.
Updated all supply currents and channel-channel skew .
Updated Table 2.
Updated absolute maximum supply voltage.
Updated Table 7.
Updated clearance and creepage dimensions.
Updated "3. Errat a and Design Migration Guidelin es"
on page 27.
Updated "5. Ordering Guide" on page 29.
Revision 1.0 to Revision 1.1
Updated Tables 3, 4, and 5.
Updated notes in tables to reflect output impedance of
85 .
Updated rise and fall time specifications.
Updated CMTI value.
Revision 1.1 to Revision 1.2
Updated document throughout to include MSL
improveme nts to MSL2A.
Updated "5. Ordering Guide" on page 29.
Updated Note 1 in ordering guide table to reflect
improvement and compliance to MSL2A moisture
sensitivity level.
Revision 1.2 to Revision 1.3
Updated " Features" on page 1.
Moved Tables 1 and 2 to page 4.
Updated Tables 6, 7, 8, and 9.
Updated Table 12 fo ot no te s.
Added Figure 15, “Si84xx Time-Dependent
Dielectric Breakdown,” on page 26.
Revision 1.3 to Revision 1.4
Updated "4. Pin Descriptions" on page 28.
Removed note for narrow-body devices.
Updated "2.4.1. Supply Bypass" on page 23.
Added Figure 6, “Recommended Bypass
Components for the Si84xx Digital Isolator Family,”
on page 23.
Updated "3.1. Power Supply Bypass Capacitors
(Revision A and Revision B)" on page 27.
Revision 1.4 to Revision 1.5
Updated "5. Ordering Guide" on page 29 to include
new title note and “ Alternative Part Number (APN)”
column.
Si8460/61/62/63
36 Rev. 1.5
Not Recommended
for New Designs
CONTACT INFORMATION
Silicon Laboratories Inc.
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Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
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Si8460AA-B-IS1 Si8460AB-B-IS1 Si8460BA-B-IS1 Si8460BB-B-IS1 Si8461AA-B-IS1 Si8461AB-B-IS1 Si8461BA-
B-IS1 Si8461BB-B-IS1 Si8462AA-B-IS1 Si8462AB-B-IS1 Si8462BA-B-IS1 Si8462BB-B-IS1 Si8463AA-B-IS1
Si8463AB-B-IS1 Si8463BA-B-IS1 Si8463BB-B-IS1 SI8460AA-B-IS1R SI8460AB-B-IS1R SI8460BA-B-IS1R
SI8460BB-B-IS1R SI8461AA-B-IS1R SI8461AB-B-IS1R SI8461BA-B-IS1R SI8461BB-B-IS1R SI8462AA-B-IS1R
SI8462AB-B-IS1R SI8462BA-B-IS1R SI8462BB-B-IS1R SI8463AA-B-IS1R SI8463AB-B-IS1R SI8463BA-B-IS1R
SI8463BB-B-IS1R Si8461BA-A-IS1R Si8461AB-A-IS1R Si8463AB-A-IS1R Si8461AA-A-IS1R Si8463AA-A-IS1R
Si8460BA-A-IS1R Si8462BB-A-IS1R Si8463BB-A-IS1R Si8460AB-A-IS1R Si8462BA-A-IS1R Si8462AA-A-IS1R
Si8462AB-A-IS1R Si8461BB-A-IS1R Si8463BA-A-IS1R Si8460AA-A-IS1R Si8460BB-A-IS1R SI8460AA-A-IS1
SI8460AB-A-IS1 SI8460BA-A-IS1 SI8460BB-A-IS1 SI8461AA-A-IS1 SI8461AB-A-IS1 SI8461BA-A-IS1 SI8461BB-A-
IS1 SI8462AA-A-IS1 SI8462AB-A-IS1 SI8462BA-A-IS1 SI8462BB-A-IS1 SI8463AA-A-IS1 SI8463AB-A-IS1
SI8463BA-A-IS1 SI8463BB-A-IS1 SI8460AA-A-IS1R SI8460AB-A-IS1R SI8461BA-B-IS1 SI8460AB-B-IS1
SI8463BB-A-IS1R SI8463BA-B-IS1 SI8461AA-A-IS1R SI8462AB-B-IS1 SI8463AB-A-IS1R SI8462BA-A-IS1R
SI8462BB-B-IS1 SI8461BA-A-IS1R SI8461BB-A-IS1R SI8462AB-A-IS1R SI8463BA-A-IS1R SI8460AA-B-IS1
SI8460BB-A-IS1R SI8461AA-B-IS1 SI8463BB-B-IS1 SI8463AB-B-IS1 SI8460BB-B-IS1 SI8461AB-B-IS1 SI8463AA-
B-IS1 SI8462BB-A-IS1R SI8462AA-B-IS1 SI8461BB-B-IS1 SI8462BA-B-IS1 SI8461AB-A-IS1R SI8460BA-B-IS1
SI8462BA-A-IS1 SI8462BB-A-IS1 SI8463AA-A-IS1 SI8463AB-A-IS1 SI8463BA-A-IS1 SI8463BB-A-IS1 SI8461AA-A-
IS1
