W9425GBDA-6 256MB (32M x 64) DDR SDRAM DIMM 1. GENERAL DESCRIPTION The W9425GBDA is a 256MB Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) memory modules. It is organized in a 32M x 64 bit configuration using eight pieces of Winbond W942508BH (32M x 8 bits) DDR SDRAMs and assembled on a JEDEC standard 184-pin DIMM PCB. To provide high data bandwidth, W9425GBDA uses a double data rate architecture to transfer two data words per clock cycle and delivers a data bandwidth of up to 2.7G (DDR333) bytes per second. It is ideal for high performance systems that require fast data transfer memory modules. By reading the Serial Presence-Detect (SPD), the system can identify the module type, DDR SDRAM timing parameters and other necessary information to optimize system setting and maximize its performance. 2. FEATURES * JEDEC standard 184-pin, Dual In-Line Memory Module (DIMM) * Comply to DDR333 specification * Differential clock inputs (CLK and CLK ) * Double Data Rate architecture, two data transfers per clock cycle * CAS Latency: 2.5 * Burst Lengths: 2, 4, 8 * Auto Refresh and Self Refresh * 8K refresh cycles / 64 mS * Serial Presence Detect with EEPROM * Interface: SSTL-2 * Power supply: 2.5V 0.1V * PCB height: 1.25 inches 3. AVAILABLE PART NUMBERS MODULE PART NUMBER SPEED W9425GBDA-6 DDR333/CL2.5 -1- Publication Release Date: March 15, 2002 Revision A1 W9425GBDA-6 4. PIN ASSIGNMENT PIN FONT PIN FONT PIN FONT PIN BACK PIN BACK PIN BACK 1 VREF 32 A5 62 VDDQ 93 VSS 124 VSS 154 RAS 2 DQ0 33 DQ24 63 WE 94 DQ4 125 A6 155 DQ45 3 VSS 34 VSS 64 DQ41 95 DQ5 126 DQ28 156 VDDQ 4 DQ1 35 DQ25 65 CAS 96 VDDQ 127 DQ29 157 CS0 5 DQS0 36 DQS3 66 VSS 97 DQS9 128 VDDQ 158 CS1 6 DQ2 37 A4 67 DQS5 98 DQ6 129 DQS12 159 DQS14 7 VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS 8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46 9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47 10 NC 41 A2 71 *S2 102 NC 133 DQ31 163 *S3 11 VSS 42 VSS 72 DQ48 103 *A13 134 *CB4 164 VDDQ 12 DQ8 43 A1 73 DQ49 104 VDDQ 135 *CB5 165 DQ52 13 DQ9 44 *CB0 74 VSS 105 DQ12 136 VDDQ 166 DQ53 14 DQS1 45 *CB1 75 CLK2 106 DQ13 137 CLK0 167 NC 15 VDDQ 46 VDD 76 CLK2 107 DQS10 138 CLK 0 168 VDD 16 CKL1 47 *DQS8 77 VDDQ 108 VDD 139 VSS 169 DQS15 17 CLK1 48 A0 78 DQS6 109 DQ14 140 *DQS17 170 DQ54 18 VSS 49 *CB2 79 DQ50 110 DQ15 141 A10 171 DQ55 19 DQ10 50 VSS 80 DQ51 111 CKE1 142 *CB6 172 VDDQ 20 DQ11 51 *CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC 21 CKE0 52 BA1 82 VDDID 113 *BA2 144 *CB7 174 DQ60 22 VDDQ 83 DQ56 114 DQ20 175 DQ61 23 DQ16 53 DQ32 84 DQ57 115 A12 145 VSS 176 VSS 24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DQS16 25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62 26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63 27 A9 57 DQ34 88 DQ59 119 DQS11 149 DQS13 180 VDDQ 28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0 29 A7 59 BA0 90 WP 121 DQ22 151 DQ39 182 SA1 30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2 31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSP KEY *These pins are not used in this module. -2- KEY W9425GBDA-6 5. PIN DESCRIPTIONS PIN NAME CLKn, CLKn FUNCTION DESCRIPTION Clock Input CLKn and CLKn are differential clock inputs. All input command signals are sampled at the positive edge of CLK(except for DQ, DM and CKE). Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self-Refresh mode is entered. Address Multiplexed pins for row and column address. Row address: A0 - A12. Column address: A0 - A9. BA0 - BA1 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Command input. When sampled at the rising edge of the clock, RAS , CAS Column Address Strobe Referred to RAS WE Write Enable Referred to RAS DM0 - DM7 Input/Output Mask The output buffer is placed at Hi-Z when DM is sampled high in read cycle. In write cycle, sampling DM high will block the write data. DQ0 - DQ63 Data Input/Output Multiplexed pins for data output and input DQS0 - DQS7 Data Strobe Input/Output Output with read data, input with write data. DQS is edge-aligned with read data, centered in write data. VDD Power (+2.5V) Power supply (2.5V). VSS Ground Ground VREF Reference Voltage SSTL-2 Reference voltage VDDSPD SPD Power Separated power supply for SPD EEPROM (2.3V - 3.6V) SCL Serial Clock Clock for serial presence detection SDA Serial Data I/O Data line for serial presence detection SAn SPD Address Line System assigned address (SA0 - SA2) to identify different memory module in a system board. NC No Connection No connection CSn CKEn A0 - A12 CAS and WE define the operation to be executed. -3- Publication Release Date: March 15, 2002 Revision A1 W9425GBDA-6 6. BLOCK DIAGRAM CS0 DQS0 DM0/DQS9 DQS4 DM4/DQS13 DM CS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U0 DQS1 DM1/DQS10 CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS U4 DQS5 DM5/DQS14 DM CS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U1 DQS2 DM2/DQS11 CS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS U5 DQS6 DM6/DQS15 DM CS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U4 DQS3 DM3/DQS12 CS I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS U6 DQS7 DM7/DQS16 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U3 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS U7 A0 ~ A13, BA0 & 1 SDRAMs U0 ~ U7 RAS SDRAMs U0 ~ U7 CAS SDRAMs U0 ~ U7 WE SDRAMs U0 ~ U7 SERIAL PD SCL SDA U7 A0 SA0 A1 SA1 A2 WP SA2 SDA VDD SPD SPD VDD/VDDQ D0~D7 VREF D0~D7 VSS D0~D7 VDDID -2- W9425GBDA-6 7. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTES Input, Output Voltage VIN, VOUT -0.3 - VDDQ +0.3 V 1 Power Supply Voltage VDD, VDDQ -0.3 - 3.6 V 1 Operating Temperature TOPR 0 - 70 C 1 Storage Temperature TSTG -55 - 150 C 1 TSOLDER 260 C 1 PD 8 W 1 IOUT 50 mA 1 Soldering Temperature (10s) Power Dissipation for Each Component Short Circuit Output Current Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 8. RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to 70 C) MAX. UNIT NOTES 2.5 2.6 V 2 2.5 VDD V 2 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2, 3 VTT VREF -0.04 VREF VREF +0.04 V 2 Input High Voltage (DC) VIH (DC) VREF +0.15 - VDDQ +0.3 V 2 Input Low Voltage (DC) VIL (DC) -0.3 - VREF -0.15 V 2 VICK (DC) -0.3 - VDDQ +0.3 V 16 VID (DC) 0.36 - VDDQ +0.6 V 14, 16 Input High Voltage (AC) VIH (AC) VREF +0.31 - - V 2 Input Low Voltage (AC) VIL (AC) - - VREF -0.31 V 2 VID (AC) 0.7 - VDDQ +0.6 V 14, 16 VX (AC) VDDQ/2 -0.2 - VDDQ/2 +0.2 V 13, 16 VISO (AC) VDDQ/2 - 0.2 - VDDQ/2 +0.2 V 15, 16 PARAMETER SYMBOL MIN. TYP. Power Supply Voltage VDD 2.4 Power Supply Voltage (for I/O Buffer) VDDQ 2.4 Input Reference Voltage VREF Termination Voltage (System) Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK inputs (DC) Input Differential Voltage. CLK and CLK inputs (AC) Differential AC input Cross Point Voltage Differential Clock AC Middle Point Note: Undershoot limit: VIL(min.) = -0.9V with a pulse width < 5 nS Overshoot limit: VIH(max.) = VDDQ +0.9V with a pulse width < 5 nS VIH(DC) and VIL(DC) are levels to maintain the current logic state, VIH(AC) and VIL(AC) are levels to change to the new logic state. -5- Publication Release Date: March 15, 2002 Revision A1 W9425GBDA-6 9. CAPACITANCE (VDD = VDDQ = 2.5V 0.1V, f = 1 MHz, TA = 25 C, VOUT(DC) = VDDQ/2, VOUT(Peak to Peak) = 0.2V) PARAMETER SYMBOL MAX. UNIT Address Input Capacitance (A0 - A12, BA0, BA1) Cadd-IN 24 PF Command Input Capacitance ( RAS , CAS , WE ) CCMD-IN 24 PF CS signals Input Capacitance ( CS0 , CS1 ) CCS-IN 24 PF CKE signal Input Capacitance (CKE0, CKE1) CCKE-IN 24 PF CLK signals Input Capacitance (CLKn, CLKn ) CCLK-IN 12 PF CI/O 5 PF DM/DQS/DQ Input Capacitance (DM0 - DM7, DQS0 - 7, DQ0 - 63) MIN. 10. DC CHARACTERISTICS PARAMETER SYM. MAX. UNIT NOTES -6 OPERATING CURRENT: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle IDD0 1240 7 OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 2.5; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. IDD1 1240 7, 9 PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM IDD2P 32 IDLE FLOATING STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM IDD2F 720 7 IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM IDD2N 720 7 IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and DM IDD2Q 640 ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min IDD3P 320 ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One Bank ActivePrecharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 920 7 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK min; IOUT = 0 mA IDD4R 1710 7, 9 OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle IDD4W 1710 7 AUTO REFRESH CURRENT: tRC = tRFC min IDD5 1880 7 SELF REFRESH CURRENT: CKE < 0.2V IDD6 48 RANDOM READ CURRENT: 4 Banks Active Read with activate every 20 nS, AutoPrecharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0 mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle IDD7 2520 -2- mA 7 W9425GBDA-6 11. AC CHARACTERISTICS OF SDRAM COMPONENTS (Notes: 10, 12) SYMBOL tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK tAC PARAMETER -6 Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto Precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto Precharge Write Recovery + Precharge Time CLK Cycle Time CL = 2.5 0.7 0.6 Data Access Time from CLK, CLK -0.7 tDQSCK DQS Output Access Time from CLK, CLK -0.6 tDQSQ tCH tCL tHP Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREF tMRD UNITS MIN. 60 72 42 15 15 1 18 12 15 30 6 NOTES MAX. 100000 nS tCK 15 nS 16 DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition UDQS - LDQS Skew (x 16) Input Setup Time Input Hold Time Control & Address Input Pulse Width (for each input) 0.45 0.45 Min. (tCL,tCH) tHP -0.55 0.9 0.4 0.45 0.45 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.75 0.75 2.2 0.45 0.55 0.55 1.1 0.6 tCK 11 nS tCK 11 nS 0.6 1.25 0.25 -0.7 0.7 Data-out Low-impedance Time from CLK, CLK -0.7 0.7 SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to Non-read Command Exit Self Refresh to Read Command Refresh Time (8K) Mode Register Set Cycle Time 0.5 1 75 10 1.5 64 -7- 11 nS Data-out High-impedance Time from CLK, CLK 12 tCK tCK 11 nS tCK nS tCK mS nS Publication Release Date: March 15, 2002 Revision A1 W9425GBDA-6 12. AC TEST CONDITION OF SDRAM COMPONENTS PARAMETER SYMBOL VALUE UNIT Input High Voltage (AC) VIH VREF +0.31 V Input Low Voltage (AC) VIL VREF -0.31 V Input Reference Voltage VREF 0.5 x VDDQ V VTT 0.5 x VDDQ V VSWING 1.0 V VR Vx (AC) V VID(AC) 1.5 V Input Signal Minimum Slew Rate SLEW 1.0 V/nS Output Timing Measurement Reference Voltage VOTR 0.5 x VDDQ V Termination Voltage Input Signal Peak to Peak Swing Differential Clock Input Reference Voltage Input Difference Voltage. CLK and CLK Inputs (AC) VDDQ VTT VIH min (AC) V SWING (MAX) VREF RT= 50 ohms VIL max (AC) VSS output T Z = 50 ohms T 30pF SLEW = (VIH min (AC) - VILmax (AC)) / T A.C. TEST LOAD (A) Notes: (1) Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage device. to the (2) All voltages are referenced to VSS, VSSQ. (3) Peak to peak AC noise on VREF may not exceed 2% of VREF(DC). (4) VOH = 1.95V,VOL=0.35V (5) VOH = 1.9V,VOL=0.4V (6) The values of IOH(DC) is based on VDDQ=2.4V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.4V and VTT = 1.11V. (7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. (8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. -2- W9425GBDA-6 (9) These parameters depend on the output loading. Specified values are obtained with the output open. (10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope. (11) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. i.e., tDQSS = 0.75xtCK, tCK = 7.5 ns, 0.75 x 7.5 ns = 5.625 ns is rounded up to 5.6 ns. (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK) + VICK( CLK )}/2. (15) Refer to the figure below. (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. CLK VX VX VX VICK VX VICK VX VID(AC) CLK VICK VICK VSS VID(AC) 0 V Differential VISO VISO(min) VISO(max) VSS (17) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. -9- Publication Release Date: March 15, 2002 Revision A1 W9425GBDA-6 13. OPERATION MODES The following Simplified Truth Table illustrates the operation modes of DDR SDRAM. For more detailed information please refer to the DDR SDRAM datasheet. Simplified Truth Table DEVICE STATE CKEN-1 CKEN DMN BS0, BS1 A10 A12, A11, A9-A0 Bank Active Idle H X X V V Bank Precharge Any H X X V L COMMAND Precharge All CS RAS CAS WE V L L H H X L L H L Any H X X X H X L L H L Active(3) H X X V L V L H L L Write with Autoprecharge Active (3) H X X V H V L H L L Read Active(3) H X X V L V L H L H Read with Autoprecharge Active(3) H X X V H V L H L H Mode Register Set Idle H X X L, L C C L L L L Extended Mode Register Set Idle H X X H, L V V L L L L No Operation Any H X X X X X L H H H Burst Read Stop Active H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto Refresh Idle H H X X X X L L L H Write Self Refresh Entry Idle H L X X X X L L L H Idle (Self Refresh) L H X X X X H X X X L H H X Idle/ Active(5) H Any (Power Down) L Data Write Enable Active H X L X X Data Write Disable Active H X H X X Self Refresh Exit Power Down Mode Entry Power Down Mode Exit L X H X X X Notes: 1. V = Valid X = Don't Care L = Low level H = High level 2. CKEn signal is input level when commands are issued. 3. CKEn-1 signal is input level one clock cycle before the commands are issued. 4. These are state designated by the BS0, BS1 signals. 5. Power Down Mode can not entry in the burst cycle. -2- X X X X H X X X L H H X H X X X L H H X X X X X X X X X X X W9425GBDA-6 14. SERIAL PRESENCE DETECT EEPROM The Serial Presence Detect (SPD) function is implemented by using a 2,408-bit EEPROM component. This nonvolatile storage device contains those data for identifying the module type and various SDRAM organizations and timing parameters. System read operations to the EEPROM device occur using the DIMM SCL(clock) and SDA (data) signals, together with SA(2:0) which provide the EEPROM Device Address. SPD EEPROM DC Operating Conditions (Vcc = 2.3V - 3.6V) PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs Output Low Voltage, lout = 3 mA Input Leakage Current, VIN = GND to VCC Output Leakage Current, VOUT = GND to VCC Power Supply Current SCL Clock Frequency = 100 KHz SYM. VCC VIH VIL VOL ILI ILO MIN. 2.3 VCC x 0.7 -0.3 ICC MAX. UNIT 3.6 V VCC +0.5 V VCC x 0.3 V 0.4 V 2 uA 2 uA 1 NOTES IOL = 3 mA mA SPD AC Operating Conditions (Vcc = 2.3V - 3.6V) PARAMETER SYM. fSCL tI MIN. MAX. 100 100 UNIT KHz nS SCL Low to SDA Data Out Valid tAA 0.2 3.5 S Time the bus must be free before a new transition can start tBUF 4.7 S tHD:STA 4.0 S Clock Low Period tLOW 4.7 S Clock High Period tHIGH 4.0 S Start Condition Setup Time tSU:STA 4.7 S Data in Hold Time tHD:DAT 0 Data in Setup Time tSU:DAT 250 S nS SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs Start Condition Hold Time SDA and SCL Rise time tR 1 SDA and SCL Fall Time tF 300 S nS 10 S nS mS Stop Condition Setup Time Data Out Hold Time Write Cycle Time tSU:STO 4 tDH tWR 200 Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled, SDA is allowed to remain high the bus level pull-up resistor, and the device does not respond to its slave address. - 11 - Publication Release Date: March 15, 2002 Revision A1 W9425GBDA-6 15. SPD DATA Byte No. FUNCTION SUPPORTED -6 FUNCTION DESCRIBED 16 17 18 19 20 Defines # Bytes Written into Serial Memory at Module Manufacturer Total # Bytes of SPD Memory Device Fundamental Memory Type (FPM, EDO, DRAM..) # Row Addresses on this assembly # Column Addresses on This Assembly # Module Rows on This Assembly Data Width of This Assembly Data Width Continuation Voltage Interface Standard of This Assembly SDRAM Cycle Time @CAS Latency of 2.5 SDRAM Access Time @CAS Latency of 2.5 DIMM Configuration Type (Non-parity, Parity ECC) Refresh Rate/Type SDRAM Width, Primary DRAM Error Checking SDRAM Data Width Minimum Clock Delay, Back Random Column Addresses Burst Lengths Supported #Bank on Each SDRAM Device CAS# Latencies Supported CS# Latency Write Latency 21 SDRAM Module Attributes 22 SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 SDRAM Cycle Time @ CAS Latency of 2 SDRAM Access Time @CAS Latency of 2 SDRAM Cycle Time @ CAS Latency of 1.5 SDRAM Access Time @CAS Latency of 1.5 Precharge to Active Command Period (tRP) Active to Active Command Period (tRRD) Active to Read/Write Command Delay Time (tRCD) Minimum Active to Precharge Period (tRAS) Density of each Row on Module Command and Address Signal Input Setup Time Command and Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 36 - 61 62 128 bytes 80h 256 bytes (2K-bit) DDR SDRAM 13 10 1 row 64 bits SSTL 2.5V 6 nS +/-0.7 nS Non parity 7.8 us, support self refresh X8 None 08h 07h 0Dh 0Ah 01h 40h 00h 04h 60h 70h 00h 82h 08h 00h TCCD = 1 CLK 01h 2, 4, 8 4 banks 2.5 0 CLK 1 CLK Differential Clock, Non-buffered Non-registered & redundant addressing 2.5V+/-10% voltage tolerance, Burst Read, Write, precharge all, auto precharge 7.5 nS +/-0.7 nS 18 nS 12 nS 18 nS 42 nS Each row of 256 MB 0.75 nS 0.75 nS 0.45 nS 0.45 nS 0Eh 04h 08h 01h 02h Initial release revision 00h 00h Superset Information (may be used in future) SPD Data Specification Revision 63 Checksum for Bytes 0 - 62 64 - 128 Unused Storage Locations - - - -2- HEX VALUE -6 20h 00h 75h 70h 00h 00h 48h 30h 48h 2Ah 40h 75h 75h 45h 45h 06h 00h W9425GBDA-6 16. LABELING INFORMATION There is a product description sticker stuck on each module to fully describe the information of the module. The following are examples of the product description sticker. Examples: MODULE P/N EXAMPLE OF STICKER W9425GBDA-6 W9425GBDA-6 256MB DDR333/CL2.5 DIMM (DDR333/CL2.5 DIMM) TAIWAN 126K264896 The content of this product description sticker is described as below: 1. MODULE PART NUMBER W9425GBDA-6/-7/-75/-8 DIMM Module Part Number Informatoin W94 25 G B D A -6/-7/-75/-8 Speed Grade -6: DDR333/CL2.5 -7: DDR266/CL2 -75: DDR266/CL2.5 -8: DDR200/CL2 Winbond Product Line W94: DDR SDRAM Memory Size 25: 256Mbytes Module Version A: A Version DDR SDRAM Type G: 32M x 8 Module Type D: Unbuffered DIMM DDR SDRAM Version B: B Version 2. Total Memory Size: 256 Mbytes 3. Compliant Industry Spec: DDR333/CL2.5 4. Module Type: DIMM 5. Manufacturing Location: TAIWAN 6. Tracking Number: 926K264896 (The number "926K264896" is for reference only. It is changed according to assembly date, assembly site, and serial lot number.) - 13 - Publication Release Date: March 15, 2002 Revision A1 W9425GBDA-6 17. PACKAGE DIMENSION Units:Inches Front View 0.394 SPD 0.157 5.25 1.250 0.70 0.098 Rear View 0.125 Max 0.050 .004 Tolerances: .005 unless othrerwise specified Component P/N: W942508BH-6 (32M X 8 DDR-SDRAM,TSOP-66) -2- W9425GBDA-6 Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 15 - Publication Release Date: March 15, 2002 Revision A1