W9425GBDA-6
256MB (32M
×
64) DDR SDRAM DIMM
Publication Release Date: March 15, 2002
- 1 - Revision A1
1. GENERAL DESCRIPTION
The W9425GBDA is a 256MB Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) memory
modules. It is organized in a 32M x 64 bit configuration using eight pieces of Winbond W942508BH
(32M x 8 bits) DDR SDRAMs and assembled on a JEDEC standard 184-pin DIMM PCB.
To provide high data bandwidth, W9425GBDA uses a double data rate architecture to transfer two
data words per clock cycle and delivers a data bandwidth of up to 2.7G (DDR333) bytes per second. It
is ideal for high performance systems that require fast data transfer memory modules.
By reading the Serial Presence-Detect (SPD), the system can identify the module type, DDR SDRAM
timing parameters and other necessary information to optimize system setting and maximize its
performance.
2. FEATURES
• JEDEC standard 184-pin, Dual In-Line Memory Module (DIMM)
• Comply to DDR333 specification
• Differential clock inputs (CLK and CLK )
• Double Data Rate architecture, two data transfers per clock cycle
• CAS Latency: 2.5
• Burst Lengths: 2, 4, 8
• Auto Refresh and Self Refresh
• 8K refresh cycles / 64 mS
• Serial Presence Detect with EEPROM
• Interface: SSTL-2
• Power supply: 2.5V ±0.1V
• PCB height: 1.25 inches
3. AVAILABLE PART NUMBERS
MODULE PART NUMBER SPEED
W9425GBDA-6 DDR333/CL2.5
W9425GBDA-6
- 2 -
4. PIN ASSIGNMENT
PIN
FONT PIN
FONT PIN
FONT PIN
BACK PIN
BACK PIN
BACK
1 VREF 32 A5 62 VDDQ 93 VSS 124
VSS 154
RAS
2 DQ0 33 DQ24 63 WE 94 DQ4 125
A6 155
DQ45
3 VSS 34 VSS 64 DQ41 95 DQ5 126
DQ28 156
VDDQ
4 DQ1 35 DQ25 65 CAS 96 VDDQ 127
DQ29 157
CS0
5 DQS0 36 DQS3 66 VSS 97 DQS9 128
VDDQ 158
CS1
6 DQ2 37 A4 67 DQS5 98 DQ6 129
DQS12 159
DQS14
7 VDD 38 VDD 68 DQ42 99 DQ7 130
A3 160
VSS
8 DQ3 39 DQ26 69 DQ43 100
VSS 131
DQ30 161
DQ46
9 NC 40 DQ27 70 VDD 101
NC 132
VSS 162
DQ47
10 NC 41 A2 71 *S2 102
NC 133
DQ31 163
*S3
11 VSS 42 VSS 72 DQ48 103
*A13 134
*CB4 164
VDDQ
12 DQ8 43 A1 73 DQ49 104
VDDQ 135
*CB5 165
DQ52
13 DQ9 44 *CB0 74 VSS 105
DQ12 136
VDDQ 166
DQ53
14 DQS1 45 *CB1 75 CLK2 106
DQ13 137
CLK0 167
NC
15 VDDQ 46 VDD 76 CLK2 107
DQS10 138
0CLK 168
VDD
16 CKL1 47 *DQS8 77 VDDQ 108
VDD 139
VSS 169
DQS15
17 CLK1 48 A0 78 DQS6 109
DQ14 140
*DQS17
170
DQ54
18 VSS 49 *CB2 79 DQ50 110
DQ15 141
A10 171
DQ55
19 DQ10 50 VSS 80 DQ51 111
CKE1 142
*CB6 172
VDDQ
20 DQ11 51 *CB3 81 VSS 112
VDDQ 143
VDDQ 173
NC
21 CKE0 52 BA1 82 VDDID 113
*BA2 144
*CB7 174
DQ60
22 VDDQ KEY 83 DQ56 114
DQ20 KEY 175
DQ61
23 DQ16 53 DQ32 84 DQ57 115
A12 145
VSS 176
VSS
24 DQ17 54 VDDQ 85 VDD 116
VSS 146
DQ36 177
DQS16
25 DQS2 55 DQ33 86 DQS7 117
DQ21 147
DQ37 178
DQ62
26 VSS 56 DQS4 87 DQ58 118
A11 148
VDD 179
DQ63
27 A9 57 DQ34 88 DQ59 119
DQS11 149
DQS13 180
VDDQ
28 DQ18 58 VSS 89 VSS 120
VDD 150
DQ38 181
SA0
29 A7 59 BA0 90 WP 121
DQ22 151
DQ39 182
SA1
30 VDDQ 60 DQ35 91 SDA 122
A8 152
VSS 183
SA2
31 DQ19 61 DQ40 92 SCL 123
DQ23 153
DQ44 184
VDDSP
*These pins are not used in this module.
W9425GBDA-6
Publication Release Date: March 15, 2002
- 3 - Revision A1
5. PIN DESCRIPTIONS
PIN NAME FUNCTION DESCRIPTION
CLKn, CLKn Clock Input CLKn and CLKn are differential clock inputs. All input command
signals are sampled at the positive edge of CLK(except for DQ, DM
and CKE).
CSn Chip Select Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
CKEn Clock Enable CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self-Refresh mode is entered.
A0 − A12 Address Multiplexed pins for row and column address.
Row address: A0 − A12. Column address: A0 − A9.
BA0 − BA1 Bank Select
Address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row Address
Strobe Command input. When sampled at the rising edge of the clock, RAS ,
CAS and WE define the operation to be executed.
CAS Column
Address Strobe
Referred to RAS
WE Write Enable Referred to RAS
DM0 − DM7 Input/Output
Mask The output buffer is placed at Hi-Z when DM is sampled high in read
cycle. In write cycle, sampling DM high will block the write data.
DQ0 − DQ63 Data
Input/Output Multiplexed pins for data output and input
DQS0 − DQS7 Data Strobe
Input/Output Output with read data, input with write data. DQS is edge-aligned with
read data, centered in write data.
VDD Power (+2.5V) Power supply (2.5V).
VSS Ground Ground
VREF Reference
Voltage SSTL-2 Reference voltage
VDDSPD SPD Power Separated power supply for SPD EEPROM (2.3V − 3.6V)
SCL Serial Clock Clock for serial presence detection
SDA Serial Data I/O Data line for serial presence detection
SAn SPD Address
Line System assigned address (SA0 − SA2) to identify different memory
module in a system board.
NC No Connection No connection
W9425GBDA-6
- 2 -
6. BLOCK DIAGRAM
A0 ~ A13, BA0 & 1 SDRAMs U0 ~ U7
RAS
CAS
WE
SDRAMs U0 ~ U7
SDRAMs U0 ~ U7
SDRAMs U0 ~ U7
SDA
SCL U7
A0 A1 A2
SERIAL PD
SA0 SA1 SA2
WP
SDA
CS0
DM4/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
U4
CS
DQS4
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM5/DQS14
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
U5
CS
DQS5
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM6/DQS15
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
U6
CS
DQS6
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM7/DQS16
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
U7
CS
DQS7
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0/DQS9
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
U0
CS
DQS0
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1/DQS10
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
U1
CS
DQS1
DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM2/DQS11
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
U4
CS
DQS2
DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3/DQS12
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
U3
CS
DQS3
DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
V
DDID
V
DD
SPD
V
DD
/V
DDQ
V
REF
V
SS
SPD
D0~D7
D0~D7
D0~D7
W9425GBDA-6
Publication Release Date: March 15, 2002
- 5 - Revision A1
7. ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTES
Input, Output Voltage VIN, VOUT -0.3 − VDDQ +0.3 V 1
Power Supply Voltage VDD, VDDQ -0.3 − 3.6 V 1
Operating Temperature TOPR 0 − 70 °C 1
Storage Temperature TSTG -55 − 150 °C 1
Soldering Temperature (10s) TSOLDER 260 °C 1
Power Dissipation for Each Component PD 8 W 1
Short Circuit Output Current IOUT 50 mA 1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8. RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to 70 °C)
PARAMETER SYMBOL
MIN. TYP. MAX. UNIT
NOTES
Power Supply Voltage VDD 2.4 2.5 2.6 V 2
Power Supply Voltage (for I/O Buffer) VDDQ 2.4 2.5 VDD V 2
Input Reference Voltage VREF 0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V 2, 3
Termination Voltage (System) VTT VREF -0.04 VREF VREF +0.04 V 2
Input High Voltage (DC) VIH (DC) VREF +0.15 - VDDQ +0.3 V 2
Input Low Voltage (DC) VIL (DC) -0.3 - VREF -0.15 V 2
Differential Clock DC Input Voltage VICK (DC) -0.3 - VDDQ +0.3 V 16
Input Differential Voltage. CLK and
CLK inputs (DC) VID (DC) 0.36 - VDDQ +0.6 V 14, 16
Input High Voltage (AC) VIH (AC) VREF +0.31 - - V 2
Input Low Voltage (AC) VIL (AC) - - VREF -0.31 V 2
Input Differential Voltage. CLK and
CLK inputs (AC) VID (AC) 0.7 - VDDQ +0.6 V 14, 16
Differential AC input Cross Point
Voltage VX (AC) VDDQ/2 -0.2
- VDDQ/2 +0.2
V 13, 16
Differential Clock AC Middle Point VISO (AC) VDDQ/2 - 0.2
- VDDQ/2 +0.2
V 15, 16
Note: Undershoot limit: VIL(min.) = -0.9V with a pulse width < 5 nS
Overshoot limit: VIH(max.) = VDDQ +0.9V with a pulse width < 5 nS
VIH(DC) and VIL(DC) are levels to maintain the current logic state, VIH(AC) and VIL(AC) are levels to change to the new logic
state.
W9425GBDA-6
- 2 -
9. CAPACITANCE
(VDD = VDDQ = 2.5V ±0.1V, f = 1 MHz, TA = 25 °C, VOUT(DC) = VDDQ/2, VOUT(Peak to Peak) = 0.2V)
PARAMETER SYMBOL
MIN. MAX. UNIT
Address Input Capacitance (A0 − A12, BA0, BA1) Cadd-IN 24 PF
Command Input Capacitance (RAS , CAS , WE ) CCMD-IN 24 PF
CS signals Input Capacitance (CS0 , CS1) CCS-IN 24 PF
CKE signal Input Capacitance (CKE0, CKE1) CCKE-IN 24 PF
CLK signals Input Capacitance (CLKn, CLKn ) CCLK-IN 12 PF
DM/DQS/DQ Input Capacitance (DM0 − DM7, DQS0 − 7, DQ0 − 63)
CI/O 5 PF
10. DC CHARACTERISTICS
MAX.
UNIT
NOTES
PARAMETER SYM.
-6
OPERATING CURRENT: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs
changing once per clock cycle IDD0 1240
7
OPERATING CURRENT: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC
min; CL = 2.5; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once
per clock cycle. IDD1 1240
7, 9
PRECHARGE-POWER-DOWN STANDBY CURRENT: All Banks Idle; Power down
mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM IDD2P 32
IDLE FLOATING STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH
min; Address and other control inputs changing once per clock cycle; VIN = VREF for
DQ, DQS and DM IDD2F 720 7
IDLE STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK
min; Address and other control inputs changing once per clock cycle; Vin > VIH min
or Vin < VIL max for DQ, DQS and DM IDD2N 720 7
IDLE QUIET STANDBY CURRENT: CS > VIH min; All Banks Idle; CKE > VIH min;
tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and
DM IDD2Q 640 mA
7
ACTIVE POWER-DOWN STANDBY CURRENT: One Bank Active; Power down
mode; CKE < VIL max; tCK = tCK min IDD3P 320
ACTIVE STANDBY CURRENT: CS > VIH min; CKE > VIH min; One Bank Active-
Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice
per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 920 7
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK min;
IOUT = 0 mA IDD4R 1710
7, 9
OPERATING CURRENT: Burst = 2; Write; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle; CL = 2.5; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle IDD4W 1710
7
AUTO REFRESH CURRENT: tRC = tRFC min IDD5 1880
7
SELF REFRESH CURRENT: CKE < 0.2V IDD6 48
RANDOM READ CURRENT: 4 Banks Active Read with activate every 20 nS, Auto-
Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0 mA; DQ, DM and DQS
inputs changing twice per clock cycle; Address changing once per clock cycle IDD7 2520
W9425GBDA-6
Publication Release Date: March 15, 2002
- 7 - Revision A1
11. AC CHARACTERISTICS OF SDRAM COMPONENTS (Notes: 10, 12)
SYMBOL PARAMETER -6 UNITS NOTES
MIN. MAX.
tRC Active to Ref/Active Command Period 60
tRFC Ref to Ref/Active Command Period 72
tRAS Active to Precharge Command Period 42 100000
tRCD Active to Read/Write Command Delay Time 15
tRAP Active to Read with Auto Precharge Enable 15
nS
tCCD Read/Write(a) to Read/Write(b) Command Period 1 tCK
tRP Precharge to Active Command Period 18
tRRD Active(a) to Active(b) Command Period 12
tWR Write Recovery Time 15
tDAL Auto Precharge Write Recovery + Precharge Time 30
tCK CLK Cycle Time CL = 2.5
6 15
tAC Data Access Time from CLK, CLK -0.7 0.7
tDQSCK DQS Output Access Time from CLK, CLK -0.6 0.6 16
tDQSQ Data Strobe Edge to Output Data Edge Skew 0.45
nS
tCH CLk High Level Width 0.45 0.55
tCL CLK Low Level Width 0.45 0.55 tCK 11
tHP CLK Half Period (minimum of actual tCH, tCL) Min.
(tCL,tCH)
tQH DQ Output Data Hold Time from DQS tHP -0.55 nS
tRPRE DQS Read Preamble Time 0.9 1.1
tRPST DQS Read Postamble Time 0.4 0.6 tCK 11
tDS DQ and DM Setup Time 0.45
tDH DQ and DM Hold Time 0.45
tDIPW DQ and DM Input Pulse Width (for each input) 1.75 nS
tDQSH DQS Input High Pulse Width 0.35
tDQSL DQS Input Low Pulse Width 0.35
tDSS DQS Falling Edge to CLK Setup Time 0.2
tDSH DQS Falling Edge Hold Time from CLK 0.2
tCK 11
tWPRES Clock to DQS Write Preamble Set-up Time 0 nS
tWPRE DQS Write Preamble Time 0.25
tWPST DQS Write Postamble Time 0.4 0.6
tDQSS Write Command to First DQS Latching Transition 0.75 1.25 11
tDSSK UDQS – LDQS Skew (x 16) -0.25 0.25
tCK
tIS Input Setup Time 0.75
tIH Input Hold Time 0.75
tIPW Control & Address Input Pulse Width (for each input) 2.2
tHZ Data-out High-impedance Time from CLK,CLK -0.7 0.7
tLZ Data-out Low-impedance Time from CLK,CLK -0.7 0.7
tT(SS) SSTL Input Transition 0.5 1.5
nS
tWTR Internal Write to Read Command Delay 1 tCK
tXSNR Exit Self Refresh to Non-read Command 75 nS
tXSRD Exit Self Refresh to Read Command 10 tCK
tREF Refresh Time (8K) 64 mS
tMRD Mode Register Set Cycle Time 12 nS
W9425GBDA-6
- 2 -
12. AC TEST CONDITION OF SDRAM COMPONENTS
PARAMETER SYMBOL VALUE UNIT
Input High Voltage (AC) VIH VREF +0.31 V
Input Low Voltage (AC) VIL VREF -0.31 V
Input Reference Voltage VREF 0.5 x VDDQ V
Termination Voltage VTT 0.5 x VDDQ V
Input Signal Peak to Peak Swing VSWING 1.0 V
Differential Clock Input Reference Voltage VR Vx (AC) V
Input Difference Voltage. CLK and CLK Inputs (AC) VID(AC) 1.5 V
Input Signal Minimum Slew Rate SLEW 1.0 V/nS
Output Timing Measurement Reference Voltage VOTR 0.5 x VDDQ V
V
SWING (MAX)
V
DD
Q
V
SS
TT
V
IH
min (AC)
V
REF
V
IL
max (AC)
SLEW = (V
IH
min (AC) - V
IL
max (AC)) / T
RT= 50 ohms
VTT
A.C. TEST LOAD (A)
Z = 50 ohms
output 30pF
Notes:
(1) Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the
device.
(2) All voltages are referenced to VSS, VSSQ.
(3) Peak to peak AC noise on VREF may not exceed ±2% of VREF(DC).
(4) VOH = 1.95V,VOL=0.35V
(5) VOH = 1.9V,VOL=0.4V
(6) The values of IOH(DC) is based on VDDQ=2.4V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.4V and VTT
= 1.11V.
(7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values
of tCK and tRC.
(8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF and must track variations in the DC level of VREF.
W9425GBDA-6
Publication Release Date: March 15, 2002
- 9 - Revision A1
(9) These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed
slope.
(11) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to
the nearest decimal place. i.e., tDQSS = 0.75×tCK, tCK = 7.5 ns, 0.75 × 7.5 ns = 5.625 ns is rounded up to 5.6 ns.
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK) + VICK(CLK )}/2.
(15) Refer to the figure below.
(16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
CLK
CLK
VSS
V
ICK
V
X
V
X
V
X
V
X
V
X
V
ICK
V
ICK
V
ICK
V
ID(AC)
V
ID(AC)
0 V Differential
V
ISO
V
ISO(min)
V
ISO(max)
V
SS
(17) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock.
W9425GBDA-6
- 2 -
13. OPERATION MODES
The following Simplified Truth Table illustrates the operation modes of DDR SDRAM. For more
detailed information please refer to the DDR SDRAM datasheet.
Simplified Truth Table
COMMAND DEVICE
STATE CKEN-1
CKEN
DMN
BS0,
BS1
A10
A12,
A11,
A9-A0
CS
RAS
CAS
WE
Bank Active Idle H X X V V V L L H H
Bank Precharge Any H X X V L X L L H L
Precharge All Any H X X X H X L L H L
Write Active(3) H X X V L V L H L L
Write with Autoprecharge Active(3) H X X V H V L H L L
Read Active(3) H X X V L V L H L H
Read with Autoprecharge Active(3) H X X V H V L H L H
Mode Register Set Idle H X X L, L
C C L L L L
Extended Mode Register
Set Idle H X X H, L
V V L L L L
No Operation Any H X X X X X L H H H
Burst Read Stop Active H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
Auto Refresh Idle H H X X X X L L L H
Self Refresh Entry Idle H L X X X X L L L H
H X X X Self Refresh Exit Idle (Self
Refresh) L H X X X X
L H H X
H X X X Power Down Mode Entry Idle/
Active(5) H L X X X X
L H H X
H X X X Power Down Mode Exit Any
(Power
Down)
L H X X X X
L H H X
Data Write Enable Active H X L X X X X X X X
Data Write Disable Active H X H X X X X X X X
Notes:
1. V = Valid X = Don’t Care L = Low level H = High level
2. CKEn signal is input level when commands are issued.
3. CKEn-1 signal is input level one clock cycle before the commands are issued.
4. These are state designated by the BS0, BS1 signals.
5. Power Down Mode can not entry in the burst cycle.
W9425GBDA-6
Publication Release Date: March 15, 2002
- 11 - Revision A1
14. SERIAL PRESENCE DETECT EEPROM
The Serial Presence Detect (SPD) function is implemented by using a 2,408-bit EEPROM component.
This nonvolatile storage device contains those data for identifying the module type and various
SDRAM organizations and timing parameters. System read operations to the EEPROM device occur
using the DIMM SCL(clock) and SDA (data) signals, together with SA(2:0) which provide the
EEPROM Device Address.
SPD EEPROM DC Operating Conditions
(Vcc = 2.3V − 3.6V)
PARAMETER/CONDITION
SYM.
MIN.
MAX.
UNIT
NOTES
Supply Voltage VCC 2.3 3.6 V
Input High (Logic 1) Voltage, all inputs VIH VCC x 0.7
VCC +0.5
V
Input Low (Logic 0) Voltage, all inputs VIL -0.3 VCC x 0.3
V
Output Low Voltage, lout = 3 mA VOL 0.4 V IOL = 3 mA
Input Leakage Current, VIN = GND to VCC ILI 2 uA
Output Leakage Current, VOUT = GND to VCC
ILO 2 uA
Power Supply Current
SCL Clock Frequency = 100 KHz ICC 1 mA
SPD AC Operating Conditions
(Vcc = 2.3V − 3.6V)
PARAMETER
SYM.
MIN.
MAX.
UNIT
SCL Clock Frequency fSCL 100 KHz
Noise Suppression Time Constant at SCL, SDA Inputs tI 100 nS
SCL Low to SDA Data Out Valid tAA 0.2 3.5
µS
Time the bus must be free before a new transition can start
tBUF 4.7
µS
Start Condition Hold Time tHD:STA 4.0
µS
Clock Low Period tLOW 4.7
µS
Clock High Period tHIGH 4.0
µS
Start Condition Setup Time tSU:STA 4.7
µS
Data in Hold Time tHD:DAT 0
µS
Data in Setup Time tSU:DAT 250 nS
SDA and SCL Rise time tR 1
µS
SDA and SCL Fall Time tF 300 nS
Stop Condition Setup Time tSU:STO 4
µS
Data Out Hold Time tDH 200 nS
Write Cycle Time tWR 10 mS
Note: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled, SDA is allowed to remain
high the bus level pull-up resistor, and the device does not respond to its slave address.
W9425GBDA-6
- 2 -
15. SPD DATA
FUNCTION SUPPORTED
HEX VALUE
Byte
No. FUNCTION DESCRIBED -6 -6
0 Defines # Bytes Written into Serial Memory at Module
Manufacturer 128 bytes 80h
1 Total # Bytes of SPD Memory Device 256 bytes (2K-bit) 08h
2 Fundamental Memory Type (FPM, EDO, DRAM..) DDR SDRAM 07h
3 # Row Addresses on this assembly 13 0Dh
4 # Column Addresses on This Assembly 10 0Ah
5 # Module Rows on This Assembly 1 row 01h
6 Data Width of This Assembly 64 bits 40h
7 Data Width Continuation - 00h
8 Voltage Interface Standard of This Assembly SSTL 2.5V 04h
9 SDRAM Cycle Time @CAS Latency of 2.5 6 nS 60h
10 SDRAM Access Time @CAS Latency of 2.5 +/-0.7 nS 70h
11 DIMM Configuration Type (Non-parity, Parity ECC) Non parity 00h
12 Refresh Rate/Type 7.8 us, support self refresh 82h
13 SDRAM Width, Primary DRAM X 8 08h
14 Error Checking SDRAM Data Width None 00h
15 Minimum Clock Delay, Back Random Column
Addresses TCCD = 1 CLK 01h
16 Burst Lengths Supported 2, 4, 8 0Eh
17 #Bank on Each SDRAM Device 4 banks 04h
18 CAS# Latencies Supported 2.5 08h
19 CS# Latency 0 CLK 01h
20 Write Latency 1 CLK 02h
21 SDRAM Module Attributes Differential Clock, Non-buffered
Non–registered & redundant
addressing 20h
22 SDRAM Device Attributes: General 2.5V+/-10% voltage tolerance,
Burst Read, Write, precharge all,
auto precharge 00h
23 SDRAM Cycle Time @ CAS Latency of 2 7.5 nS 75h
24 SDRAM Access Time @CAS Latency of 2 +/-0.7 nS 70h
25 SDRAM Cycle Time @ CAS Latency of 1.5 - 00h
26 SDRAM Access Time @CAS Latency of 1.5 - 00h
27 Precharge to Active Command Period (t
RP
) 18 nS 48h
28 Active to Active Command Period (t
RRD
) 12 nS 30h
29 Active to Read/Write Command Delay Time (t
RCD
) 18 nS 48h
30 Minimum Active to Precharge Period (t
RAS
) 42 nS 2Ah
31 Density of each Row on Module Each row of 256 MB 40h
32 Command and Address Signal Input Setup Time 0.75 nS 75h
33 Command and Address Signal Input Hold Time 0.75 nS 75h
34 Data Signal Input Setup Time 0.45 nS 45h
35 Data Signal Input Hold Time 0.45 nS 45h
36 − 61 Superset Information (may be used in future) - 00h
62 SPD Data Specification Revision Initial release revision 00h
63 Checksum for Bytes 0 − 62 - - - 06h
64 − 128
Unused Storage Locations - 00h
W9425GBDA-6
Publication Release Date: March 15, 2002
- 13 - Revision A1
16. LABELING INFORMATION
There is a product description sticker stuck on each module to fully describe the information of the
module. The following are examples of the product description sticker.
Examples:
MODULE P/N EXAMPLE OF STICKER
W9425GBDA-6
(DDR333/CL2.5 DIMM)
W9425GBDA-6
256MB DDR333/CL2.5 DIMM
TAIWAN 126K264896
The content of this product description sticker is described as below:
1. MODULE PART NUMBER W9425GBDA-6/-7/-75/-8
DIMM Module Part Number Informatoin
W94
Winbond Product Line
W94:
DDR SDRAM
Memory Size
25:
256Mbytes
DDR SDRAM Type
G:
32M x 8
Speed Grade
-
6
: DDR333/CL2.5
-7:
DDR266/CL2
-75:
DDR266/CL2.5
-8:
DDR200/CL2
Module Version
A:
A Version
Module Type
D:
Unbuffered DIMM
DDR SDRAM Version
B:
B Version
25 GB D A-6/-7/-75/-8
2. Total Memory Size: 256 Mbytes
3. Compliant Industry Spec: DDR333/CL2.5
4. Module Type: DIMM
5. Manufacturing Location: TAIWAN
6. Tracking Number: 926K264896
(The number “926K264896” is for reference only. It is changed according to assembly
date, assembly site, and serial lot number.)
W9425GBDA-6
- 2 -
17. PACKAGE DIMENSION
0.394
1.250
0.70 0.157
0.098
5.25
Units:Inches
Tolerances: .005 unless othrerwise specified
Component P/N: W942508BH-6 (32M X 8 DDR-SDRAM,TSOP-66)
Front View
Rear View
0.125 Max
0.050 .004
SPD
W9425GBDA-6
Publication Release Date: March 15, 2002
- 15 - Revision A1
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.
