ANALOG DEVICES High Speed 8-Bit Monolithic A/D Converter ADS002 FEATURES 150MSPS Encode Rate Low Input Capacitance: 17pF Low Power: 750mW -5.2V Single Supply MIL-STD-883 Compliant Versions Available APPLICATIONS Radar Systems Digital Oscilloscopes/ATE Equipment Laser/Radar Warning Receivers Digital Radio Electronic Warfare (ECM, ECCM, ESM) Communication/Signal intelligence GENERAL DESCRIPTION The AD9002 is an 8-bit, high speed, analog-to-digital converter. The AD9002 is fabricated in an advanced bipolar process which allows operation at sampling rates in excess of 150 megasamples/ second. Functionally, the AD9002 is comprised of 256 parallel comparator stages whose outputs are decoded to drive the ECL compatible output latches. An exceptionally wide large signal analog input bandwidth of 160MHz is due to an innovative comparator design and very close attention to device layout considerations. The wide input bandwidth of the AD9002 allows very accurate acquisition of high speed pulse inputs, without an external track-and-hold. The comparator output decoding scheme minimizes false codes which is critical to high speed linearity. The AD9002 provides an external hysteresis control pin which can be used to optimize comparator sensitivity to further improve performance. Additionally, the AD9002s low power dissipation of 750mW makes it usable over the full extended temperature This is an abridged data sheet. To obtain the most recent version or complete data sheet, call our fax retrieval system at 1-800-446-6212. 2-402 ANALOG-TO-DIGITAL CONVERTERS FUNCTIONAL BLOCK DIAGRAM OVERFLOW INHIBIT AD9002 ANALOG IN + Vee OVERFLOW BIT 8 (MSB) D BIT 7 E c 0 BIT 6 1 N G BITS REF Mu BIT 4 BIT BIT2 BIT 1 (LSB) Vaer (tT encooe (7 ENCODE (6 3 GNO HYSTERESIS -Vs range. The AD9002 also incorporates an overflow bit to indicate overrange inputs. This overflow output can be disabled with the overflow inhibit pin. The AD9002 is available in two grades, one with 0.5LSB linearity and one with 0.75LSB linearity. Both versions are offered in an industrial grade, 25C to + 85C, packaged in a 28-pin DIP and a 28-pin JLCC. The military temperature range devices, 35C to + 125C, are available in ceramic DIP and LCC packages and are compliant to MIL-STD-883 Class B. REV. BSPECIFICATIONS AD9002 ABSOLUTE MAXIMUM RATINGS! Supply Voltage (Vs) . . ..... -6V Digital Output Current... 2... eee. 20mA Analog-to-Digital Supply Voltage Differential . . .. 0.5V Operating Temperature Range Analog Input Voltage _Vs5 to +0.5V AD9002AD/BD/AJ/BJ .......... 25C to +85C Digital Input Voltage ................4+. Vs 0 0V AD9002SE/SD/TD/TE .........,. 55 to +125C Reference Input Voltage (+ Vrer Veer)? . ~3.5Vt00.1V Storage Temperature Range cee ee eee 65E to + 150C Differential Reference Voltage .............. 2.1V Junction Temperature? .. . ieee ee ee HITS IC Reference Midpoint Current. . . -.....+4mA Lead Soldering Temperature (10sec) eee ee ee *300C ENCODE to ENCODE Differential Voltage tee ee ee AV Electrical Characteristics (V,= 5.2; Differential Reference Voltage = 2.0V, unless otherwise stated) Test AD9002AD/AJ AD9002BD/B) AD9002SD/SE AD9002TD/TE Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION | 8 8 8 8 Bits DC ACCURACY Differential Linearity ' + 25C | 1 0.6 0.75 0.4 0.5 0.6 0.75 0.4 0.5 LSB ' Full VI 10 0.75 1.0 0.75 LSB Integral Linearity j +25C | I 0.6 1.0 0.4 0.8 0.6 1.0 0.4 0.5 LSB i Full VI 1,2 1,2 1.2 1.2 LSB No Missing Codes "Full VE GUARANTEED GUARANTEED GUARANTEED GUARANTEED INITIAL OFFSET ERROR Top of Reference Ladder +25C | I 8 14 8 M4 8 14 8 14 mV Full VI 17 17 7 7 m Bottom of Reference Ladder 425C I 4 10 4 10 4 10 4 10 mV Full =, VI 12 12 73 12 mV Offset Drift Coefficient Full Vv 20 20 20 20 nv ANALOG INPUT Input Bias Current +25C | I 60 100 60 100 60 100 60 100 pa Full VI 200 200 200 200 pA input Resistance +25C | Il 100 200 100 200 100 200 100 200 kn Input Capacitance +25C | HE 17 22 17 22 17 22 v7 22 pF Large Signal Bandwidth* +25 | V 160 160 160 160 MHz Input Slew Rate +25C | V 440 440 440 440 Vis REFERENCE INPUT Reference Ladder Resistance +25C | VI 64 80 110 64 30 110 o4 80 110 64 80 Ho n Ladder Temperature Coefficient v 0.25 0.25 0.28 0.2 OPC Reterence Input Bandwidth +28C | V 10 10 10 10 MHz DYNAMIC PERFORMANCE 1 Conversion Rate +28C 1 125 Isa 125 150 125 150 125 150 MSPS Aperture Delay, [ +25C 13 1.3 13 1.3 ns Aperture Uncertainty Jitter! ; 725s ov Is 1s 1S Is Ps Output Delay itpp 425C 1 25 37 5.5 25 3.7 5.5 28 47 5.5 25 3.7 5.8 ns Transient Response +259C OV 6 6 46 6 ns Overvoltage Recovery Time! +29C OV 6 6 4 6 ns Ourput Rise Time? +25C 1 3.0 3.0 3.0 3.0 ns Output Fall Time +259C 2.5 25 2.5 25 ns Output Time Skew ''' +25C V 0.6 0.6 0.6 0.6 ns ENCODE INPUT Logic 1" Voltage Full VI -Hl -11 -tl -tt Vv Logic 0 Voltage Full VI ! -1S 15 -1LS -15] Vv Logic 1 Current Full VI 150 150 150 150 BA Logic 0 Current Fult VI : 120 120 120 120 pA Input Capacitance 2250 | V 3 3 3 3 pF Encode Pulse Width ( Lows? +250 FT 1.5 Ls 1.5 15 ns Encode Pulse Width (High |" +28C | 1 1s 1s Ls 15 ns OVERFLOW INHIBIT INPUT OV Input Current Full VI 144 300 144 300 144 300 144 300 BA AC LINEARITY '* Effective Bits'* 425C | V 7.6 : 76 7.6 76 Bits In-Band Harmonics deta L.23MHz +25C FT 48 55 48 55 48 55 48 55 dB de to 9. 3MHz +28C OV 50 50 50 50 dB de to 19.3MHz +250 OV 44 44 4 44 dB Signal-to-Noise Ratio! 4325C 01 46 47.6 46 47.6 46 47.6 46 47.6 dB two Tone Intermod Rejecuon'" | + 25C | Vv 60 60 60 60 dB DIGITALOUTPUTS Logic 1 Voltage Full VI 7 4a = -11 -11 Vv Logic 0" Voltage Full VI -15 -45 -15 -15 v POWER SUPPLY"? Supply Current( - 5 2V) 425C | I 145 178 145 175. 145 175 145 175 mA Full VI 200 200 200 200 mA Nominal Power Dissipation +29C | Vv 750 750 750 750 mW Reference Ladder Dissipation +25C | V 50 so 50 50 mW Power Supply Rejction Ratio' | +25C | I 08 15 0.8 15 0.8 1s 0.8 LS mv/V REV.B ANALOG-TO-DIGITAL CONVERTERS 2-403ADS002 NOTES Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 4.Vper = Veer under all circumstances. 3Maximuim junction temperature (t; max) should not exceed 175C for ceramic packages, and 150C for plastic packages: ty = PD (64) + ta PD (8jc) + te where PD = power dissipation 8y, = thermal impedance from junction to ambient (C/W) 8; = thermal impedance from junction to case (CW? t, = ambient temperature (C) tc = case temperature (C) typical thermal impedances are: Ceramic DIP @;4 = 56C/W; 8y = 20C/W Plastic DIP @)4 = 60C/W; @; = 20C/W Ceramic LCC 54 = 69C/W; 8) = 23CW PLCC 64 =60C/W, tyc = 19C/W, Recommended Operating Conditions Measured with AIN =0V. 5Measured by FFT analysis where fundamental is ~3dB FS. Input slew rate derived from rise time (10 to 90%) of full scale input. 7Qutputs terminated through 1002 to 2V. 'Measured from ENCODE in to data out for LSB only. *For full-scale step input, 8-bit accuracy is attained in specified time. Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage. "Qurput time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences. ENCODE signal rise/fall times should be less than 10ns for normal operation. Measured at 125MSPS encode rate. Analog input frequency = 1.23MHz. 15RMS signal to rms noise, with 1.23MHz analog input signal. Input signals 1V p-p @1.23MHz and IV p-p @2.30MHz. "Supplies should remain stable within + 5% for normal operation. 'SMeasured at ~5.2V +5%. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level 1 - 100% production tested. Input Voltage Test Level If ~ 100% production tested at + 25C, and sample tested Par + Min Nominal Max at specified temperatures. Test Levell1] - Sample tested only. ~Vs ~ 5.46 ~ 5.20 4.94 Test Level IV - Parameter is guaranteed by design and characteriza- + VREF Veer 0.0V +0.1 tion testing. Veer -2.1 -2.0 + VeEF Test Level V Parameter is atypical value only. Analog Input Veer + Veer TestLevel VI = - = All devices are 100% production tested at + 25C. 100% production tested at temperature extremes for extended temperature devices; sampie tested at temperature extremes for commerciaV/industrial devices. ORDERING GUIDE Package Model Linearity | Temperature Range | Option AD9002AD 0.75LSB 25C to + 85C D-28 AD9002BD 0.50LSB 25C to + 85C D-28 AD9002AJ 0.75LSB 25C to + 85C J-28 AD9002BJ 0.50LSB 25C to + 85C J-28 AD9002SD? 0.75 LSB | 55Cto + 125C D-28 AD9002SE? 0.75LSB | 55Cto +125C E-28A AD9002TD? 0.SO0LSB | 55Cto + 125C D-28 AD9002TE? 0.50LSB | ~55Cto + 125C E-28A NOTES 'D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Leaded Chip Carrier. For outtine information see Package Information section. *MIL-STD-883 versions. 2-404 ANALOG-TO-DIGITAL CONVERTERS REV. BADS002 FUNCTIONAL DESCRIPTION Pin# Name Description 1 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together. 2 OVERFLOW INH OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs. OVERFLOW ENABLED ANALOG (FLOATING OR ~ 5.2V) OVERFLOW INHIBITED (GND) INPUT OF D, D, Ds; Dy D; Dg D; Dg OF D, D, D; Dy Ds Dg Dz Dg Vin > + Veer 1 0 00 00 00 0 0 t 2212 +927 1 7 ~21 Vine + VREF ox xxx X xX x o xX xx XxX Xx x 3 HYSTERESIS The Hysteresis control voltage varies the comparator hysteresis from OmV to 10mV, for a change from 5,2V to ~2.2V at the Hysteresis control pin. Normally connected to 5.2V. 4 + Veer The most positive reference voltage for the internal resistor ladder. 5 ANALOG INPUT One of two analog input pins. Both analog input pins should be connected together. 6 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together. 7 ENCODE Noninverted input of the differential encode input. This pin is driven in conjunction with ENCODE. Data is latched on the rising edge of the ENCODE signal. 8 ENCODE Inverted input of the differential encode input. This pin is driven in conjunction with ENCODE. 9 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together. 10 ANALOG INPUT One of two analog input pins. Both analog inputs should be connected together. 1] VreF The most negative reference voltage for the internal resistor ladder. 12 REF yap The midpoint tap on the internal resistor ladder. 13 DIGITALGROUND One of four digital ground pins. All digital ground pins should be connected together. 14 DIGITAL Vs One of two negative digital supply pins (nominally 5.2V). Both digital supply pins should be connected together. 15 Di Digital data output (LSB). 16-19 D2-D5 Digital data output. 20 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together. 21,22 ANALOG Vs One of two negative analog supply pins (nominally 5.2V). Both analog supply pins should be connected together. 23 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together. 24,25 D6,D7 Digital data ourput. 26 D8 Digital data output (MSB), 27 OVERFLOW Overflow data output. Logic high indicates an input overvoltage (Viy> + Veer) if OVERFLOW INHIBIT is enabled (overflow enabled, 5.2V). See OVERFLOW INHIBIT. 28 DIGITAL Vs One of two negative digital supply pins (nominally 5.2V). Both digital supply pins should be connected together. PIN DESIGNATIONS DIP Lcc JLCC DIGITAL GROUND Cy . [20] DIGITAL - vy a z ; . a i : . z overrtow inn [2 | [27] OVERFLOW 3 g Ss i g zs i e g z z z 3 wesreness [3] pow PEER REE PEERES GS vm [4] 35] 0 13h tes MME ale Fs ANALOG GROUND (J 23 | oiGrrac GaouND AMALOG INPUT 5 280, anacoc ineur [5 | ewcove [7] aps0cz [22] anatoc - vy, Tor viEw ENCODE | w] tWoe to Sco) [21] ANALOG vy, ANALOG GrounD [ 9 ANALOG INPUT | 10 [9] oQ veer [] [18] >. PEF iy [12 [17] 0, DiGiTaL GRoUNO [13 [10] 0 prarrac -v, [14] [re] 0, usar *SEE FUNCTION DESCRIFTIONS REV. B [20] o1GrTaL GrouNo ANALOG GROUND 6 24D, ANALOG GrouNo [6] 21 DIGITAL GROUND 22 ANALOG - 21 ANALOG - V5 ANALOG INPUT 10 20 DIGITAL GROUND wo, Voce 40 188) a 4 s ANALOG-TO-DIGITAL CONVERTERS 2-405 REF ap DIGITAL GROUND &