AX88198 L Fast Ethernet Controller with TCP/IP Stack Local Bus Fast Ethernet Controller with TCP/IP Stack Document No.: AX88198-01/V.01/2003-11-0 Features: z z z z z z z General purpose I/O pins and I2C busses allow controlling hardware simply from network without using a host CPU. Allows adding or changing the protocols used through rewriting of the Flash ROM. Protocol supported ARP, ICMP, IP, TCP, UDP, HTTP, DHCP, TFTP and SNMP. Interface with physical layer Media Independent Interface (Complied with Clause 22 of IEEE802.3) 10BASE-T/Full Duplex, 10BASE-T/Half Duplex and 100BASE-TX/Half Duplex (100BASE-TX/Full Duplex is not supported) Effective transfer rate approximately 2Mbps maximum. Host interface 8/16 bits parallel Directly connectable type Includes SH-3/4, EPSON S1C33, MC68000, MC68030, Philips PR31500/PR31700, Toshiba TX3912, NEC VR4121, PC Card (PCMCIA) and ISA. z z z z z z z z z Endian switching between little and big is possible. Host command system EPSON Standard Code for Network General purpose I/O 16 maximum (Directly controllable from the network. 8 out of 16 are shared with the serial interface.) EEPROM Interface 3-wire and 16-bit Interface compatible with 93C46 (partially usable by user) I2C bus Master Function (Multi-master and 10bit slave supported. Fast/Normal mode.) And slave function contained. Core CPU EPSON S1C33240 50MHz Built-in Flash ROM 128KB (1KBx128 blocks) Power supply 3.3V, 120mA (Max.) Package QFP15-100pin Product description AX88198L is best suited for making your 8/16 bits class CPU-featured equipment connectable to network without using a HIGH performance OS or protocol stacks provided by software vendors .Its capability of internally processing protocols for TCP/IP connection including ARP, ICMP, IP, TCP and UDP. ASIX ELECTRONICS CORPORATION AX88198 L Fast Ethernet Controller with TCP/IP Stack CONTENT 1. Product description............................................................................................................................3 2. System Block Diagram.......................................................................................................................4 3. Pin Description ...................................................................................................................................5 4. Pin Functions......................................................................................................................................6 5. HARDWARE SPECIFICATIONS........................................................................................................14 6. HOST INTERFACE ............................................................................................................................25 7. Built-in Registers..............................................................................................................................27 8. PRECAUTIONS ON IMPLEMENTATION ..........................................................................................48 9. ELECTRIC CHARACTERISTICS ......................................................................................................50 10. PACKAGE........................................................................................................................................62 ASIX ELECTRONICS CORPORATION AX88198 L Fast Ethernet Controller with TCP/IP Stack 1. Product description AX88198L is an intelligent network controller equipped with the built-in protocol processing function. By simplified commands and data from the host CPU (EPSON C33) enables AX88198L to establish TCP/IP communication .Its capability of internally processing protocols for TCP/IP connection including ARP, ICMP, IP, TCP and UDP. MII (Media Independent Interface) is employed for interfacing the physical layer. Just adding PHY chip designed for MII allows you to realize 10BASE-T/100BASE-TX equipment operable on networks. AX88198L is best suited for making your 8/16 bits class CPU-featured equipment connectable to network without using a HIGH performance OS or protocol stacks provided by software vendors. Also, it enables to connect your equipment directly to various types of host CPUs. This data sheet includes hardware and register information only, For "Host interface connection", "Programming guide" and "demo board development kit". Please refer to related application note. ASIX ELECTRONICS CORPORATION AX88198 L Fast Ethernet Controller with TCP/IP Stack 2. System Block Diagram 32bit RISC CPU OSC3 OSC4 PLLC OSCO OSC1 CPU Flash ROM Core 128KB OSC3/PLL Serial / I/O Port SRAM 8KB I/O Port OSC1 Timer DBG (Debug Unit) High-speed DMA OSC2 DSIO DST[2:0] DPCO DCLK GPIO15/DTR# GPIO14/RTS# GPIO13/DSR# GPIO12/CTS# GPIO11/RSV1 GPIO10/MODE GPIO9/TXD GPIO8/RXD GPIO7/OSCCTL GPIO6 GPIO5 GPIO4 GPIO3 GPIO2/CRS GPIO1 GPIO0/INT0 ITC (Interrupt Controller) RESET# HCS# HA[2:0] HRD0# HRD1# HWR0# HWR1# HD[15:0] HINT Host MPU Interface MII Interface MII_RXCLK MII_RXD[3:0] MII_RXDV MII_COL MII_RXER HIFSEL[2:0] HINTPOL HMUX HENDIAN HSIZE SCL SDA EP_CS EP_SK EP_DO EP_DI MII_TXCLK MII_TXD[3:0] MII_TXEN MDC MDIO I2C Bus Master / Slave CRC Generator/ Checker EEPROM Interface VDD VSS TEST[1:0] Control Registers Internal Bus ASIX ELECTRONICS CORPORATION AX88198 L Fast Ethernet Controller with TCP/IP Stack 3. Pin Description 75 51 76 50 AX88198 QFP15-100pin 100 26 INDEX 1 25 5 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 4. Pin Functions 4.1.1 Pin in Power Supply System Pin name VDD VSS Pin No. I/O Function 18,32,44, _ 47,61,79, 90 Built-in logic power supply (+) Power pins. Be sure to supply (3.3V to every pin. 9,25,45,5 2,70,88 Power supply (-) GND Grounding pins. Be sure to ground every pin. __ 4.1.2 Host Interface Signals Pin name HCS# Pin No. 48 HA[2:0] 51,50,49 HD[15:0] 69 to62, 60 to 53 HRD0# 71 HRD1# 72 HWR0# 73 I/O Function Host Chip Select: It is the host interface access control signal. Access to the host interface is enabled as long as this signal remains LOW. This pin has a built-in pull-up resister enabling to accept 5V input. I Host Address: It is the host interface port select signal. It selects the port to be accessed while HCS# = LOW. Following shows the selectable ports. 00x: Command port (write)/Status port (read) 01x: Data port (read/write) 1xx: Flag port (read/write) These pins contain the pull-up resister enabling to accept 5V input. U HA0 is used for switching between the upper and lower bytes when the 8-bit interface is selected. It is disabled when the 16-bit interface is used. Host Data: I/O Data signal line of the host interface. When the 8-bit interface is selected, HDATA [7:0] alone is enabled and HDATA [15:8] is not driven. These pins contain the pull-up resister enabling to accept 5V input. Output is 3.3V CMOS output. I Host Read/Host Write: R/W control signal of the host interface. Function I changes depending on the HIFSEL[2:0] bit status in the I I 6 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack HWR1# 74 HINT 75 HIFSEL[2:0] 83,82,78 HMUX 84 HINTPOL 85 HENDIAN 92 HSIZE 93 HIFCR register. For the detail, refer to "4. Host Interface". I These pins contain the pull-up resister enabling to accept 5V input. Tri Host Interrupt: Interrupt line from AX88198 to the host interface. Causes of interrupts are identifiable from contents of the flag port. Polarity of the interrupt is changeable by changing state of HINTPOL line at the reset. Since this signal is 3.3V/3-state output, be sure to externally connect a pull-up resister when HINTPOL=0 and a pull down resister when HINTPOL=1. I Host Interface Select: It is the host interface type select signal. These pins contain the pull-up resister. For the detail, refer to "4. Host Interface". I Host Bus Multiplex It sets whether the address bus and the data bus of the host interface are multiplexed in time-sharing. In case of multiplex, a latched HD[2:0] is used instead of HA[2:0]. The control line to be used for latching varies with the CPU type selected with HIFSEL. 1:Separate bus, 0:Multiplex bus This pin was not used in our specifications before Rev.1.3 and is set as a separate bus type when nothing is connected to. Connect this pin to GND only when a multiplex bus is used. State of this pin is acquired to the HIFCR register at reset. This pin contains the pull-up resistor. I Host Interrupt Polarity Select: It is the polarity select pin for HRQI and HDVI when they are active. 1:HIGH active, 0:LOW active State of this pin is acquired to HIFCR at reset. This pin contains the pull-up resister. I Host Interface Endian Select: It is the endian type select pin. Appropriately selecting the type for a CPU to be used allows switching the upper and lower data on the command or status port and on the data port. 1:Big Endian, 0:Little Endian State of this pin is acquired to the HIFCR register at reset. This pin contains the pull-up resistor. I Host Bus Size Select: It is the interface size select pin. It is used to specify the data bus size when accessing the port. 1:8bit, 0:16bit State of this pin is acquired to HIFCR at reset. This pin contains the pull-up resister. 7 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 4.1.3 MII Interface Signals Pin No. I/O Function 35 I 40 to 37 I MII_RXDV 36 I MII_TXCLK 33 I 27 to 30 O MII_TXEN 31 O MII_RXER 34 I MII_COL 26 I MDC 41 O MII Receive Clock: Receiving clock entered from PHY chip. It is the reference clock of MII_RXD [3:0], MII_RXDV. Its frequency is 2.5MHz for 10BASE-T and 25MHz for 100BASE-TX. MII Receive Data: Receive data entered from PHY chip. MII Receive Data Valid: Input signal from PHY chip. If it is HIGH at the positive going edge of MII_RXCLK, MII_RXD [3:0] is valid. MII Transmit Clock: Transmit clock entered from PHY chip. It is the reference clock of MII_TXD [3:0], MII_TXEN. Its frequency is 2.5MHz for 10BASE-T and 25MHz for 100BASE-TX. MII Transmit Data: Transmit data output to PHY chip. MII Transmit Enable: Output signal to PHY chip. If it is HIGH at the positive going edge of MII_TXCLK, MII_TXD[3:0] is valid. MII Receive Error: Input signal from PHY chip. This signal indicates that receive data contained an error. It is valid on 100BASE-TX alone and ignored on 10BASE-T. MII Collision Detect: It indicates that collision of signals occurred during Half Duplex communication. MII Management Interface Clock: MDIO 42 GPIO2/CRS 15 Pin name MII_RXCLK MII_RXD[3:0] MII_TXD[3:0] I/O MII Management Interface Data I/O This pin must be connected to a pull-up resister externally. I MII Carrier Sense When the alternate function of GPIO2 is selected, this pin functions as CRS input pin to enter state of the carrier in Half Duplex communication. It is not used when Half Duplex communication is not employed. 8 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 4.1.4 External Device Control Signals Pin name Pin No. EP_CS 19 EP_SK 20 EP_DI 21 EP_DO 22 SCL 23 SDA 24 Function I/O EEPROM Chip Select: It is the EEPROM chip select pin. O EEPROM Serial Clock: It is the EEPROM clock pin. EEPROM Data In: I It is the EEPROM data input pin. O EEPROM Data Out: It is the EEPROM data output pin. 2 OD/I I C Serial Clock: I2C bus serial clock pin. When the master is selected, it is input signal and it becomes output signal when the slave is selected. Since output of this pin is open drain, a pull-up resister must be provided externally. Select an optimum pull-up resister value taking into consideration of load on the bus as well as noises. 2 OD/I I C Serial Data: I2C bus data input/output pin. It is a bi-directional signal used to input or output data and ACK. Since output of this pin is open drain, a pull-up resister must be provided externally. Select an optimum pull-up resister value taking into consideration of load on the bus as well as noises. O 9 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 4.1.5 General Purpose Input and Output Pins Pin name Pin No. I/O GPIO0/INT0 17 I/O GPIO1 16 I/O GPIO2/CRS 15 I/O GPIO3 14 I/O GPIO4 13 I/O GPIO5 12 I/O GPIO6 11 I/O GPIO7/OSCCTL 10 I/O GPIO8/RXD 8 I/O GPIO9/TXD 7 I/O GPIO10/MODE 6 I/O GPIO11/RSV1 5 I/O GPIO12/CTS# 4 I/O GPIO13/DSR# 3 I/O GPIO14/RTS# 2 I/O GPIO15/DTR# 1 I/O Function General Purpose I/O [7:0]: They are general purpose input/output pins. They accept 5V input. GPIO0 is used as an interrupt pin and allows sending interrupt notice to a previously specified destination. GPIO2 is used as the CRS input pin in Half Duplex communication. GPIO7 can be used as the OSC control pin in the sleep mode. For the detail, refer to Chapter 5.3. After the hardware is reset, all pins are used for input only. General Purpose I/O [15:8]: General-purpose input/output pin for 3.3V CMOS level and Schmitt input. They can be used as start-stop synchronous serial terminals by setting GPLLT register. 10 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 4.1.6 Clock Generator Pins Pin name Pin no. I/O Function OSC1 46 I OSC2 43 O OSC3 89 I OSC4 87 O OSC1 clock pin When using the sleep mode in the power management, it is used to connect 32.768kHz crystal. AX88198 in the sleep mode is operated with this clock. When the sleep mode is not used, connect OSC1 to VSS and open OSC2. OSC3 clock pin (for oscillation of crystal/ceramics or for input of external clock) Operating clock oscillation pin for AX88198. A crystal transducer of 10 to 25MHz is connected. When entering an external clock, input a clock of 10 to 25MHz to OSC3 and make OSC4 open. OSCO 94 O OSC output pin It is used to generate buffered output of OSC3 input. Frequency of output from this pin is the same as that OSC3 input. Supplying clock to PHY chip from this pin helps reducing number of oscillators for PHY. PLLC 80 -- PLL capacitor connecting pin It is the capacitor connecting pin for doubling OSC3 frequency with the internal PLL. Be sure to connect R and C shown in Fig.1.3. Unless they are connected, this IC does not operate normally. 11 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack CG2 Crystal2 OSC3 Rf2 OSC4 CD2 CG1 Crystal1 OSC1 Rf1 OSC2 CD1 C2 PLLC R1 Fig.1.3 C1 VSS Clock Generator Connection Diagram Crystal1 Crystal transducer 32.768kHz Ci (Max.) =34k CG1 Gate capacitance 10pF CD1 Drain capacitance 10pF Rf1 Feedback resistance 10M Crystal2 Crystal transducer 25MHz CG2 Gate capacitance 10pF CD2 Drain capacitance 10pF Rf2 Feedback resistance 1M R1 Resister 4.7k C1 Capacitor 100pF C2 Capacitor 5pF 12 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 4.1.7 Other Pins Pin name DSIO DST[2:0] Pin No. 95 98,97,96 DPCO 99 DCLK 100 RESET# 91 TEST1,TEST0 86,81 Reserve 77,76 I/O Function I/O These pins are used for communication with the debug O tool ICD33. ICD33 is mainly use for rewriting flash O memory on AX88198. O It should not be connected to any equipment other than above. I I Hardware Reset Input: AX88198 is reset as the LOW level is input. contains the pull-up resister. This pin Test Input: Testing pins for this IC. They are made open when operated normally. They contain the pull-down resistor. - These pins are reserved for future expansion. Normally, do not connect. Please refer to "AX88198 Technical Information No. 25" for more details about replacement with new mask versions. 13 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 5. HARDWARE SPECIFICATIONS 5.1 Core CPU A 32 bits microcomputer is employed for the core CPU. CPU operating clock, always working identically with the internal bus, is initially set to twice the OSC3. Setting PSEN bit (11 bit) of GENCR register reduces it to 1/4 clock comparing when it operates normally. This arrangement helps reducing operating current. The inside is processed according to Little Endian. 5.2 ROM and Boot Address AX88198 contains a 128Kbytes Flash ROM. After the reset, it is started from 0x0C00000, namely area 10 Flash ROM area. Of these 128Kbytes, 127Kbytes are for the system firmware area, while the remaining 1Kbyte is for the user area. The user area ranges from 0xC1FC00 to 0xC1FFFF. Rewriting in the system firmware is done from the debug serial pin and network by using a special tool and program. To rewrite in the user area, the debug serial pin or host interface can be used. Also, to rewrite in the user area, the debug serial pin or the host interface is used and the host interface command is executed, and it is not necessary to designate an absolute address. However, this area can be used only as a data area. This area cannot store a program for execution. 5.3 RAM AX88198 contains an 8Kbytes RAM. Device size of this built-in RAM is 32 bits enabling to read/write data of a byte, half-word or word in a single cycle. Since this RAM is exclusively used by AX88198, user can't operate it. 5.4 Peripheral Circuits Among the peripheral blocks of the built-in core CPU S1C33240, S1S60000 uses the following built-in peripheral circuits. For details of respective peripheral circuits, refer to "S1C33 Family ASIC Macro Manual". * C33 core block CPU 32-bit RISC type CPU S1C33000 BCU Bus control unit ITC Interrupt controller CLG Clock generator DBG Functional block for debugging featured with ICD33 (In-Circuit Debugger for S1C33 Family) * C33 peripheral circuits block 14 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack Pre-scaler programmable 16 bits programmable timer Serial interface Input/output port Elapsed timer C33DMA block HSDMA (HIGH-speed DMA) Used to set the clock for peripheral circuits 4-channel 5.5 Serial Interface GPIO [15:8] becomes the serial interface pin when the serial interface is in the enabled status and when host interface is set off. The serial interface is enabled when the following two conditions are met: GPALT register bit [15:8] = FFh GENCR register bit [10:8] (SERCONF) = "000" or "010" or "011" The host interface is disabled when the following two conditions are met: HIFSEL[2:0] pin = "LLL" HIFCR register bit [10:8] (HIFSEL) = "111" When the serial interface mode is enabled, the operation mode changes depending on the status of the SERCO NF pin and the GPIO10 pin (MODE pins) settings. Normally the system remains in the hardware control mode while the host interface is disabled. Following Table shows relations between settings and operation modes. GPALT[15:8] SERCONF[2:0] MODE Mode Communication conditions FFh 000 - Hardware control mode Fixed (*1) 010 High Hardware control mode Fixed (*1) Low Serial emulation mode (Active Open) Variable (*2) High Hardware control mode Fixed (*1) Low Serial emulation mode (Passive Open) Variable (*2) Other than above - Reserved. Do not set any other value. - - - Varies according to host Fixed (*1) 011 00h 15 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack interface setting. Disabled: Hardware control mode Enabled: Used as GPIO[15:8] Other than above - - - Disabled. Does not operate in either mode. *1: Start-Stop synchronous serial, 9600 baud, 8-bit data, 1 stop-bit, no parity, no flow control. *2: Set in the SERMODE register Note: After selecting each mode, do no access the serial interface for 100ms. 5.5.1 Hardware Control Mode When the "hardware control mode" mentioned in Table 2.1 is set, the serial interface operates with the hardware control mode. Use of this mode allows confirming and changing each hardware status (EEPROM, I2C, GPIO) from the serial interface. Use this mode to change the status of the EEPROM when the host CPU is not connected, or when you need to confirm the status of GPIO from the serial interface. When the hardware control mode is set, the communication conditions are fixed as follows. Start-Stop synchronous serial, 9600 baud, 8-bit data, 1 stop bit, no parity, no flow control 5.5.2 Serial Emulation Mode When the "serial emulation mode" mentioned in Table 2.1 is set, the serial interface operates in the serial emulation mode. In this mode, serial interface transmit and receive data are transmitted and received between destinations connected to the network (S232 is converted to Ethernet and vice versa). This mode is an especially effective way for a device with a conventional RS232 interface to exchange data with another device on the Ethernet. A TCP/IP connection is used. By enabling RTC/CTS control, flow control is also possible. The communication conditions are set up by the SERMODE register. [Establishing connection] When GPIO [15:8] is set to the serial emulation mode, the AX88198 performs processing equivalent to when a System Open command and TCP Open command are transmitted from the host interface. The contents of the SOPAR register are used as parameters by the System Open 16 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack command. With TCP Open, if SERCONF (bit[10:8] = 010 and Active Open, 011 then Passive Open processing is performed. In Active Open (when the client is operating), a connection request is issued to establish connection for the IP address (set by the DADR0H, DADR0L register) of the address preset in the EEPROM and the port (set by the PORT register). When the connection is later terminated by the destination, reconnection is performed automatically. In Passive Open (when the server is operating) the server opens the self-preset communication port (set by the PORT register) and waits for the connection (listen status). Connection is established when it is requested from outside. [Transmission from Serial Interface to Network] Serial data received from the serial interface is output to the network when no data is received during the transfer time of about 100 data after the last data was received or when 1 packet (536 bytes) of data was received. [Transmission from Network to Serial Interface] Data received from the network is transmitted to the serial interface after an error check is executed and header information is removed inside AX88198. Functions of each pin are as shown in following table Pin Pin Name In/Out Function GPIO15 1 DTR# O Data Terminal Ready Indicates that data receiving is enabled. It is a LOW active signal. Enters the Low status after initialization in the serial emulation mode. Normally High status in the hardware control mode. GPIO14 2 RTS# O Request to Send Indicates that data transmission is enabled. It is a LOW active signal. Enters the Low status when receiving is possible in the serial emulation mode. Hardware control mode is normally Low status. GPIO13 3 DSR# I Data Set Ready Input of the state that transmission from outside is enabled. Currently not used. GPIO12 4 CTS# I Clear to Send Input of the state that receive from outside is enabled. It is a LOW active signal. When this pin goes HIGH, transmission is temporarily suspended, and when it 17 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack returns to LOW, transmission is resumed. Since this operation is controlled according to the interrupt-based software control, the time from the transmission stop to the resumption after signal change is uncertain. So, the external device is requested to start the control when the buffer capacity is sufficient to some extent GPIO11 5 - - - GPIO10 6 MODE I Mode Select Used to switch over normal/hardware control modes. Be sure to set this pin to LOW in the normal mode. GPIO9 7 TXD O Transmit Data Serial transmit data GPIO8 8 RXD I Receive Sata Serial transmit data TXD and RXD are start-stop synchronous serial pins to be transmitted/received by use of the serial interface Ch.0 function of the built-in S1C33240. For details, refer to the serial interface specifications in the technical manual for the S1C33240. Other control lines are controlled by the software. CTS# signals are processed by internal interruptions. 5.6 Power Supply 5.6.1 Operating Voltage AX88198 operates with the voltage supplied across VDD and VSS. This operating voltage is as shown below. VDD = 3.30.3V(VSS = GND) Note: AX88198 has 7 VDD pins and 6 VSS pins. Be sure to connect every pin to the power supply so that any of them may not become open. 18 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 5.7 Power on Reset Be sure to implement initial reset at powering on in order to ensure normal start of AX88198. Schmitt input is applied RESET#. Operation of OSC3 oscillation circuit is started by the initial reset (RESET#=LOW) and then CPU is started by OSC3 clock at the positive going edge of the reset signal. OSC3 oscillation circuit takes some time until its oscillation stabilizes(VDD=3V, the time required for stabilized oscillation under normal operation condition: 10ms Max.). Thus, in order to ensure positive start of CPU, be sure to release the initial reset only after this time has been elapsed. Make sure that length of the initial reset pulse is longer than the above oscillation stabilizing time. 3.0V(VDD=3.3V) tSTA3 (OSC3 oscillation start time) Min. VDD 0.5VDD 0.1VDD RESET# Powering on Power on Reset Timing After powering on, maintain RESET# pin below 0.1 y VDD (LOW level) until supply voltage reaches the oscillation start voltage (3.0V) or above. It is also required to maintain RESET# pin below 0.5 y VDD until oscillation of OSC3 oscillation circuit is stabilized. Note: Oscillation start time of OSC3 oscillation circuit depends on the device substrate pattern used as well as the operating environment. So you must be sure to provide enough time before releasing the reset. x Reset pulse When AX88198 is in operation, it is possible to implement the initial reset by inputting LOW level pulse to the RESET# pin. In this case, however, the pulse width used must be greater than the minimum reset pulse width listed in the "AC Characteristics". When applying reset pulse while OSC3 oscillation circuit is not in operation, RESET# pin must be maintained at LOW level for a period longer than the oscillation stabilization time. It is the same requirement as that for the power on reset. x Check of Resetting Operation 19 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack When AX88198 hardware started operating after normal resetting, signals EP_SK and EP_CS change for checking connection of the EEPROM. also, when the AX88198 software started operating, signals MII_MDC and MII_MDIO change for checking connection of the PHY chip. If these signals do not change, check the power supply, the OSC3 clock, state of the RESET# pin and setting of the PLLC pin. When the initialization with the firmware completes, the BOOT status (000Bh) can be read from the host interface. (But, this does not apply when HIFSEL [2:0] pin is "111" and HIFSEL [2:0] of the HIFCR register is "111." In this setting, it is understood that "the host interface is not connected.") 2.6 OSC3 Clock Operating clock for AX88198 is entered to OSC3 pin. For the internal bus and CPU operation, the clock entered from OSC3 is used after it has been doubled. Normally, 25MHz clock is used. The lowest frequency allowed to input is 10MHz. While the power save mode is turned on, the internal bus clock and CPU operating clock is reduced to 1/4 of the normal operation (1/2 of that input from OSC3). When operating AX88198 on 100BASE-TX, be sure to enter 25MHz to OSC3 and operate AX88198 in the normal mode. Note that it cannot operate in the power saving mode. 20 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 5.8 NETWORK INTERFACE 5.8.1 MII Interface AX88198 employs MII (Media Independent Interface) for connection with the physical layer (PHY chip) enabling it to connect various network PHY chips designed for MII. For the detail of MII, refer to IEEE 802.3 Clause 22 (IEEE 802.3). However, your attention is required on the following points. * CRS (Carrier Sense) signal This signal is not used in Full Duplex communication. Connect CRS signal to GPIO2 pin only when Half Duplex communication is to take place. Also, when setting PHY forcibly to Half Duplex communication, Half Duplex must be set on GENCR. * TX_ER signal This signal is used to propagate the error received with RX_ER. used on AX88198 since it does have a repeating function. This signal, however, is not Following figures show MII transmit waveform and MII receive waveform, respectively. In transmission, MII_TXEN is set to HIGH level and then level of MII_TXD is changed after MII_TXCLK has reached HIGH level. In Half Duplex communication, interrupt occurs in AX88198 as MII_COL goes HIGH level thereby forcing MII_TXEN to LOW level and suspending transmission. Then transmission is resumed after a predetermined time. In receiving, after MII_RXDV has reached HIGH level, MII_RXD is acquired at positive-going edge of MII_RXCLK. If MII_RXER goes HIGH level while communicating with 100BASE-TX, FCS error is set after receiving is complete and the received frames are disposed. MII_TXCLK MII_TXEN MII_TXD[3:0] DATA DATA DATA DATA MII_COL MII Transmit Waveform 21 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack MII_RXCLK MII_RXDV MII_RXD[3:0] DATA DATA DATA DATA MII_RXER MII Receive Waveform 5.8.2 Management Interface AX88198 supports MII management interface. It can write or read registers in PHY through this interface. 5.8.3 Connecting PHY Chips Fig.3.5 shows connection between AX88198 and PHY chips. You do not have to connect CRS for Full Duplex communication only. Also, TX_ER signal is not connected. [Important] Make necessary setting so that the PHY chip address becomes 0x01 all the time. cannot be guaranteed if set to any other setting. Operation In the normal operation and the power save mode, OSC pin on AX88198 outputs the signal being formed after buffering OSC3 input. Thus connecting a 25MHz crystal oscillator to OSC3 input and connecting OSCO to the clock of PHY allows you operate both AX88198 and PHY with a single crystal oscillator. Note: Before supplying clock form OSCO to PHY, make sure that it meets the clock accuracy required by PHY. Also make sure that length of the pattern connected is minimized and the clock waveform satisfies requirements of the PHY specification. 22 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack After deciding a PHY chip to be used, acquire result of auto negotiation, speed (100BASE/10BASE) established by link and bit information showing the mode (Full Duplex/ Half Duplex) and arrange so that they are reflected to the ANEGR register. (Realtek Company's RTL8201L is not equipped with a register for storing result of auto negotiation and cannot be used for AX88198. ) x Acquiring Method of ANEGR Register Value (1) Seek for a register in which result of auto negotiation can be stored. In general, it is available between 16 and 19 or at 24 or 25. (2) Set the value obtained by subtracting 16 from the register offset to LSOFF bit. (3) Set DINV and SINV according to the result storing method. (4) Set each bit of DUPLEX and SPEED depending on the result store bit position. AX88198 PHY MII_RXCLK RX_CLK 4 MII_RXD[3:0] RXD[3:0] MII_RXDV RX_DV MII_TXCLK TX_CLK 4 MII_TXD[3:0] TXD[3:0] MII_TXEN TX_EN MII_RXER RX_ER MII_COL COL MDC MDC MDIO MDIO GPIO2/CRS CRS RX_ER OSCO CLKIN OSC3 25MHz VXCO 25MHz VXCO Connection between AX88198 and PHY 5.8.4 Communication Mode When using AX88198, it is normally recommended to select 10BASE-T/Full Duplex mode. AX88198 does not support 100BASE-TX/Full Duplex communication. When the automatic negotiation function of the PHY chip is used, the AX88198 performs auto-negotiation to select the communication mode in the following order: 1) 100Base 23 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack TX/half-duplex, 2) 10Base T/full-duplex, 3) 10Base T/half-duplex. in the mode of the first link established. The PHYMODE register can be set to limit the link conditions. Communication is performed Communication Mode Setup Flow (1)The auto-negotiation is executed selecting 100BASE-TX/Half Duplex as the target. If it ends successfully, 100BASE-TX/ Half Duplex is employed and the setup process is ended. Otherwise, the negotiation continues to the next step. (2)The auto-negotiation is started selecting 10BASE-T/Full Duplex as the target. If it ends successfully, 10BASE-T/Full Duplex is employed and the setup process is ended. Otherwise, the negotiation continues to the next step. (3)The auto-negotiation is executed selecting 10BASE-T/Half Duplex as the target. If it ends successfully, 10BASE-T/Half Duplex is employed. The setup process is ended. (Even when this is not applicable to auto-negotiation, it is specified that link is made in this state, and it is linked here if the connection is correct. ) (4)If all negotiations ended unsuccessfully, AX88198 judges that the link has not been established. 24 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 6. HOST INTERFACE The host interface is for connecting AX88198 to external CPU and is of 8-bit or 16-bit parallel type. The host interface allows connecting six types of CPUs directly depending on its setting. 6.1 Control Signals Following tables shows the host interface signals. Every input pin including I/O pins contain a pull-up resister enabling then to accept 5V input is acceptable for HCS#, HA [2:0], HD [15:0], HRD0#, HRD1#, HWR0# and HWR1#. Output is 3.3V CMOS or 3-state output. When not using the host interface (when implementing GPIO control independently, for instance), be sure to leave the every host interface signal unconnected. Pin name HCS# I/O Function I It is the access enable signal. Access available as it goes LOW. HA[2:0] I Port select signal HD[15:0] I/O Input/output data bus HRD0# I A R/W control signal. Its function depends on state of HIFSEL [2:0]. HRD1# I A R/W control signal. Its function depends on state of HIFSEL [2:0]. HWR0# I A R/W control signal. Its function depends on state of HIFSEL [2:0]. HWR1# I A R/W control signal. Its function depends on state of HIFSEL [2:0]. HINT Tri It is the interrupt signal. Polarity is settable. HIFSEL[2:0] I Host interface type select signal HMUX I Host interface bus multiplex (enabled at the reset) 1:Separate bus, 0:Multiplex bus HINTPOL I Host interrupt line polarity select (enabled at the reset) 1:HIGH active, 0:LOW active HENDIAN I Host interface endian select (enabled at the reset) 1:Big Endian, 0:Little Endian HSIZE I Host interface size select (enabled at the reset) 1:8bit, 0:16bit Tri: 3-state output When HCS# is LOW, an access port is selected depending on the state of HA [2:0]. shows the port assignment. 25 Following ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack (1) When 16-bit interface is selected HA[2:0] Access port Command port (Write) / Status port (Read) 00x Data port 01x Flag port 1xx Note: The flag port outputs the same contents to the upper and lower 8 bits. (2) When 8-bit interface is selected HA[2:0] Access port 000 Lower command port (Write) / Lower status port (Read) 001 Upper command port (Write) /Upper status port (Read) 010 Lower data port 011 Upper data port Flag port 1xx Note: When the 8-bit interface is used, data transfer of one time is completed as access is made to both the upper and lower ports. The order in accessing the upper and lower ports is optional. The flag port does not have the upper or lower port. 26 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7. Built-in Registers THIS PAGE LEFT BLANK 27 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack Register name Offset REVID 00h Major functions Device ID, Revision display (R/O) Register name Offset SNMSKH 13h Major functions Subnet mask MAC0 01h MAC address SNMSKL 14h Subnet mask MAC1 02h MAC address DGWH 15h Default gateway MAC2 03h MAC address DGWL 16h Default gateway GENCR 04h General-purpose setting register DADR0H 17h Destination address 0 HIFCR 05h Specifies host interface DADR0L 18h Destination address 0 2 I2CSAR 06h Specifies I C slave address DADR2H 19h Destination address 1 I2CCONF 07h DADR2L 1Ah Destination address 1 08h DADR2H 1Bh Destination address 2 GPALT Specifies I2C clock, specifies noise filter Enables alternate GPIO function 09h DADR2L 1Ch Destination address 2 GPCFG Specifies GPIO I/O 0Ah Specifies GPIO output value DADR3H 1Dh Destination address 3 GPDAT 0Bh DADR3L 1Eh PORT 1Fh Port number EPMSK 0Ch Specifies operation mask of GPIO from network Prohibits EEPROM operation from network Prohibits operation of I2C built-in slave from network Specifies waiting time in power management Specifies operation mode of PHY Destination address 3 GPMSK DPORT 20h Destination port number RSPAR 21h Serial communication mode setting TMOUT\ 22h Timeout setting SOPAR 23h SYSTEM OPEN flag COMN0 24h Community name of SNMP Agent COMN1 25h Community name of SNMP Agent COMN2 26h Community name of SNMP Agent COMN3 27h Community name of SNMP Agent I2CMAK 0Dh PMWAIT 0Eh PHYMODE 0Fh ANEGR 10h IPADRH 11h Specifies information to be stored auto-negotiation unique to PHY IP address IPADRL 12h IP address Unless specify. All bits are able to both READ and WRITE 28 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.1 REVID (Device ID, Revision display: 00h) bit Name Init. Description 15:8 REV 01h (Revision), this byte is "READ ONLY" Indicates revision of the chip. Current value is 01h. 7:0 C3h (Device ID) "READ ONLY" Indicates ID of the chip. ID of AX88198 is C3h. ID 7.2 MAC0 (MAC address:01h) bit Name Init. Description 15:8 MAC0L 00h MAC 0 (MSB Low byte) 7:0 00h MAC 0 (MSB high byte) MAC0H 7.3 MAC1 (MAC address:02h) bit Name Init. Description 15:8 MAC1L 00h MAC 1 low byte 7:0 00h MAC 1 high byte MAC1H 7.4 MAC2(MAC address:03h) bit Name Init. Description 15:8 MAC2L 00h MAC 2 (LSB Low byte) 7:0 00h MAC 2 (LSB high byte) MAC2H Example: When setting the MAC address 00-00-48-12-34-56, following values are specified to the registers. MAC0: 0000h, MAC1: 1248h, MAC2: 5634h, namely MAC0L-MAC0H- MAC1L-MAC1HMAC2L-MAC2H 29 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.5 GENCR (General Configuration Register: 04h) Description Bit Name Init 15 DISBC 0 (Disable Broadcast Receive) Used to specify whether broadcast packets are to be received or not. This function is used only under limited conditions. It should normally be set to 0. 0: Receives broadcast packets 1: Does not receive broadcast packets 14 DDSTEN 0 (Default Destination Massaging enable) When the INT0 function (separate GPIO0 function) is enabled, the interrupt notice function is enabled and DDSTEN indicates that the destination address of the notice transmission is enabled. 0: Interrupt notice function is invalid 1: Interrupt notice function is valid and DADR0H, DADR0L is valid 13 Reserved 0 Reserved. Be sure to set 0. 12 SLPEN 0 (Sleep Mode Enable) Selects use or non-use of the sleep mode as the power management. For the sleep mode, refer to Chapter 6. 0: Does not use the sleep mode 1: Use the sleep mode U When PMWAIT = 0, however, the sleep mode is not available despite of the setting of this bit. 11 PSEN 0 (Power Save Mode Enable) It reduces the operating clock to 1/4 of the normal level in order to save power consumption. 0: Does not use the power save mode. 1: Use the power save mode. 10:8 SERCONF 000 (Serial Configuration) When the serial Interface pin (alternate function of GPIO[15:8] is enabled, it specifies how to use the pin. 000: Hardware control mode (Note 1) 010: Serial emulation mode Active Open (Client operation) 011: Serial emulation mode Passive Open (Server operation) Other than the above: Reserved. Note 1 : A fixed operation all the time irrespective of state of the GPIO10/MODE pin. 30 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7:6 ESKDIV 00 (EEPROM Serial Clock Divide) It is used specify how the EEPROM Interface clock should be divided in comparison with the internal bus clock. The slower the clock is, the longer becomes the time required for the access. Set an appropriate time on the EEPROM connected. 11:/32 10:/64 01:/128 00:/256 5:4 MDCDIV 00 (MIF Clock Divide) It is used to specify how the MII Management Interface clock should be divided in comparison with the internal bus clock. The slower the clock is, the longer becomes the time required for the access. Set an appropriate division so that the clock may be 4MHz maximum. 11:1/4 10:1/8 01:1/16 00:1/32 3:0 Reserved 0000 Reserved. Be sure to set 0. 31 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.6 HIFCR (Specify Host interface: 05h) bit Name Init. Description 15 Reserved 0 14 HIPOL pin Host Interrupt Polarity: Sets the polarity when interrupts are used by the host I/F. 0:Low active 1:High active * The initial value depends on the status of the HIPOL pin when hardware is reset, with High=1and Low=0. 13 HMUX pin Host Multiplex: Determines whether the multiplex bus is used by the host interface. 0:Multiplex bus 1:Separate bus * The initial value depends on the status of the HMUX pin when hardware is reset, with High=0 and Low=1. 12 HENDN pin Host Endian: Sets the host I/F Endian type. 0:Little 1:Big * Set High=1, Low=0. The initial value depends on the status of the HENDIAN pin when hardware is reset. 11 HSIZE pin Host Interface Size: Sets host I/F bus width. 0:16bit 1:8bit * Set High=1, Low=0. The initial value depends on the status of the HSIZE pin when hardware is reset. 10:8 HIFSEL pin Host Interface Type: Switches the class of the host I/F. For more details, please refer to Chapter 4.3. * The initial value depends on the status of the HIFSEL[2:0] pin when hardware is reset, with High=1and Low=0. 7:0 Reserved 00h Reserved. Be sure to set 0. Reserved. Be sure to set 0. 32 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.7 I2CSADR(I2C Slave Address Register: offset 06h) bit Name Init. Description 15:7 Reserved all 0 Reserved. Be sure to set 0. 6:0 30h It is used to specify the slave address when AX88198 operates as I2C slave device. SADR Specify a value in the range of 30h to 37h. [ Important ] The value specified here must be the one officially assigned by Philips of Holland. For the AX88198, the range of 30h to 37h is assigned by Philips. 33 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.8 I2CCONF (I2C Configuration Register: offset 07h) bit Name Init. Description 15:11 Reserved 00000 Reserved. Be sure to set 0. 10:8 NCCNT 000 (Noise Cancel count value: Master, Slave) It is used to select a value of the noise canceller of I2C bus. A larger value removes noise better. Normally the value is selected in the 0 to 2. For a noisy environment, select 3 or greater value. 7:0 SCLCNT 00h (SCL delay count value: Master) When AX88198 operates as I2C master device, it is used to specify the I2C transfer clock. The transfer clock is calculated according to the following formula. I2C transfer clock [Hz] = Internal bus clock /(2 x (SCLCNT+NCCNT)+15) When connecting the Fast mode device, the clock should be 400kHz maximum. And when connecting the Normal mode device, 100kHz maximum is recommended. [ Setting example ] When OSC3 input is 25MHz, Internal bus clock = 50MHz As for Fast mode: SCLCNT=53 (35h), NCCNT=2 As for Normal mode: SCLCNT=241 (F1h), NCCNT=2 34 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.9 GPALT (GPIO Alternate Function Register: offset 08h) bit Name Init. Description 15:8 GPALT[15:8] FFh Used to enable function of GPIO [15:8] as the serial pin. Refer to Chapter 2.3 for detail. 0: GPIO function 1: Serial Interface pin [ Important ] Be sure to switch bit [15:8] in a lump. When set for any value other than "00h" or "FFh", does not operate normally for either function. 7 GPALT7 0 Used to enable function of GPIO7 as OSCCTL. After the sleep mode is turned on, GPIO7 is used to specify whether the external oscillator is to be stopped or not. When this bit is 1, GPIO7 generates output. In the normal operation, its output is HIGH level and in the sleep mode, LOW level is output. 0: GPIO7 1: OSCCTL output 6 GPALT6 0 Alternate function of GPIO6 is not prepared. Set "0". 5 GPALT5 0 Alternate function of GPIO5 is not prepared. Set "0". 4 GPALT4 0 Alternate function of GPIO4 is not prepared. Set "0". 3 GPALT3 0 2 GPALT2 0 1 GPALT1 0 0 GPALT0 0 Alternate function of GPIO3 is not prepared. Set "0". Used to enable function of GPIO2 as CRS. In Half Duplex communication, GPIO2 is used CRS input. 0: GPIO2 1: CRS input Alternate function of GPALT1 is not prepared. Set "0". Used to enable functions of GPIO0 as INT0. It detects the LOW level and enables the notification function on the network. Also, it restores the normal mode from the sleep mode. 0: GPIO0 1: INT0 (LOW Level) Note: When using it as INT0, design the peripheral circuits so that it comes to HIGH Level all the time other than interruption. 35 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.10 PCFG (GPIO I/O Configuration Register: offset 09h) bit Name 15:0 GPCFG15 to GPCFG0 Init. Description 0000h Used to specify input or output for GPIO [15:0]. Bit [15:0] is corresponding to GPIO [15:0] enabling bit-by-bit setup. or 0: Selects inputs 1: Selects output C200h Initial setting changes depending on the GPIO[15:8] setting z Initial value is C200h when serial pin is set (in hardware control mode, or serial emulation mode) z Initial value is 0000h for any other case. Also, the value of this register changes depending on the GPALT setting. z If GPALT[0]=1, then GPCFG[0]=0 (INT0 input) z If GPALT[2]=1, then GPCFG[2]=0 (CRS input) z If GPALT[7]=1, then GPCFG[7]=1 (OSCCTL output) z If GPALT[15:8]=FFh, then GPCFG[15:8]=C2h (DTR#, RTS#, TXD output) 7.11 GPDAT (GPIO Output Data Register: offset 0Ah) bit Name 15:0 GPDAT15 to GPDAT0 Init. Description 0000 When the output mode is set for GPIO [15:0], it is used to specify the value to be output to the pin. Bit [15:0] is or corresponding to GPIO [15:0] enabling bit-by-bit setup. 0200h When other than the output mode is selected, the value is saved on the register but not notified to the pin. or 0: LOW output 1: HIGH output 8200h Initial setting changes depending on the GPIO[15:8] setting z Initial value is 8200h for hardware control mode set in serial mode. z Initial value is 0200h for serial emulation mode set in serial mode. z Initial value is 0000h for any other case. Also, the value of this register changes depending on the GPALT setting. z If GPALT[7]=1, then GPDAT[7]=1 (OSCCTL=High) z If GPALT[15:8]=FFh, then GPDAT[9]=1 (TXD=High) 36 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.12 GPMSK (GPIO Access Mask Register: offset 0Bh) bit Name Init. Description 15:0 GPMSK15 0000h It disables modifying the output value of GPIO from network. Bit [15:0] is corresponding to GPIO [15:0] enabling bit-by-bit to setup. This setting is invalid when the output mode is not selected. However, the set value is maintained. GPMSK0 0: Allows modifications from network 1: Prohibits modifications from network 37 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.13 PMSK (EEPROM Access Mask Register: offset 0Ch) bit Name Init. Description 15:12 EPUSE 11 10 9 8 7:0 0000 EEPROM Usage: ID that indicates how to use EEPROM user areas (28h to 7Fh). 0000 - 0111 Standard (that users use freely.) 0001 - 0111 Reserve 1000 0111 MIB system group 1001 - 1111 Reserve PINGDIS 0 Pin0 Reply Disable: It is used to control the ping (ICMP Echo Reply) function. 0 - replies to ping. 1 - prohibits reply to ping. TFTPDIS 0 TFTP Service Disable: It is used to control the TFTP function (to be used for the firmware update function). 0 - enables the TFTP function. 1 - disables the TFTP function. HTTPDIS 0 HTTP Server Disable: It is used to control the HTTP server function (to be used for hardware control function). 0 - enables the HTTP server function. 1 - disables the HTTP server function. SNMPDIS 0 SNMP Server Disable: It is used to control the SNMP server function. 0 - enables the SNMP server function. 1 - disables the SNMP server function. EEPROM Access Mask: EPMSK[7:0] 00h It is used to specify areas where EEPROM is not rewritten to indices below set values from network. [EPUSE = 1000: MIB system group] When EPUSE is set to 1000 (MIB system group), the EEPROM user area is interpreted as follows: Offset Area size (byte) Usage 28h to 3Bh 40 Character string that becomes sysDescr of MIB-II system group. 3Ch to 3Fh 8 OID that becomes sysObjectID of MIB-II system group. 38 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack Store sysDescr in the form of character string. To store it as "test," for example, store the following value from the offset 28h. Byte string: 0x74, 0x65, 0x73, 0x74 EEPROM: 0x6574, 0x7473 When the byte string includes 0 or comes to 40 bytes, sysDescr is regarded to end there. Store sysObjectID from below enterprise. Before storing it, encode it to OID type with BER. When the sysObjectID is 1.3.6.1.4.1.1248.5.1.1.1, for example, store the following value from the offset 3Ch. Byte string: 0x89, 0x60, 0x05, 0x01, 0x01, 0x01 EEPROM: 0x6089, 0x0105, 0x0101 When the byte string includes 0 or comes to 8 bytes, sysObjectID is regarded to end there. Your attention is requested to the fact that, if 1 stands at the most significant bit of the offset 3Fh, the data becomes abnormal. 39 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.14 I2CMSK (I2C Slave Access Mask Register: offset 0Dh) bit Name 15:7 Reserved 6:0 Init. all 0 Description Reserved. Be sure to set 0. 2 I2CMSK[6:0] 000000 Prevents I C rewrites from the network for Index values lower than the value set. Note: With devices that specify indexes as more than one byte, this mask is valid only for the first index specification data (data that follows the slave device address specification). Only the second piece of data following the slave device address specification is affected by this mask. 7.15 PMWAIT (Power Management Wait Time Register: offset 0Eh) bit Name Init. Description 000h Reserved. Be sure to set 0. SLPWAIT 0h Sleep Wait Time It is used to specify the waiting time until the sleep mode is turned on from the power down mode. When the set value is n, the waiting time comes to 2n(ms) approximately. When 0 is specified, the sleep mode is not turned on irrespective of setting of SLPEN of the GENCR register. Specifying a value in the range from 1 to 15 allows setting the waiting time in the range from 2ms to 32768ms. 15:4 Reserved 3:0 40 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.16 PHYMODE (Physical Layer Operation Mode: offset 0Fh) bit Name 15 ANEGD 14:11 Reserved 10:8 AMODE 7:2 Reserved 1:0 MLINK Init. Description Auto Negotiation Disable: It is used to specify whether auto negotiation is used or not when a link is established. When a PHY chip to be used does not have the auto negotiation function or when the counterpart of the link does not support the auto negotiation function, 1 is set so that link conditions are set by MLINK bit. 0: Uses the auto negotiation function of PHY. 1: Does not use the auto negotiation function of PHY. 0000 Reserved. Be sure to set 0. 100 Auto Negotiation Link Mode: Used to specify an available link mode using the auto-negotiation. 000: 10BASE/Half Duplex 001: 10BASE/Full Duplex 010: 10BASE/Full or Half Duplex 011: 100BASE/Half Duplex 100: 100BASE/Half Duplex or 10BASE/Full or Half Duplex 101: 100BASE/Full Duplex or 10BASE/Full Duplex (reserved for future extension and thus not specifiable) 110: 100BASE/Full or Half Duplex (reserved for future extension and not thus specifiable) 111: Reserved Reserved. Be sure to set 0. 00 Manual Link: When ANEGEN=1, the manual procedure is specified for establishing the link. 00: 10BASE/Half Duplex 01: 10BASE/Full Duplex 10: 100BASE/Half Duplex 11: 100BASE/Full Duplex (reserved for future extension and thus not specifiable) 0 41 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.17 ANEGR (Auto Negotiation Result Information Register: offset 10h) bit Name Init. Description 15:12 LSOFF 0001 Link Status Offset: When the link is attempted through the auto-negotiation, which is unique to the PHY chip, is carried out, it is used to specify the position of MII management interface register to store the negotiation result as an offset from index 16. When it is 111, however, the index is 0. 0000: Index 16 register stores result of the attempt to establish the link. 0001: Index 17 register stores result of the attempt to establish the link. ... 1110: Index 30 register stores result of the attempt to establish the link. 1111: Index 0 register stores result of the attempt to establish the link. 11:10 Reserved 00 Reserved. Be sure to set 0. Duplex Invert: Used to change the meaning of bit being 9 DINV 0 specified for DUPLEX. 0: When Bit[DUPLEX]=1, Full Duplex and when Bit[DUPLEX]=0, Half Duplex. 1: When Bit[DUPLEX]=1, Half Duplex and when Bit[DUPLEX]=0, Full Duplex. Speed Invert: Used to change the meaning of bit being specified 8 SINV 0 with SPEED. 0: When Bit[SPEED]=1, 100BASE and when Bit[SPEED]=0, 10BASE. 1: When Bit[SPEED]=1, 10BASE and when Bit[SPEED]=0, 100BASE. 7:4 DUPLEX 1110 Duplex bit: It is used to specify the position of the bits to indicate the Duplex mode in the register storing the result of the auto-negotiation (indicated with LSOFF)/ 1111: bit15, 1110: bit14, ... 0001: bit1, 0000: bit0 3:0 SPEED 1111 Speed bit: It is used to specify the position of the bits to indicate the link speed in the register storing the result of the auto-negotiation (indicated with LSOFF). 1111: bit15, 1110: bit14, ... 0001: bit1, 0000: bit0 Setup example : ICS1893-Y of ICS Company stores results of the auto negotiation in the register of Index 17, allocates the link speed to bit15 and the Duplex mode to bit14. Thus, the setup is as follows: LSOFF=0001, DINV=0, SINV=0, DUPLEX=1110, SPEED=1111. 42 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.18 IPADRH, IPADRL (Default IP Address: offset 11h, 12h) Please refer to following table 7.19 SNMSKH, SNMSKL (Subnet Mask: offset 13h, 14h) Please refer to following table 7.20 DGWH, DGWL (Default Gateway: offset 15h, 16h) Please refer to following table 7.21 DADRnH, DADRnL (Destination Address: offset 17h to 1Eh) Please refer to following table DADR0H, DADR0L, DADR1H, DADR1L, DADR2H, DADR2L, DADR3H and DADR3L hold the four destination addresses. Also, DADR0H, DADR0L are used as the IP address in the following cases. x Connection destination IP address while client (Active Open) is operating in serial emulation mode. x Transmit destination IP address when using the GPIO0 interrupt notice function. Target IP address Subnet mask Default gateway Destination address 0 Destination address 1 Destination address 2 Destination address 3 Notation in Register setting hex 192.168.0.254 C0.A8.00.FE IPADRH=A8C0h, IPADRL=FE00h 255.255.255.0 FF.FF.FF.00 SNMSKH=FFFFh, SNMSKL=00FFh 192.168.0.1 C0.A8.00.01 DGWH=A8C0h, DGWL=0100h 192.168.0.2 C0.A8.00.02 DADR0H=A8C0h, DADR0L=0200h 192.168.0.3 C0.A8.00.03 DADR1H=A8C0h, DADR1L=0300h Initial value 192.168.0.4 192.168.0.5 C0.A8.00.04 DADR2H=A8C0h, DADR2L=0400h C0.A8.00.05 DADR3H=A8C0h, DADR3L=0500h 43 Offset 11h, 12h 13h, 14h 15h, 16h 17h, 18h, 19h, 1Ah 1Bh, 1Ch 1Dh, 1Eh ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.22 PORT (Default Port: offset 1Fh) It is used as Port Number in the following cases: x Listening port number in a server (Passive Open) operation in the serial emulation mode. x Transmit source port number of the transmit packet while client (Active Open) is operating in serial emulation mode. x Transmit source port number of the transmit packet when using the GPIO0 interrupt notice function. The default value is C000h (49152). 7.23 DPORT (Destination Port: offset 20h) It is used as Port Number in the following cases: x Destination port number in a client (Active Open) operation in the serial emulation mode. x Destination port number in using the interrupt notification function of GPIO0. The default value is C001h (49153). 44 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.24 SERMODE (Serial Mode: offset 21h) SERMODE sets the operation mode for the serial emulation operation. SERMODE is specified with the SERCONF setting of the GENCR register. The bits are assigned as follows for GENCR.SERCONF=010 (serial emulation mode). bit Name 15:9 Reserved 8:6 BAUD 5 LEN 4 STOP 3:2 PARITY 1:0 FLOW Init. Descriptions all 0 Reserved. Be sure to set 0. 011 Baud rate: Used to specify baud rate of the serial interface. 000: 1200 001: 2400 010: 4800 011: 9600 100: 19200 101: 38400 110: 57600 111: 115200 Data Length: Data length 1 0: 7bit 1: 8bit Stop bit: Stop bit length 0 0: 1bit 1: 2bit 00 Parity: Parity check setting 00: None 01: Reserved 10: Even number parity 11: Odd number parity Flow Control: Flow control setting 01 00: None 01: RTS/CTS 10 or 11: Reserved. 7.25 TMOUT Timeout: offset 22h) Used to specify the timeout value for TCP connection on the second time scale. The default value is 64 (40h). When 0 is specified, it is set to the default value (64 seconds). This setting is used for the following purposes in the same way as when TCP is specified by option parameters 12 and 13 of the open command. * * * * TTL of the IP datagram to be transmitted. Time taken to give up active open of the TCP. Time taken to wait for ACK to receive TCP transmitted data. Time taken to wait for host CPU's response for a received SNMP request. 45 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.26 SOPAR (System Open Parameter: offset 23h) When bit0 of flag data (No. 2 byte of option data) is 1 in opening the SYSTEM communication end point from the host interface, this setup is enabled. When bit0 is 0, this setup is disabled. Also, this setting is used as an open parameter even when the serial emulation mode is enabled. bit Name 15:8 Reserved 7 DLEN 6 IPEN 5 SNMEN 4 DGWEN 3:0 Reserved Init. Descriptions all 0 Reserved. Be sure to set 0. DATALINK Enable: 0 It is used to specify if the DATALINK layer is directly used. When this setup is enabled, the protocol processing built in AX88198 is not used and data transmitted and received on the network is handled as transmission and receive date of the host interface as it is. However, the create and check functions of FCS data are enabled. 0: The built-in protocol processing is used. 1: Data is directly input and output in and from the DATALINK layer. 1 IP Address Enable: It is used to specify whether specifying IP address from the host interface is enabled or disabled. 0: Disables specifying IP address and tries to acquire it by means of DHCP. 1: Enables specifying IP address. To enable specification with the built-in registers IPADRH and IPADRL, specify 0.0.0.0 to IP addresses to be specified from the host interface. 1 Subnet Mask Enable: It is used to specify whether specifying subnet mask from the host interface is enabled or disabled. 0: Disables specifying subnet mask and specifies default values of IP addresses. 1: Enables specifying subnet mask. To enable specification with the built-in registers SNMSKH and SNMSKL, specify 0.0.0.0 to subnet masks to be specified from the host interface. 1 Default Gateway Enable: It is used to specify whether specifying default gateway from the host interface is enabled or disabled. 0: Disables specifying default gateway. 1: Enables specifying default gateway. To enable specification with the built-in registers DGWH and DGWL, specify 0.0.0.0 to default gateway to be specified from the host interface. all 0 Reserved. Be sure to set 0. 46 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 7.27 COMN0, COMN1, COMN2, COMN3 (Community Name: offset 24h to 27h) It holds community name that can be set to the SNMP agent. Initial values and set values of respective registers are as shown in following table. The default community name of the SNMP agent is "public" irrespective of values of the built-in registers. Target Community name Initial value public Notation in hex Register setting COMN0=7570h, COMN1=6C62h, 70.75.62.6C.69.63.00.00 COMN2=6369h, COMN3=0000h 47 Offset 24h 25h 26h 27h ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 8. PRECAUTIONS ON IMPLEMENTATION Following describes the precautions to be heeded when designing substrates and implementing ICs. Oscillation circuit * Oscillation characteristics vary depending on given conditions (such as parts used and substrate patterns). In particular, when using ceramic or crystal transducers, maker specified constants of components such as capacitance and resistance should be strictly observed. * Disturbance of oscillation clock due to noises can cause malfunctioning. Pay attention to the following in order to prevent above trouble. (1) Be sure to minimize the distance when connecting parts such as transducer, resistor and capacitor to OSC3 (OSC1), OSC4 (OSC2) and PLLC pin. (2) Be sure to provide as much VSS pattern as possible to OSC3 (OSC1) and OSC4 (OSC2) pins as well as to peripheral areas of the parts connected to these pins. The same applies to PLLC pin, too. Don't try to connect non-oscillation system parts to this VSS pattern. (3) When entering external clock to OSC3 (OSC1) pin, be sure to minimize the distance from the clock source. In this case, OSC4 (OSC2) pin must be made open. * In order to prevent unstable operation of the oscillation circuit due to leak current across OSC3 (OSC1) - VDD, be sure to locate OSC3(OSC1) sufficiently away from VDD power supply and signal line on the substrate pattern. * When feeding clock to PHY chip by use of OSCO pin, try to minimize the pattern length. And, make sure that the clock satisfies the frequency accuracy required by PHY. Reset circuit * Reset signal entered to RESET# pin at powering on is affected by factors (such as turn on time of power supply, parts used and substrate patterns). Before employing the constants such as capacitance and resistance, be sure to test them carefully using applied products. As for the pull-up resister of RESET# pin, dispersion of resistance values must be carefully studied before finalizing the constant. * In order to prevent the reset due to noise during operation, be sure to connect the parts such as capacitor and resistor to RESET# pin with the minimum distance. Power supply * Sudden fluctuations in voltage due to noise can cause malfunctioning. In order to prevent above trouble, following rules should be observed. 48 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack (1) Use the shortest and thickest pattern as much as practicable for the connection between power supply and VDD or VSS pin. (2) Connect VDD pin and VSS pin with the minimum distance when connecting a bypass capacitor across VDD - VSS. Layout of signal line * Don't route a large current signal line near to circuits susceptible to noise (such as oscillation circuit). This rule must be observed in order to prevent electromagnetic induced noise resulting from mutual inductance. * If a HIGH-speed signal line is routed for a long distance in parallel with another signal line or if such line is routed across another line, noises can be generated from mutual interference between the signals resulting in the system malfunctioning. In particular, you must avoid routing a HIGH-speed signal line near to the circuits susceptible to noises. Network block * Don't route the signal lines for signals input to and output from PHY (such as TXP, TXN, RXP, and XN) near to the oscillation block. Processing Unused Pins * Unused GPIO pins should either be set for output, or their input levels should be fixed with pull-up or pull-down resistors. (Avoid connecting them directly to VDD or VSS. Inadvertently setting output could result in over current flow and destruction of the chip.) * If the environment contains lots of noise, pins should be provided with external pull-up/pull-down resistors even if they are provided with internal pull-up/pull-down. * Pins 76 and 77 are reserved for external circuit connections that will be required with planned low-cost replacements (a mask ROM version). 49 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 9. ELECTRIC CHARACTERISTICS 9.1 Absolute Maximum Rating Item Symb ol Supply voltage VDD Input voltage VI Condition Except FailSafe pin (*1) FailSafe pin (*1) HIGH level output current Rating -0.3 to +4.0 V -0.3 to VDD+0.5 V -0.3 to +7.0 V -10 mA -40 mA 10 mA 40 mA -65 to +150 C IOH 1 pin Total of all pins LOW level output current IOL 1 pin Total of all pins Storage temperature TSTG (VSS=0V) Unit Not e *1: FailSafe pin = HCS#,HA[2:0],HD[15:0],HRD0#,HRD1#,HWR0#,HWR1#,GPIO[7:0],EP_DI 9.2 Recommended Operating Conditions (VSS=0V) Item Supply voltage Symb ol Condition Typ. Max. Unit Note 3.00 - 3.60 V Except FailSafe pin (*1) VSS - VDD V FailSafe pin (*1) VSS - 5.5 V fCPU - - 50 MHz LOW-speed oscillation operating fOSC1 frequency - 32.76 8 - kHz -40 25 85 C 0 25 70 C Input voltage CPU operating frequency Operating temperature VDD Min. VI Ta During normal operation. When writing to Flash ROM Input rise time (normal input) tri - - 50 ns Input fall time (normal input) tfi - - 50 ns 50 ASIX ELECTRONICS 1 AX88198 L Fast Ethernet Controller with TCP/IP Stack Input rise time (Schmitt input) tri - - 5 ms Input fall time (Schmitt input) tfi 5 ms *1: FailSafe pin=HCS#,HA[2:0],HD[15:0],HRD0#,HRD1#,HWR0#,HWR1#,GPIO[7:0],EP_DI Note : When "HIGH" level output is turned on, don't apply external voltage HIGHer than the output voltage to FailSafe pin. 51 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 9.3 DC Characteristics (Except where otherwise specified: VDD=3.0V to 3.6V, Ta=-40C to +85C) Item Static current consumption Symb ol Condition IDDS Static state, Tj=85C Min. Typ. Max. Unit Note - - 120 A Large leak current ILI -1 - 1 A Off-state leak current IOZ -1 - 1 A HIGH level output voltage IOH=-2mA (Type1), VOH IOH=-6mA (Type2), VDD=Min. VDD -0.4 - - V - - 0.4 V LOW level output voltage VOL HIGH level input voltage VIH CMOS level, VDD=Max. 2.4 - - V LOW level input voltage VIL CMOS level, VDD=Min. - - 0.4 V Positive trigger input voltage VT+ CMOS Schmitt, VDD=Max. 1.1 - 2.4 V Negative trigger input voltage VT- CMOS Schmitt, VDD=Min. 0.6 - 1.8 V Hysteresis voltage VH CMOS Schmitt 0.1 - - V Pull-up resistor RPU VI=0V Other than DSIO 80 200 480 k DSIO 40 100 240 k 40 100 240 k Pull-down resistor IOL=2mA (Type1), IOL=6mA (Type2), VDD=Min. RPD VI=VDD (TEST0,TEST1) Input pin capacitance CI f=1MHz, VDD =0V - - 10 pF Output pin capacitance CO f=1MHz, VDD =0V - - 10 pF Input/output pin capacitance CIO f=1MHz, VDD =0V - - 10 pF Note: For the characteristics of pins, refer to "Appendix B List of Pin Characteristics". 52 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 9.4 Current consumption (Except where otherwise specified: VDD=3.0V to 3.6V, Ta=-40C to +85C) Item Current consumption Symb ol Condition IDD1 fCPU=50MHz Min. Typ. Max. Unit Note - 100 120 mA 1 When power save mode is IDD2 fCPU=12.5MHz turned on - 80 100 mA 2 When sleep mode is turned on - 30 120 mA 3 IDD3 OSC1 oscillation is 32.768kHz 1: When transmission and reception are conducted at the same time by use f internal loop back. 2: OSC3 and OSC1 are operated. 3: OSC3 is stopped and OSC1 is operated. 53 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 9.5 AC Characteristics 9.5.1 Description of Symbols tCYC: Bus clock cycle time : Depends on OSC3 input value. When OSC3 input = 25MHz, the internal bus clock = 50MHz : tCYC = 20ns 9.5.2 AC Characteristics Measuring Condition Signal detection level: Input signal HIGH level VIH=VDD-0.4V LOW level VIL=0.4V Output signal HIGH level VOH=1/2 VDD LOW level VOL=1/2 VDD Following conditions are assumed when external clock is entered to OSC3 Input signal HIGH level VIH=1/2 VDD LOW level VIL=1/2 VDD Input signal waveform: Output load capacitance: Rise (10%90%VDD) Fall (90%10%VDD) 5ns CL=50pF 54 5ns ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 9.5.3 AC Characteristics Table External clock input characteristics (Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85C) Item Symbol Min. Max. Unit Note HIGH-speed clock cycle time tC3 40 100 ns tC3ED 45 55 % OSC3 clock input rise time tIF - 5 ns OSC3 clock input fall time tIR - 5 ns Minimum reset pulse width tRST 6 tCYC - ns OSC3 clock input duty Input, output and input/output port (Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85C) Item Symbol Min. Max. Unit Note Input data setup time tINPS 20 - ns Input data hold time tINPH 10 - ns Output data delay time tOUTD - 20 ns Host interface (Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85C) Item Symbol Min. Max. Unit Note Host Interface access enabled period (HCS#,HA[2:0],HWR0#,HWR1#, HRD0#,HRD1#) tHAV 2tCYC+5 - ns Host Interface output data delay time tHOD - 25 ns Host Interface output floating delay time tHZD - 25 ns Host Interface interrupt output delay time tHIOD - 20 ns Host Interface interrupt floating delay time tHIZD - 20 ns Host Interface set input setup time tHIS 10 - ns Host Interface set input hold time tHID 10 - ns 55 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack MII (Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to (85(C) Item Symbol Min. Max. Unit Note MII output data delay time tTXD 0 15 ns MII input data setup time tRXS 10 - ns MII input data hold time tRXH 10 - ns MDIO output delay tMOD tCYC tCYC+5 ns MDIO data setup time tMIS 3 - ns MDIO data hold time tMIH 0 - ns Serial EEPROM (Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85C) Item Symbol Min. Max. Unit Note Input data setup time tEIS 15 - ns Input data hold time tEIH 0 - ns Output data delay time tEOD - 5 ns I2C bus (Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85C) Item Symbol Min. Max. Unit Note SDA data setup time tIIS 5 - ns SDA output delay time tIOD 5tCYC - ns 56 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 9.5.4 AC Characteristics Timing Chart Clock tC3 tC3H OSC3 (HIGH speed clock) tIF tIR Input, output, input/output port Internal bus clock tINPS tINPH GPIO input tOUTD GPIO output Host interface (Write) Internal bus clock tHAV HCS# HA[2:0] HWR0#,HWR1# HRD0#,HRD1# Invalid Valid HDATA[15:0] Invalid Write DATA 57 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack Host interface (Read) Internal bus clock tHAV HCS# HA[2:0] HWR0#,HWR1# HRD0#,HRD1# Invalid Valid tHOD HDATA[15:0] Invalid tHZD Read DATA Host interface (control line) Internal bus clock tHIZD tHIOD active HINT ( ) valid Status/Data Read Reset (set input) RESET# Internal bus clock HIFSEL[2:0] tHIS tHIH input HINTPOL HWPOL MII transmit 58 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack MII_TXCLK tTXD(Min.) tTXD(Max.) MII_TXD[3:0] MII TXEN 59 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack MII receive MII_RXCLK tRXS tRXH MII_RXD[3:0] MII_RXDV MDIO output MII_MDC tMOD MII MDIO MDIO input MII_MDC tMIS tMIH MII MDIO Serial EEPROM (Read) EP_CS EP_SK EP DO tEIS tEIH EP DI 60 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack Serial EEPROM (Write) EP_CS EP_SK tEOD EP DO HIGH(Pull-up) EP DI(Status) I2C bus tIIS tIOD SDA SCL 61 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack 10. PACKAGE QFP15-100pin : Plastic QFP 100pin Body size 14 x 14 x 1.4mm HD D 75 51 76 HE E 50 INDEX 26 100 1 e b 25 Symbol A1 A2 AMax. 2 R1 R C L2 3 L L1 Dimension in Millimeters 0 0.3 10 Min. Nom. Max. L E 13.9 14 14.1 L1 1 D 13.9 14 14.1 L2 0.5 1.7 HE 15.7 16 16.3 HD 15.7 16 16.3 A A1 A2 0.1 1.3 e 1.4 1.5 0.5 0.5 2 12 3 12 b 0.13 0.18 0.28 R 0.2 C 0.1 0.125 0.175 R1 0.2 62 0.7 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack Restrictions on Power Consumption Chip temperature goes higher as power consumption of LSI grows larger. Temperature of LSI chip in the package is calculated based on its ambient temperature Ta, heat resistance of package j-a and power consumption PD as shown below. Chip temperature (Tj) = Ta + (PD x j-a) (C) In the normal operation, it is recommended to maintain the chip temperature (Tj) below 85C. Following shows heat resistance of QFP15-100pin package. Heat resistance j-a = 100(C /W) 63 ASIX ELECTRONICS AX88198 L Fast Ethernet Controller with TCP/IP Stack Revision V.01 Date Comment 2003/11/1 Initial release 4F, NO.8, HSIN ANN RD., SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C. TEL: 886-3-5799500 FAX: 886-3-5799558 Email: Web: support@asix.com.tw http://www.asix.com.tw 64 ASIX ELECTRONICS