AX88198L - ASIX Electronics Corporation

ASIX ELECTRONICS CORPORATION

AX88198 L

Fast Ethernet Controller with TCP/IP Stack

Local Bus Fast Ethernet Controller with TCP/IP Stack

Document No.: AX88198-01/V.01/2003-11-0

Features:

z General purpose I/O pins and I2C busses

allow controlling hardware simply from

network without using a host CPU.

z Allows adding or changing the protocols

used through rewriting of the Flash ROM.

z Protocol supported ARP, ICMP, IP, TCP,

UDP, HTTP, DHCP, TFTP and SNMP.

z Interface with physical layer Media

Independent Interface (Complied with

Clause 22 of IEEE802.3) 10BASE-T/Full

Duplex, 10BASE-T/Half Duplex and

100BASE-TX/Half Duplex

(100BASE-TX/Full Duplex is not

supported)

z Effective transfer rate approximately 2Mbps

maximum.

z Host interface 8/16 bits parallel

z Directly connectable type Includes SH-3/4,

EPSON S1C33, MC68000, MC68030,

Philips PR31500/PR31700, Toshiba

TX3912, NEC VR4121, PC Card

(PCMCIA) and ISA.

z Endian switching between little and big is

possible.

z Host command system EPSON Standard

Code for Network

z General purpose I/O 16 maximum (Directly

controllable from the network. 8 out of

16 are shared with the serial interface.)

z EEPROM Interface 3-wire and 16-bit

Interface compatible with 93C46

(partially usable by user)

z I2C bus Master Function (Multi-master and

10bit slave supported. Fast/Normal

mode.) And slave function contained.

z Core CPU EPSON S1C33240 50MHz

z Built-in Flash ROM 128KB (1KB×128

blocks)

z Power supply 3.3V, 120mA (Max.)

z Package QFP15-100pin

Product description

AX88198L is best suited for making your 8/16 bits class CPU-featured equipment

connectable to network without using a HIGH performance OS or protocol stacks provided

by software vendors .Its capability of internally processing protocols for TCP/IP connection

including ARP, ICMP, IP, TCP and UDP.

ASIX ELECTRONICS CORPORATION

AX88198 L

Fast Ethernet Controller with TCP/IP Stack

CONTENT

1. Product description............................................................................................................................3

2. System Block Diagram.......................................................................................................................4

3. Pin Description...................................................................................................................................5

4. Pin Functions......................................................................................................................................6

5. HARDWARE SPECIFICATIONS........................................................................................................14

6. HOST INTERFACE............................................................................................................................25

7. Built-in Registers..............................................................................................................................27

8. PRECAUTIONS ON IMPLEMENTATION ..........................................................................................48

9. ELECTRIC CHARACTERISTICS ......................................................................................................50

10. PACKAGE........................................................................................................................................62

ASIX ELECTRONICS CORPORATION

AX88198 L

Fast Ethernet Controller with TCP/IP Stack

1. Product description

AX88198L is an intelligent network controller equipped with the built-in protocol processing

function. By simplified commands and data from the host CPU (EPSON C33) enables AX88198L

to establish TCP/IP communication .Its capability of internally processing protocols for TCP/IP

connection including ARP, ICMP, IP, TCP and UDP. MII (Media Independent Interface) is

employed for interfacing the physical layer. Just adding PHY chip designed for MII allows you

to realize 10BASE-T/100BASE-TX equipment operable on networks. AX88198L is best suited

for making your 8/16 bits class CPU-featured equipment connectable to network without

using a HIGH performance OS or protocol stacks provided by software vendors. Also, it

enables to connect your equipment directly to various types of host CPUs.

This data sheet includes hardware and register information only, For “Host interface connection”,

“Programming guide” and “demo board development kit”. Please refer to related application note.

ASIX ELECTRONICS CORPORATION

AX88198 L

Fast Ethernet Controller with TCP/IP Stack

2. System Block Diagram

32bit RISC CPU

Host MPU

Interface

CRC

Generator/

Checker

OSC3/PLL

MII Interface

SRAM

8KB

Flash ROM

128KB

C Bus

Master / Slave

EEPROM

Interface

High-speed

DMA ITC

(Interrupt

Controller)

I/O Port

Timer

DBG

(Debug

Unit)

Contr ol Regist ers

CPU

Core

Serial /

I/O Port

OSC1

OSC3

OSC4

OSC1

OSC2

DSIO

DST[2:0]

DPCO

DCLK

OSCO

HD[15:0]

HRD0#

HWR0#

HINT

HIFSEL[2:0]

HINTPOL

HENDIAN

SCL

SDA

EP_CS

EP_SK

EP_DO

EP_DI

GPIO7/OSCCTL

GPIO15/DTR#

GPIO14/RTS#

GPIO13/DSR#

GPIO12/CTS#

GPIO11/RSV1

GPIO10/MODE

GPIO9/TXD

GPIO8/RXD

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2/CRS

GPIO1

GPIO0/INT0

MII_TXCLK

MII_TXD[3:0]

MII_TXEN

MII_RXCLK

MII_RXD[3:0]

MII_RXDV

MII_COL

MII_RXER

MDC

MDIO

VDD

VSS

HCS#

HA[2:0]

PLLC

TEST[1:0]

RESET#

HSIZE

HRD1#

HWR1#

Inte rnal Bus

HMUX

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3. Pin Description

INDEX

100

AX88198

QFP15-100pin

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4. Pin Functions

4.1.1 Pin in Power Supply System

Pin name Pin No. I/O Function

VDD

18,32,44,

47,61,79,

Built-in logic power supply (+)

Power pins. Be sure to supply (3.3V to every pin.

VSS 9,25,45,5

2,70,88

__ Power supply (-) GND

Grounding pins. Be sure to ground every pin.

4.1.2 Host Interface Signals

Pin name Pin No. I/O Function

HCS# 48 I

Host Chip Select:

It is the host interface access control signal. Access to

the host interface is enabled as long as this signal remains

LOW.

This pin has a built-in pull-up resister enabling to accept

5V input.

HA[2:0] 51,50,49 I

Host Address:

It is the host interface port select signal. It selects the

port to be accessed while HCS# = LOW. Following

shows the selectable ports.

00x: Command port (write)/Status port (read)

01x: Data port (read/write)

1xx: Flag port (read/write)

These pins contain the pull-up resister enabling to accept

5V input.

Ú HA0 is used for switching between the upper and lower

bytes when the 8-bit interface is selected. It is

disabled when the 16-bit interface is used.

HD[15:0] 69 to62,

60 to 53

I/O Host Data:

Data signal line of the host interface. When the 8-bit

interface is selected, HDATA [7:0] alone is enabled and

HDATA [15:8] is not driven.

These pins contain the pull-up resister enabling to accept

5V input. Output is 3.3V CMOS output.

HRD0# 71 I

HRD1# 72 I

HWR0# 73 I

Host Read/Host Write:

R/W control signal of the host interface. Function

changes depending on the HIFSEL[2:0] bit status in the

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HWR1# 74 I

HIFCR register. For the detail, refer to “4. Host

Interface”.

These pins contain the pull-up resister enabling to accept

5V input.

HINT 75 Tri

Host Interrupt:

Interrupt line from AX88198 to the host interface.

Causes of interrupts are identifiable from contents of the

flag port. Polarity of the interrupt is changeable by

changing state of HINTPOL line at the reset.

Since this signal is 3.3V/3-state output, be sure to

externally connect a pull-up resister when HINTPOL=0

and a pull down resister when HINTPOL=1.

HIFSEL[2:0] 83,82,78 I Host Interface Select:

It is the host interface type select signal. These pins

contain the pull-up resister. For the detail, refer to “4.

Host Interface”.

HMUX 84 I

Host Bus Multiplex

It sets whether the address bus and the data bus of the host

interface are multiplexed in time-sharing. In case of

multiplex, a latched HD[2:0] is used instead of HA[2:0].

The control line to be used for latching varies with the

CPU type selected with HIFSEL.

1:Separate bus, 0:Multiplex bus

This pin was not used in our specifications before Rev.1.3

and is set as a separate bus type when nothing is

connected to. Connect this pin to GND only when a

multiplex bus is used.

State of this pin is acquired to the HIFCR register at reset.

This pin contains the pull-up resistor.

HINTPOL 85 I

Host Interrupt Polarity Select:

It is the polarity select pin for HRQI and HDVI when they

are active.

1:HIGH active, 0:LOW active

State of this pin is acquired to HIFCR at reset. This pin

contains the pull-up resister.

HENDIAN 92 I

Host Interface Endian Select:

It is the endian type select pin. Appropriately selecting the

type for a CPU to be used allows switching the upper and

lower data on the command or status port and on the data

port.

1:Big Endian, 0:Little Endian

State of this pin is acquired to the HIFCR register at reset.

This pin contains the pull-up resistor.

HSIZE 93 I

Host Bus Size Select:

It is the interface size select pin. It is used to specify the

data bus size when accessing the port.

1:8bit, 0:16bit

State of this pin is acquired to HIFCR at reset. This pin

contains the pull-up resister.

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4.1.3 MII Interface Signals

Pin name Pin No. I/O Function

MII_RXCLK 35 I

MII Receive Clock:

Receiving clock entered from PHY chip. It is the

reference clock of MII_RXD [3:0], MII_RXDV. Its

frequency is 2.5MHz for 10BASE-T and 25MHz for

100BASE-TX.

MII_RXD[3:0] 40 to 37 I MII Receive Data:

Receive data entered from PHY chip.

MII_RXDV 36 I

MII Receive Data Valid:

Input signal from PHY chip. If it is HIGH at the

positive going edge of MII_RXCLK, MII_RXD [3:0] is

valid.

MII_TXCLK 33 I

MII Transmit Clock:

Transmit clock entered from PHY chip. It is the

reference clock of MII_TXD [3:0], MII_TXEN. Its

frequency is 2.5MHz for 10BASE-T and 25MHz for

100BASE-TX.

MII_TXD[3:0] 27 to 30 O MII Transmit Data:

Transmit data output to PHY chip.

MII_TXEN 31 O

MII Transmit Enable:

Output signal to PHY chip. If it is HIGH at the positive

going edge of MII_TXCLK, MII_TXD[3:0] is valid.

MII_RXER 34 I

MII Receive Error:

Input signal from PHY chip. This signal indicates that

receive data contained an error. It is valid on

100BASE-TX alone and ignored on 10BASE-T.

MII_COL 26 I

MII Collision Detect:

It indicates that collision of signals occurred during Half

Duplex communication.

MDC 41 O

MII Management Interface Clock:

MDIO 42 I/O

MII Management Interface Data I/O

This pin must be connected to a pull-up resister

externally.

GPIO2/CRS 15 I

MII Carrier Sense

When the alternate function of GPIO2 is selected, this pin

functions as CRS input pin to enter state of the carrier in

Half Duplex communication. It is not used when Half

Duplex communication is not employed.

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4.1.4 External Device Control Signals

Pin name Pin No. I/O Function

EP_CS 19 O

EEPROM Chip Select:

It is the EEPROM chip select pin.

EP_SK 20 O

EEPROM Serial Clock:

It is the EEPROM clock pin.

EP_DI 21 I

EEPROM Data In:

It is the EEPROM data input pin.

EP_DO 22 O

EEPROM Data Out:

It is the EEPROM data output pin.

SCL 23 OD/I

I2C Serial Clock:

I2C bus serial clock pin. When the master is selected, it

is input signal and it becomes output signal when the

slave is selected.

Since output of this pin is open drain, a pull-up resister

must be provided externally. Select an optimum

pull-up resister value taking into consideration of load

on the bus as well as noises.

SDA 24 OD/I

I2C Serial Data:

I2C bus data input/output pin. It is a bi-directional

signal used to input or output data and ACK.

Since output of this pin is open drain, a pull-up resister

must be provided externally. Select an optimum

pull-up resister value taking into consideration of load

on the bus as well as noises.

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4.1.5 General Purpose Input and Output Pins

Pin name Pin No. I/O Function

GPIO0/INT0 17 I/O

GPIO1 16 I/O

GPIO2/CRS 15 I/O

GPIO3 14 I/O

GPIO4 13 I/O

GPIO5 12 I/O

GPIO6 11 I/O

GPIO7/OSCCTL 10 I/O

General Purpose I/O [7:0]:

They are general purpose input/output pins.

They accept 5V input.

GPIO0 is used as an interrupt pin and allows

sending interrupt notice to a previously

specified destination. GPIO2 is used as the

CRS input pin in Half Duplex

communication. GPIO7 can be used as the

OSC control pin in the sleep mode. For the

detail, refer to Chapter 5.3.

After the hardware is reset, all pins are used

for input only.

GPIO8/RXD 8 I/O

GPIO9/TXD 7 I/O

GPIO10/MODE 6 I/O

GPIO11/RSV1 5 I/O

GPIO12/CTS# 4 I/O

GPIO13/DSR# 3 I/O

GPIO14/RTS# 2 I/O

GPIO15/DTR# 1 I/O

General Purpose I/O [15:8]:

General-purpose input/output pin for 3.3V

CMOS level and Schmitt input. They can be

used as start-stop synchronous serial

terminals by setting GPLLT register.

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4.1.6 Clock Generator Pins

Pin name Pin no. I/O Function

OSC1 46 I

OSC2 43 O

OSC1 clock pin

When using the sleep mode in the power

management, it is used to connect 32.768kHz crystal.

AX88198 in the sleep mode is operated with this

clock. When the sleep mode is not used, connect

OSC1 to VSS and open OSC2.

OSC3 89 I

OSC4 87 O

OSC3 clock pin (for oscillation of crystal/ceramics or

for input of external clock)

Operating clock oscillation pin for AX88198. A

crystal transducer of 10 to 25MHz is connected.

When entering an external clock, input a clock of 10

to 25MHz to OSC3 and make OSC4 open.

OSCO 94 O

OSC output pin

It is used to generate buffered output of OSC3 input.

Frequency of output from this pin is the same as that

OSC3 input. Supplying clock to PHY chip from this

pin helps reducing number of oscillators for PHY.

PLLC 80 --

PLL capacitor connecting pin

It is the capacitor connecting pin for doubling OSC3

frequency with the internal PLL. Be sure to connect R

and C shown in Fig.1.3. Unless they are connected,

this IC does not operate normally.

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Fig.1.3 Clock Generator Connection Diagram

Crystal1 Crystal transducer 32.768kHz Ci (Max.)

=34kΩ

CG1 Gate capacitance 10pF

CD1 Drain capacitance 10pF

Rf1 Feedback

resistance

10MΩ

Crystal2 Crystal transducer 25MHz

CG2 Gate capacitance 10pF

CD2 Drain capacitance 10pF

Rf2 Feedback

resistance

1MΩ

R1 Resister 4.7kΩ

C1 Capacitor 100pF

C2 Capacitor 5pF

CG1

CD1

Rf1

Crystal1

CG2

CD2

Rf2

Crystal2

OSC3

OSC4

OSC1

OSC2

PLLC

VSS

R1 C1

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4.1.7 Other Pins

Pin name Pin No. I/O Function

DSIO 95 I/O

DST[2:0] 98,97,96 O

DPCO 99 O

DCLK 100 O

These pins are used for communication with the debug

tool ICD33. ICD33 is mainly use for rewriting flash

memory on AX88198.

It should not be connected to any equipment other than

above.

RESET# 91 I Hardware Reset Input:

AX88198 is reset as the LOW level is input. This pin

contains the pull-up resister.

TEST1,TEST0 86,81 I Test Input:

Testing pins for this IC. They are made open when

operated normally. They contain the pull-down

resistor.

Reserve 77,76

These pins are reserved for future expansion.

Normally, do not connect. Please refer to "AX88198

Technical Information No. 25" for more details about

replacement with new mask versions.

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5. HARDWARE SPECIFICATIONS

5.1 Core CPU

A 32 bits microcomputer is employed for the core CPU. CPU operating clock, always working

identically with the internal bus, is initially set to twice the OSC3. Setting PSEN bit (11 bit) of

GENCR register reduces it to 1/4 clock comparing when it operates normally. This arrangement

helps reducing operating current. The inside is processed according to Little Endian.

5.2 ROM and Boot Address

AX88198 contains a 128Kbytes Flash ROM. After the reset, it is started from 0×0C00000,

namely area 10 Flash ROM area. Of these 128Kbytes, 127Kbytes are for the system firmware

area, while the remaining 1Kbyte is for the user area. The user area ranges from 0×C1FC00 to

0×C1FFFF. Rewriting in the system firmware is done from the debug serial pin and network by

using a special tool and program. To rewrite in the user area, the debug serial pin or host

interface can be used. Also, to rewrite in the user area, the debug serial pin or the host interface

is used and the host interface command is executed, and it is not necessary to designate an absolute

address. However, this area can be used only as a data area. This area cannot store a program for

execution.

5.3 RAM

AX88198 contains an 8Kbytes RAM. Device size of this built-in RAM is 32 bits enabling to

read/write data of a byte, half-word or word in a single cycle. Since this RAM is exclusively

used by AX88198, user can’t operate it.

5.4 Peripheral Circuits

Among the peripheral blocks of the built-in core CPU S1C33240, S1S60000 uses the following

built-in peripheral circuits. For details of respective peripheral circuits, refer to “S1C33 Family

ASIC Macro Manual”.

• C33 core block

CPU 32-bit RISC type CPU S1C33000

BCU Bus control unit

ITC Interrupt controller

CLG Clock generator

DBG Functional block for debugging featured with ICD33

(In-Circuit Debugger for S1C33 Family)

• C33 peripheral circuits block

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Pre-scaler Used to set the clock for peripheral circuits

programmable

16 bits programmable timer

Serial interface

Input/output port

Elapsed timer

C33DMA block

HSDMA (HIGH-speed DMA) 4-channel

5.5 Serial Interface

GPIO [15:8] becomes the serial interface pin when the serial interface is in the enabled status and

when host interface is set off.

The serial interface is enabled when the following two conditions are met:

GPALT register bit [15:8] = FFh

GENCR register bit [10:8] (SERCONF) = “000” or “010” or “011”

The host interface is disabled when the following two conditions are met:

HIFSEL[2:0] pin = “LLL”

HIFCR register bit [10:8] (HIFSEL) = “111”

When the serial interface mode is enabled, the operation mode changes depending on the status of

the SERCO NF pin and the GPIO10 pin (MODE pins) settings. Normally the system remains in

the hardware control mode while the host interface is disabled.

Following Table shows relations between settings and operation modes.

GPALT[15:8] SERCONF[2:0] MODE Mode Communication

conditions

000 -

Hardware control mode Fixed (*1)

High Hardware control mode Fixed (*1) 010

Low Serial emulation mode

(Active Open)

Variable (*2)

High Hardware control mode Fixed (*1) 011

Low Serial emulation mode

(Passive Open)

Variable (*2)

FFh

Other than

above

- Reserved. Do not set any

other value.

00h - - Varies according to host Fixed (*1)

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interface setting.

Disabled: Hardware

control mode

Enabled: Used as

GPIO[15:8]

Other than

above

- - Disabled. Does not operate in

either mode.

*1: Start-Stop synchronous serial, 9600 baud, 8-bit data, 1 stop-bit, no parity, no flow control.

*2: Set in the SERMODE register

Note: After selecting each mode, do no access the serial interface for 100ms.

5.5.1 Hardware Control Mode

When the “hardware control mode” mentioned in Table 2.1 is set, the serial interface operates with

the hardware control mode. Use of this mode allows confirming and changing each hardware

status (EEPROM, I2C, GPIO) from the serial interface. Use this mode to change the status of the

EEPROM when the host CPU is not connected, or when you need to confirm the status of GPIO

from the serial interface.

When the hardware control mode is set, the communication conditions are fixed as follows.

Start-Stop synchronous serial, 9600 baud, 8-bit data, 1 stop bit, no parity, no flow control

5.5.2 Serial Emulation Mode

When the “serial emulation mode” mentioned in Table 2.1 is set, the serial interface operates in the

serial emulation mode. In this mode, serial interface transmit and receive data are transmitted

and received between destinations connected to the network (S232 is converted to Ethernet and

vice versa). This mode is an especially effective way for a device with a conventional RS232

interface to exchange data with another device on the Ethernet. A TCP/IP connection is used.

By enabling RTC/CTS control, flow control is also possible. The communication conditions are

set up by the SERMODE register.

[Establishing connection]

When GPIO [15:8] is set to the serial emulation mode, the AX88198 performs processing

equivalent to when a System Open command and TCP Open command are transmitted from the

host interface. The contents of the SOPAR register are used as parameters by the System Open

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command. With TCP Open, if SERCONF (bit[10:8] = 010 and Active Open, 011 then Passive

Open processing is performed.

In Active Open (when the client is operating), a connection request is issued to establish

connection for the IP address (set by the DADR0H, DADR0L register) of the address preset in the

EEPROM and the port (set by the PORT register). When the connection is later terminated by

the destination, reconnection is performed automatically.

In Passive Open (when the server is operating) the server opens the self-preset communication port

(set by the PORT register) and waits for the connection (listen status). Connection is established

when it is requested from outside.

[Transmission from Serial Interface to Network]

Serial data received from the serial interface is output to the network when no data is received

during the transfer time of about 100 data after the last data was received or when 1 packet (536

bytes) of data was received.

[Transmission from Network to Serial Interface]

Data received from the network is transmitted to the serial interface after an error check is

executed and header information is removed inside AX88198. Functions of each pin are as shown

in following table

Pin Pin Name In/Out Function

GPIO15 1 DTR# O Data Terminal Ready

Indicates that data receiving is enabled. It is a LOW

active signal. Enters the Low status after

initialization in the serial emulation mode.

Normally High status in the hardware control mode.

GPIO14 2 RTS# O Request to Send

Indicates that data transmission is enabled. It is a

LOW active signal. Enters the Low status when

receiving is possible in the serial emulation mode.

Hardware control mode is normally Low status.

GPIO13 3 DSR# I Data Set Ready

Input of the state that transmission from outside is

enabled. Currently not used.

GPIO12 4 CTS# I Clear to Send

Input of the state that receive from outside is enabled.

It is a LOW active signal. When this pin goes HIGH,

transmission is temporarily suspended, and when it

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returns to LOW, transmission is resumed. Since this

operation is controlled according to the

interrupt-based software control, the time from the

transmission stop to the resumption after signal

change is uncertain. So, the external device is

requested to start the control when the buffer capacity

is sufficient to some extent

GPIO11 5 - - -

GPIO10 6 MODE I Mode Select

Used to switch over normal/hardware control modes.

Be sure to set this pin to LOW in the normal mode.

GPIO9 7 TXD O Transmit Data

Serial transmit data

GPIO8 8 RXD I Receive Sata

Serial transmit data

TXD and RXD are start-stop synchronous serial pins to be transmitted/received by use of the serial

interface Ch.0 function of the built-in S1C33240. For details, refer to the serial interface

specifications in the technical manual for the S1C33240. Other control lines are controlled by the

software. CTS# signals are processed by internal interruptions.

5.6 Power Supply

5.6.1 Operating Voltage

AX88198 operates with the voltage supplied across VDD and VSS. This operating voltage is as

shown below.

VDD = 3.3±0.3V(VSS = GND)

Note: AX88198 has 7 VDD pins and 6 VSS pins. Be sure to connect every pin to the power

supply so that any of them may not become open.

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5.7 Power on Reset

Be sure to implement initial reset at powering on in order to ensure normal start of AX88198.

Schmitt input is applied RESET#.

Operation of OSC3 oscillation circuit is started by the initial reset (RESET#=LOW) and then CPU

is started by OSC3 clock at the positive going edge of the reset signal. OSC3 oscillation circuit

takes some time until its oscillation stabilizes(VDD=3V, the time required for stabilized oscillation

under normal operation condition: 10ms Max.). Thus, in order to ensure positive start of CPU, be

sure to release the initial reset only after this time has been elapsed. Make sure that length of the

initial reset pulse is longer than the above oscillation stabilizing time.

Power on Reset Timing

After powering on, maintain RESET# pin below 0.1 y VDD (LOW level) until supply voltage

reaches the oscillation start voltage (3.0V) or above. It is also required to maintain RESET# pin

below 0.5 y VDD until oscillation of OSC3 oscillation circuit is stabilized.

Note: Oscillation start time of OSC3 oscillation circuit depends on the device substrate pattern

used as well as the operating environment. So you must be sure to provide enough time before

releasing the reset.

x Reset pulse

When AX88198 is in operation, it is possible to implement the initial reset by inputting LOW level

pulse to the RESET# pin.

In this case, however, the pulse width used must be greater than the minimum reset pulse width

listed in the “AC Characteristics”.

When applying reset pulse while OSC3 oscillation circuit is not in operation, RESET# pin must be

maintained at LOW level for a period longer than the oscillation stabilization time. It is the same

requirement as that for the power on reset.

x Check of Resetting Operation

VDD

RESET#

tSTA3

(

OSC3 oscillation start time

)

Min.

3.0V

(

VDD=3.3V

)

0.5VDD

0.1VDD

Powering on

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When AX88198 hardware started operating after normal resetting, signals EP_SK and EP_CS

change for checking connection of the EEPROM. also, when the AX88198 software started

operating, signals MII_MDC and MII_MDIO change for checking connection of the PHY chip. If

these signals do not change, check the power supply, the OSC3 clock, state of the RESET# pin and

setting of the PLLC pin.

When the initialization with the firmware completes, the BOOT status (000Bh) can be read from

the host interface. (But, this does not apply when HIFSEL [2:0] pin is “111” and HIFSEL [2:0] of

the HIFCR register is “111.” In this setting, it is understood that “the host interface is not

connected.”)

2.6 OSC3 Clock

Operating clock for AX88198 is entered to OSC3 pin. For the internal bus and CPU operation,

the clock entered from OSC3 is used after it has been doubled. Normally, 25MHz clock is used.

The lowest frequency allowed to input is 10MHz.

While the power save mode is turned on, the internal bus clock and CPU operating clock is

reduced to 1/4 of the normal operation (1/2 of that input from OSC3).

When operating AX88198 on 100BASE-TX, be sure to enter 25MHz to OSC3 and operate

AX88198 in the normal mode. Note that it cannot operate in the power saving mode.

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5.8 NETWORK INTERFACE

5.8.1 MII Interface

AX88198 employs MII (Media Independent Interface) for connection with the physical layer

(PHY chip) enabling it to connect various network PHY chips designed for MII. For the detail of

MII, refer to IEEE 802.3 Clause 22 (IEEE 802.3 ). However, your attention is required on the 　

following points.

• CRS (Carrier Sense) signal

This signal is not used in Full Duplex communication. Connect CRS signal to GPIO2 pin only

when Half Duplex communication is to take place. Also, when setting PHY forcibly to Half

Duplex communication, Half Duplex must be set on GENCR.

• TX_ER signal

This signal is used to propagate the error received with RX_ER. This signal, however, is not

used on AX88198 since it does have a repeating function.

Following figures show MII transmit waveform and MII receive waveform, respectively.

In transmission, MII_TXEN is set to HIGH level and then level of MII_TXD is changed after

MII_TXCLK has reached HIGH level. In Half Duplex communication, interrupt occurs in

AX88198 as MII_COL goes HIGH level thereby forcing MII_TXEN to LOW level and

suspending transmission. Then transmission is resumed after a predetermined time.

In receiving, after MII_RXDV has reached HIGH level, MII_RXD is acquired at positive-going

edge of MII_RXCLK. If MII_RXER goes HIGH level while communicating with

100BASE-TX, FCS error is set after receiving is complete and the received frames are disposed.

MII Transmit Waveform

MII_TXCLK

MII_TXEN

MII_TXD[3:0] DATA DATA DATA DATA

MII_COL

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MII Receive Waveform

5.8.2 Management Interface

AX88198 supports MII management interface. It can write or read registers in PHY through this

interface.

5.8.3 Connecting PHY Chips

Fig.3.5 shows connection between AX88198 and PHY chips.

You do not have to connect CRS for Full Duplex communication only. Also, TX_ER signal is

not connected.

[Important]

Make necessary setting so that the PHY chip address becomes 0×01 all the time. Operation

cannot be guaranteed if set to any other setting.

In the normal operation and the power save mode, OSC pin on AX88198 outputs the signal being

formed after buffering OSC3 input. Thus connecting a 25MHz crystal oscillator to OSC3 input

and connecting OSCO to the clock of PHY allows you operate both AX88198 and PHY with a

single crystal oscillator.

Note: Before supplying clock form OSCO to PHY, make sure that it meets the clock accuracy

required by PHY. Also make sure that length of the pattern connected is minimized and the

clock waveform satisfies requirements of the PHY specification.

MII_RXCLK

MII_RXDV

MII_RXD[3:0] DATA DATA DATA DATA

MII_RXER

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After deciding a PHY chip to be used, acquire result of auto negotiation, speed

(100BASE/10BASE) established by link and bit information showing the mode (Full Duplex/ Half

Duplex) and arrange so that they are reflected to the ANEGR register. (Realtek Company’s

RTL8201L is not equipped with a register for storing result of auto negotiation and cannot be used

for AX88198. )

x Acquiring Method of ANEGR Register Value

(1) Seek for a register in which result of auto negotiation can be stored. In general, it is available

between 16 and 19 or at 24 or 25.

(2) Set the value obtained by subtracting 16 from the register offset to LSOFF bit.

(3) Set DINV and SINV according to the result storing method.

(4) Set each bit of DUPLEX and SPEED depending on the result store bit position.

Connection between AX88198 and PHY

5.8.4 Communication Mode

When using AX88198, it is normally recommended to select 10BASE-T/Full Duplex mode.

AX88198 does not support 100BASE-TX/Full Duplex communication.

When the automatic negotiation function of the PHY chip is used, the AX88198 performs

auto-negotiation to select the communication mode in the following order: 1) 100Base

PHY AX88198

MII_RXCLK

MII_RXD[3:0]

MII_RXDV

MII_TXCLK

MII_TXD[3:0]

MII_TXEN

MII_RXER

MII_COL

MDC

MDIO

RX_CLK

RX_DV

TX_CLK

TXD[3:0]

TX_EN

RX_ER

COL

MDC

MDIO

CRS

RX_ER

RXD[3:0]

GPIO2/CRS

25MHz VXCO

OSC3 OSCO CLKIN

25MHz VXCO

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TX/half-duplex, 2) 10Base T/full-duplex, 3) 10Base T/half-duplex. Communication is performed

in the mode of the first link established.

The PHYMODE register can be set to limit the link conditions.

Communication Mode Setup Flow

(1) The auto-negotiation is executed selecting 100BASE-TX/Half Duplex as the target. If it ends

successfully, 100BASE-TX/ Half Duplex is employed and the setup process is ended. Otherwise,

the negotiation continues to the next step.

(2) The auto-negotiation is started selecting 10BASE-T/Full Duplex as the target. If it ends

successfully, 10BASE-T/Full Duplex is employed and the setup process is ended.

Otherwise, the negotiation continues to the next step.

(3) The auto-negotiation is executed selecting 10BASE-T/Half Duplex as the target. If it ends

successfully, 10BASE-T/Half Duplex is employed. The setup process is ended. (Even when this

is not applicable to auto-negotiation, it is specified that link is made in this state, and it is linked

here if the connection is correct. )

(4) If all negotiations ended unsuccessfully, AX88198 judges that the link has not been established.

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6. HOST INTERFACE

The host interface is for connecting AX88198 to external CPU and is of 8-bit or 16-bit parallel

type. The host interface allows connecting six types of CPUs directly depending on its setting.

6.1 Control Signals

Following tables shows the host interface signals. Every input pin including I/O pins contain a

pull-up resister enabling then to accept 5V input is acceptable for HCS#, HA [2:0], HD [15:0],

HRD0#, HRD1#, HWR0# and HWR1#. Output is 3.3V CMOS or 3-state output. When not

using the host interface (when implementing GPIO control independently, for instance), be sure to

leave the every host interface signal unconnected.

Pin name I/O Function

HCS# I It is the access enable signal. Access available as it

goes LOW.

HA[2:0] I Port select signal

HD[15:0] I/O Input/output data bus

HRD0# I A R/W control signal. Its function depends on state of

HIFSEL [2:0].

HRD1# I A R/W control signal. Its function depends on state of

HIFSEL [2:0].

HWR0# I A R/W control signal. Its function depends on state of

HIFSEL [2:0].

HWR1# I A R/W control signal. Its function depends on state of

HIFSEL [2:0].

HINT Tri It is the interrupt signal. Polarity is settable.

HIFSEL[2:0] I Host interface type select signal

HMUX I Host interface bus multiplex (enabled at the reset)

1:Separate bus, 0:Multiplex bus

HINTPOL I Host interrupt line polarity select (enabled at the reset)

1:HIGH active, 0:LOW active

HENDIAN I Host interface endian select (enabled at the reset)

1:Big Endian, 0:Little Endian

HSIZE I Host interface size select (enabled at the reset)

1:8bit, 0:16bit

Tri: 3-state output

When HCS# is LOW, an access port is selected depending on the state of HA [2:0]. Following

shows the port assignment.

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(1) When 16-bit interface is selected

HA[2:0] Access port

00× Command port (Write) / Status port (Read)

01× Data port

1×× Flag port

Note: The flag port outputs the same contents to the upper and lower 8 bits.

(2) When 8-bit interface is selected

HA[2:0] Access port

000 Lower command port (Write) / Lower status port (Read)

001 Upper command port (Write) /Upper status port (Read)

010 Lower data port

011 Upper data port

1×× Flag port

Note: When the 8-bit interface is used, data transfer of one time is completed as access

is made to both the upper and lower ports. The order in accessing the upper

and lower ports is optional. The flag port does not have the upper or lower

port.

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7. Built-in Registers

THIS PAGE LEFT BLANK

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REVID 00h Device ID, Revision display (R/O)

MAC0 01h

MAC address

MAC1 02h

MAC address

MAC2 03h

MAC address

GENCR 04h

General-purpose setting register

HIFCR 05h

Specifies host interface

I2CSAR 06h

Specifies I2C slave address

I2CCONF 07h

Specifies I2C clock, specifies noise

filter

GPALT 08h

Enables alternate GPIO function

GPCFG 09h

Specifies GPIO I/O

GPDAT 0Ah

Specifies GPIO output value

GPMSK 0Bh

Specifies operation mask of GPIO

from network

EPMSK 0Ch

Prohibits EEPROM operation from

network

I2CMAK 0Dh

Prohibits operation of I2C built-in

slave from network

PMWAIT 0Eh

Specifies waiting time in power

management

PHYMODE 0Fh

Specifies operation mode of PHY

ANEGR 10h

Specifies information to be stored

auto-negotiation unique to PHY

IPADRH 11h

IP address

IPADRL 12h

IP address

SNMSKH 13h Subnet mask

SNMSKL 14h

Subnet mask

DGWH 15h

Default gateway

DGWL 16h

Default gateway

DADR0H 17h

Destination address 0

DADR0L 18h

Destination address 0

DADR2H 19h

Destination address 1

DADR2L 1Ah

Destination address 1

DADR2H 1Bh

Destination address 2

DADR2L 1Ch

Destination address 2

DADR3H 1Dh

Destination address 3

DADR3L 1Eh

Destination address 3

PORT 1Fh

Port number

DPORT 20h

Destination port number

RSPAR 21h

Serial communication mode setting

TMOUT\ 22h

Timeout setting

SOPAR 23h

SYSTEM OPEN flag

COMN0 24h

Community name of SNMP Agent

COMN1 25h

Community name of SNMP Agent

COMN2 26h

Community name of SNMP Agent

COMN3 27h

Community name of SNMP Agent

Unless specify. All bits are able to both READ and WRITE

29 ASIX ELECTRONICS

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Fast Ethernet Controller with TCP/IP Stack

7.1 REVID (Device ID, Revision display: 00h)

bit Name Init. Description

15:8 REV 01h (Revision), this byte is “READ ONLY”

Indicates revision of the chip. Current value is 01h.

7:0 ID C3h (Device ID) “READ ONLY”

Indicates ID of the chip. ID of AX88198 is C3h.

7.2 MAC0 (MAC address:01h)

bit Name Init. Description

15:8 MAC0L 00h MAC 0 (MSB Low byte)

7:0 MAC0H 00h

MAC 0 (MSB high byte)

7.3 MAC1 (MAC address:02h)

bit Name Init. Description

15:8 MAC1L 00h MAC 1 low byte

7:0 MAC1H 00h

MAC 1 high byte

7.4 MAC2(MAC address:03h)

bit Name Init. Description

15:8 MAC2L 00h MAC 2 (LSB Low byte)

7:0 MAC2H 00h

MAC 2 (LSB high byte)

Example:

When setting the MAC address 00-00-48-12-34-56, following values are specified to the registers.

MAC0: 0000h, MAC1: 1248h, MAC2: 5634h, namely MAC0L-MAC0H- MAC1L-MAC1H-

MAC2L-MAC2H

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7.5 GENCR (General Configuration Register: 04h)

Bit Name Init Description

15 DISBC 0 (Disable Broadcast Receive)

Used to specify whether broadcast packets are to be received or

not. This function is used only under limited conditions. It

should normally be set to 0.

0: Receives broadcast packets

1: Does not receive broadcast packets

14 DDSTEN 0 (Default Destination Massaging enable)

When the INT0 function (separate GPIO0 function) is enabled,

the interrupt notice function is enabled and DDSTEN indicates

that the destination address of the notice transmission is enabled.

0: Interrupt notice function is invalid

1: Interrupt notice function is valid and DADR0H, DADR0L

is valid

13 Reserved 0 Reserved. Be sure to set 0.

12 SLPEN 0 (Sleep Mode Enable)

Selects use or non-use of the sleep mode as the power

management. For the sleep mode, refer to Chapter 6.

0: Does not use the sleep mode

1: Use the sleep mode

Ú When PMWAIT = 0, however, the sleep mode is not available

despite of the setting of this bit.

11 PSEN 0 (Power Save Mode Enable)

It reduces the operating clock to 1/4 of the normal level in order

to save power consumption.

0: Does not use the power save mode.

1: Use the power save mode.

10:8 SERCONF 000 (Serial Configuration)

When the serial Interface pin (alternate function of GPIO[15:8]

is enabled, it specifies how to use the pin.

000: Hardware control mode (Note 1)

010: Serial emulation mode Active Open (Client operation)

011: Serial emulation mode Passive Open (Server operation)

Other than the above: Reserved.

Note 1 : A fixed operation all the time irrespective of state of the

GPIO10/MODE pin.

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7:6 ESKDIV 00 (EEPROM Serial Clock Divide)

It is used specify how the EEPROM Interface clock should be

divided in comparison with the internal bus clock. The slower

the clock is, the longer becomes the time required for the access.

Set an appropriate time on the EEPROM connected.

11:/32

10:/64

01:/128

00:/256

5:4 MDCDIV 00 (MIF Clock Divide)

It is used to specify how the MII Management Interface clock

should be divided in comparison with the internal bus clock.

The slower the clock is, the longer becomes the time required

for the access. Set an appropriate division so that the clock

may be 4MHz maximum.

11:1/4

10:1/8

01:1/16

00:1/32

3:0 Reserved 0000 Reserved. Be sure to set 0.

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7.6 HIFCR (Specify Host interface: 05h)

bit Name Init. Description

15 Reserved 0 Reserved. Be sure to set 0.

14 HIPOL pin Host Interrupt Polarity:

Sets the polarity when interrupts are used by the host I/F.

0:Low active

1:High active

* The initial value depends on the status of the HIPOL pin when

hardware is reset, with High=1and Low=0.

13 HMUX pin Host Multiplex:

Determines whether the multiplex bus is used by the host

interface.

0:Multiplex bus

1:Separate bus

* The initial value depends on the status of the HMUX pin when

hardware is reset, with High=0 and Low=1.

12 HENDN pin Host Endian:

Sets the host I/F Endian type.

0:Little

1:Big

* Set High=1, Low=0. The initial value depends on the status of

the HENDIAN pin when hardware is reset.

11 HSIZE pin Host Interface Size:

Sets host I/F bus width.

0:16bit

1:8bit

* Set High=1, Low=0. The initial value depends on the status of

the HSIZE pin when hardware is reset.

10:8 HIFSEL pin Host Interface Type:

Switches the class of the host I/F. For more details, please refer to

Chapter 4.3.

* The initial value depends on the status of the HIFSEL[2:0] pin

when hardware is reset, with High=1and Low=0.

7:0 Reserved 00h Reserved. Be sure to set 0.

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7.7 I2CSADR(I2C Slave Address Register: offset 06h)

bit Name Init. Description

15:7 Reserved all 0 Reserved. Be sure to set 0.

6:0 SADR 30h It is used to specify the slave address when AX88198 operates as

I2C slave device.

Specify a value in the range of 30h to 37h.

[ Important ]

The value specified here must be the one officially assigned by

Philips of Holland. For the AX88198, the range of 30h to 37h

is assigned by Philips.

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7.8 I2CCONF (I2C Configuration Register: offset 07h)

bit Name Init. Description

15:11 Reserved 00000 Reserved. Be sure to set 0.

10:8 NCCNT 000 (Noise Cancel count value: Master, Slave)

It is used to select a value of the noise canceller of I2C bus. A

larger value removes noise better. Normally the value is

selected in the 0 to 2. For a noisy environment, select 3 or

greater value.

7:0 SCLCNT 00h (SCL delay count value: Master)

When AX88198 operates as I2C master device, it is used to

specify the I2C transfer clock. The transfer clock is calculated

according to the following formula.

I2C transfer clock [Hz] = Internal bus clock /(2 ×

(SCLCNT+NCCNT)+15)

When connecting the Fast mode device, the clock should be

400kHz maximum. And when connecting the Normal mode

device, 100kHz maximum is recommended.

[ Setting example ]

When OSC3 input is 25MHz, Internal bus clock = 50MHz

As for Fast mode: SCLCNT=53 (35h), NCCNT=2

As for Normal mode: SCLCNT=241 (F1h), NCCNT=2

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7.9 GPALT (GPIO Alternate Function Register: offset 08h)

bit Name Init. Description

15:8 GPALT[15:8]

FFh Used to enable function of GPIO [15:8] as the serial pin. Refer

to Chapter 2.3 for detail.

0: GPIO function

1: Serial Interface pin

[ Important ]

Be sure to switch bit [15:8] in a lump. When set for any value

other than "00h" or "FFh", does not operate normally for either

function.

7 GPALT7 0 Used to enable function of GPIO7 as OSCCTL.

After the sleep mode is turned on, GPIO7 is used to specify

whether the external oscillator is to be stopped or not. When

this bit is 1, GPIO7 generates output. In the normal operation,

its output is HIGH level and in the sleep mode, LOW level is

output.

0: GPIO7

1: OSCCTL output

6 GPALT6 0 Alternate function of GPIO6 is not prepared. Set “0”.

5 GPALT5 0 Alternate function of GPIO5 is not prepared. Set “0”.

4 GPALT4 0 Alternate function of GPIO4 is not prepared. Set “0”.

3 GPALT3 0 Alternate function of GPIO3 is not prepared. Set “0”.

2 GPALT2 0 Used to enable function of GPIO2 as CRS.

In Half Duplex communication, GPIO2 is used CRS input.

0: GPIO2

1: CRS input

1 GPALT1 0 Alternate function of GPALT1 is not prepared. Set “0”.

0 GPALT0 0 Used to enable functions of GPIO0 as INT0.

It detects the LOW level and enables the notification function on

the network. Also, it restores the normal mode from the sleep

mode.

0: GPIO0

1: INT0 (LOW Level)

Note: When using it as INT0, design the peripheral circuits so

that it comes to HIGH Level all the time other than

interruption.

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7.10 PCFG (GPIO I/O Configuration Register: offset 09h)

bit Name Init. Description

15:0 GPCFG15

GPCFG0

0000h

C200h

Used to specify input or output for GPIO [15:0]. Bit [15:0] is

corresponding to GPIO [15:0] enabling bit-by-bit setup.

0: Selects inputs

1: Selects output

Initial setting changes depending on the GPIO[15:8] setting

z Initial value is C200h when serial pin is set (in hardware

control mode, or serial emulation mode)

z Initial value is 0000h for any other case.

Also, the value of this register changes depending on the

GPALT setting.

z If GPALT[0]=1, then GPCFG[0]=0 (INT0 input)

z If GPALT[2]=1, then GPCFG[2]=0 (CRS input)

z If GPALT[7]=1, then GPCFG[7]=1 (OSCCTL output)

z If GPALT[15:8]=FFh, then GPCFG[15:8]=C2h (DTR#,

RTS#, TXD output)

7.11 GPDAT (GPIO Output Data Register: offset 0Ah)

bit Name Init. Description

15:0 GPDAT15

GPDAT0

0000

0200h

8200h

When the output mode is set for GPIO [15:0], it is used to

specify the value to be output to the pin. Bit [15:0] is

corresponding to GPIO [15:0] enabling bit-by-bit setup.

When other than the output mode is selected, the value is saved

on the register but not notified to the pin.

0: LOW output

1: HIGH output

Initial setting changes depending on the GPIO[15:8] setting

z Initial value is 8200h for hardware control mode set in serial

mode.

z Initial value is 0200h for serial emulation mode set in serial

mode.

z Initial value is 0000h for any other case.

Also, the value of this register changes depending on the

GPALT setting.

z If GPALT[7]=1, then GPDAT[7]=1 (OSCCTL=High)

z If GPALT[15:8]=FFh, then GPDAT[9]=1 (TXD=High)

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7.12 GPMSK (GPIO Access Mask Register: offset 0Bh)

bit Name Init. Description

15:0 GPMSK15

GPMSK0

0000h It disables modifying the output value of GPIO from network.

Bit [15:0] is corresponding to GPIO [15:0] enabling bit-by-bit

setup. This setting is invalid when the output mode is not

selected. However, the set value is maintained.

0: Allows modifications from network

1: Prohibits modifications from network

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7.13 PMSK (EEPROM Access Mask Register: offset 0Ch)

bit Name Init. Description

15:12 EPUSE 0000 EEPROM Usage:

ID that indicates how to use EEPROM user areas (28h to 7Fh).

0000 – 0111 Standard (that users use freely.)

0001 – 0111 Reserve

1000 0111 MIB system group

1001 – 1111 Reserve

11 PINGDIS 0 Pin0 Reply Disable:

It is used to control the ping (ICMP Echo Reply) function.

0 – replies to ping.

1 – prohibits reply to ping.

10 TFTPDIS 0 TFTP Service Disable:

It is used to control the TFTP function (to be used for the

firmware update function).

0 – enables the TFTP function.

1 – disables the TFTP function.

9 HTTPDIS 0 HTTP Server Disable:

It is used to control the HTTP server function (to be used for

hardware control function).

0 – enables the HTTP server function.

1 – disables the HTTP server function.

8 SNMPDIS 0 SNMP Server Disable:

It is used to control the SNMP server function.

0 – enables the SNMP server function.

1 – disables the SNMP server function.

7:0 EPMSK[7:0] 00h

EEPROM Access Mask:

It is used to specify areas where EEPROM is not rewritten to

indices below set values from network.

[EPUSE = 1000: MIB system group]

When EPUSE is set to 1000 (MIB system group), the EEPROM user area is interpreted as follows:

Offset Area size (byte) Usage

28h to 3Bh 40 Character string that becomes sysDescr of MIB-II

system group.

3Ch to 3Fh 8 OID that becomes sysObjectID of MIB-II system

group.

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Fast Ethernet Controller with TCP/IP Stack

Store sysDescr in the form of character string. To store it as “test,” for example, store the following

value from the offset 28h.

Byte string: 0×74, 0×65, 0×73, 0×74

EEPROM: 0×6574, 0×7473

When the byte string includes 0 or comes to 40 bytes, sysDescr is regarded to end there.

Store sysObjectID from below enterprise. Before storing it, encode it to OID type with BER.

When the sysObjectID is 1.3.6.1.4.1.1248.5.1.1.1, for example, store the following value from the

offset 3Ch.

Byte string: 0×89, 0×60, 0×05, 0×01, 0×01, 0×01

EEPROM: 0×6089, 0×0105, 0×0101

When the byte string includes 0 or comes to 8 bytes, sysObjectID is regarded to end there. Your

attention is requested to the fact that, if 1 stands at the most significant bit of the offset 3Fh, the

data becomes abnormal.

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7.14 I2CMSK (I2C Slave Access Mask Register: offset 0Dh)

bit Name Init. Description

15:7 Reserved all 0 Reserved. Be sure to set 0.

6:0 I2CMSK[6:0] 000000

Prevents I2C rewrites from the network for Index values lower

than the value set.

Note: With devices that specify indexes as more than one byte,

this mask is valid only for the first index specification

data (data that follows the slave device address

specification).

Only the second piece of data following the slave device

address specification is affected by this mask.

7.15 PMWAIT (Power Management Wait Time Register: offset 0Eh)

bit Name Init. Description

15:4 Reserved 000h

Reserved. Be sure to set 0.

3:0 SLPWAIT 0h Sleep Wait Time

It is used to specify the waiting time until the sleep mode is

turned on from the power down mode. When the set value is n,

the waiting time comes to 2n(ms) approximately.

When 0 is specified, the sleep mode is not turned on irrespective

of setting of SLPEN of the GENCR register.

Specifying a value in the range from 1 to 15 allows setting the

waiting time in the range from 2ms to 32768ms.

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7.16 PHYMODE (Physical Layer Operation Mode: offset 0Fh)

bit Name Init. Description

15 ANEGD 0 Auto Negotiation Disable:

It is used to specify whether auto negotiation is used or not when

a link is established. When a PHY chip to be used does not have

the auto negotiation function or when the counterpart of the link

does not support the auto negotiation function, 1 is set so that

link conditions are set by MLINK bit.

0: Uses the auto negotiation function of PHY.

1: Does not use the auto negotiation function of PHY.

14:11 Reserved 0000 Reserved. Be sure to set 0.

10:8 AMODE 100 Auto Negotiation Link Mode:

Used to specify an available link mode using the

auto-negotiation.

000: 10BASE/Half Duplex

001: 10BASE/Full Duplex

010: 10BASE/Full or Half Duplex

011: 100BASE/Half Duplex

100: 100BASE/Half Duplex or 10BASE/Full or Half Duplex

101: 100BASE/Full Duplex or 10BASE/Full Duplex (reserved

for future extension and thus not specifiable)

110: 100BASE/Full or Half Duplex (reserved for future

extension and not thus specifiable)

111: Reserved

7:2 Reserved Reserved. Be sure to set 0.

1:0 MLINK 00 Manual Link:

When ANEGEN=1, the manual procedure is specified for

establishing the link.

00: 10BASE/Half Duplex

01: 10BASE/Full Duplex

10: 100BASE/Half Duplex

11: 100BASE/Full Duplex (reserved for future extension and

thus not specifiable)

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Fast Ethernet Controller with TCP/IP Stack

7.17 ANEGR (Auto Negotiation Result Information Register: offset 10h)

bit Name Init. Description

15:12 LSOFF 0001 Link Status Offset: When the link is attempted through the

auto-negotiation, which is unique to the PHY chip, is carried out,

it is used to specify the position of MII management interface

When it is 111, however, the index is 0.

0000: Index 16 register stores result of the attempt to establish

the link.

0001: Index 17 register stores result of the attempt to establish

the link.

...

1110: Index 30 register stores result of the attempt to establish

the link.

1111: Index 0 register stores result of the attempt to establish

the link.

11:10 Reserved 00 Reserved. Be sure to set 0.

9 DINV 0 Duplex Invert: Used to change the meaning of bit being

specified for DUPLEX.

0: When Bit[DUPLEX]=1, Full Duplex and when

Bit[DUPLEX]=0, Half Duplex.

1: When Bit[DUPLEX]=1, Half Duplex and when

Bit[DUPLEX]=0, Full Duplex.

8 SINV 0 Speed Invert: Used to change the meaning of bit being specified

with SPEED.

0: When Bit[SPEED]=1, 100BASE and when Bit[SPEED]=0,

10BASE.

1: When Bit[SPEED]=1, 10BASE and when Bit[SPEED]=0,

100BASE.

7:4 DUPLEX 1110

Duplex bit:

It is used to specify the position of the bits to indicate the

Duplex mode in the register storing the result of the

auto-negotiation (indicated with LSOFF)/

1111: bit15, 1110: bit14, ... 0001: bit1, 0000: bit0

3:0 SPEED 1111

Speed bit:

It is used to specify the position of the bits to indicate the link

speed in the register storing the result of the auto-negotiation

(indicated with LSOFF).

1111: bit15, 1110: bit14, ... 0001: bit1, 0000: bit0

Setup example :

ICS1893-Y of ICS Company stores results of the auto negotiation in the register of Index 17,

allocates the link speed to bit15 and the Duplex mode to bit14. Thus, the setup is as follows:

LSOFF=0001, DINV=0, SINV=0, DUPLEX=1110, SPEED=1111.

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7.18 IPADRH, IPADRL (Default IP Address: offset 11h, 12h)

Please refer to following table

7.19 SNMSKH, SNMSKL (Subnet Mask: offset 13h, 14h)

Please refer to following table

7.20 DGWH, DGWL (Default Gateway: offset 15h, 16h)

Please refer to following table

7.21 DADRnH, DADRnL (Destination Address: offset 17h to 1Eh)

Please refer to following table

DADR0H, DADR0L, DADR1H, DADR1L, DADR2H, DADR2L, DADR3H and DADR3L hold

the four destination addresses. Also, DADR0H, DADR0L are used as the IP address in the

following cases.

x Connection destination IP address while client (Active Open) is operating in serial emulation

mode.

x Transmit destination IP address when using the GPIO0 interrupt notice function.

Target Initial value

Notation in

hex Register setting Offset

IP address 192.168.0.254 C0.A8.00.FE IPADRH=A8C0h,

IPADRL=FE00h

11h, 12h

Subnet mask 255.255.255.0 FF.FF.FF.00 SNMSKH=FFFFh,

SNMSKL=00FFh

13h, 14h

Default gateway 192.168.0.1 C0.A8.00.01 DGWH=A8C0h,

DGWL=0100h

15h, 16h

Destination

address 0

192.168.0.2 C0.A8.00.02 DADR0H=A8C0h,

DADR0L=0200h

17h,

18h,

Destination

address 1

192.168.0.3 C0.A8.00.03 DADR1H=A8C0h,

DADR1L=0300h

19h,

1Ah

Destination

address 2

192.168.0.4 C0.A8.00.04 DADR2H=A8C0h,

DADR2L=0400h

1Bh,

1Ch

Destination

address 3

192.168.0.5 C0.A8.00.05 DADR3H=A8C0h,

DADR3L=0500h

1Dh,

1Eh

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Fast Ethernet Controller with TCP/IP Stack

7.22 PORT (Default Port: offset 1Fh)

It is used as Port Number in the following cases:

x Listening port number in a server (Passive Open) operation in the serial emulation mode.

x Transmit source port number of the transmit packet while client (Active Open) is operating in

serial emulation mode.

x Transmit source port number of the transmit packet when using the GPIO0 interrupt notice

function.

The default value is C000h (49152).

7.23 DPORT (Destination Port: offset 20h)

It is used as Port Number in the following cases:

x Destination port number in a client (Active Open) operation in the serial emulation mode.

x Destination port number in using the interrupt notification function of GPIO0.

The default value is C001h (49153).

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7.24 SERMODE (Serial Mode: offset 21h)

SERMODE sets the operation mode for the serial emulation operation. SERMODE is specified

with the SERCONF setting of the GENCR register.

The bits are assigned as follows for GENCR.SERCONF=010 (serial emulation mode).

bit Name Init. Descriptions

15:9 Reserved all 0 Reserved. Be sure to set 0.

8:6 BAUD 011

Baud rate: Used to specify baud rate of the serial interface.

000: 1200

001: 2400

010: 4800

011: 9600

100: 19200

101: 38400

110: 57600

111: 115200

5 LEN 1 Data Length: Data length

0: 7bit

1: 8bit

4 STOP 0 Stop bit: Stop bit length

0: 1bit

1: 2bit

3:2 PARITY 00 Parity: Parity check setting

00: None

01: Reserved

10: Even number parity

11: Odd number parity

1:0 FLOW 01 Flow Control: Flow control setting

00: None

01: RTS/CTS

10 or 11: Reserved.

7.25 TMOUT Timeout: offset 22h)

Used to specify the timeout value for TCP connection on the second time scale. The default

value is 64 (40h). When 0 is specified, it is set to the default value (64 seconds). This setting is

used for the following purposes in the same way as when TCP is specified by option parameters 12

and 13 of the open command.

• TTL of the IP datagram to be transmitted.

• Time taken to give up active open of the TCP.

• Time taken to wait for ACK to receive TCP transmitted data.

• Time taken to wait for host CPU’s response for a received SNMP request.

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7.26 SOPAR (System Open Parameter: offset 23h)

When bit0 of flag data (No. 2 byte of option data) is 1 in opening the SYSTEM communication

end point from the host interface, this setup is enabled. When bit0 is 0, this setup is disabled.

Also, this setting is used as an open parameter even when the serial emulation mode is enabled.

bit Name Init. Descriptions

15:8 Reserved all 0 Reserved. Be sure to set 0.

7 DLEN 0 DATALINK Enable:

It is used to specify if the DATALINK layer is directly used.

When this setup is enabled, the protocol processing built in

AX88198 is not used and data transmitted and received on the

network is handled as transmission and receive date of the host

interface as it is. However, the create and check functions of

FCS data are enabled.

0: The built-in protocol processing is used.

1: Data is directly input and output in and from the

DATALINK layer.

6 IPEN 1

IP Address Enable:

It is used to specify whether specifying IP address from the host

interface is enabled or disabled.

0: Disables specifying IP address and tries to acquire it by means

of DHCP.

1: Enables specifying IP address.

∗ To enable specification with the built-in registers IPADRH and

IPADRL, specify 0.0.0.0 to IP addresses to be specified from

the host interface.

5 SNMEN 1

Subnet Mask Enable:

It is used to specify whether specifying subnet mask from the

host interface is enabled or disabled.

0: Disables specifying subnet mask and specifies default values

of IP addresses.

1: Enables specifying subnet mask.

∗ To enable specification with the built-in registers SNMSKH

and SNMSKL, specify 0.0.0.0 to subnet masks to be specified

from the host interface.

4 DGWEN 1

Default Gateway Enable:

It is used to specify whether specifying default gateway from the

host interface is enabled or disabled.

0: Disables specifying default gateway.

1: Enables specifying default gateway.

∗ To enable specification with the built-in registers DGWH and

DGWL, specify 0.0.0.0 to default gateway to be specified

from the host interface.

3:0 Reserved all 0

Reserved. Be sure to set 0.

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7.27 COMN0, COMN1, COMN2, COMN3 (Community Name: offset 24h to 27h)

It holds community name that can be set to the SNMP agent. Initial values and set values of

respective registers are as shown in following table. The default community name of the SNMP

agent is “public” irrespective of values of the built-in registers.

Target Initial

value Notation in hex Register setting Offset

Community

name public 70.75.62.6C.69.63.00.00

COMN0=7570h,

COMN1=6C62h,

COMN2=6369h,

COMN3=0000h

24h

25h

26h

27h

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8. PRECAUTIONS ON IMPLEMENTATION

Following describes the precautions to be heeded when designing substrates and implementing

ICs.

 Oscillation circuit

• Oscillation characteristics vary depending on given conditions (such as parts used and

substrate patterns). In particular, when using ceramic or crystal transducers, maker

specified constants of components such as capacitance and resistance should be strictly

observed.

• Disturbance of oscillation clock due to noises can cause malfunctioning. Pay attention to

the following in order to prevent above trouble.

(1) Be sure to minimize the distance when connecting parts such as transducer, resistor and

capacitor to OSC3 (OSC1), OSC4 (OSC2) and PLLC pin.

(2) Be sure to provide as much VSS pattern as possible to OSC3 (OSC1) and OSC4 (OSC2)

pins as well as to peripheral areas of the parts connected to these pins. The same applies

to PLLC pin, too. Don’t try to connect non-oscillation system parts to this VSS pattern.

(3) When entering external clock to OSC3 (OSC1) pin, be sure to minimize the distance from

the clock source. In this case, OSC4 (OSC2) pin must be made open.

• In order to prevent unstable operation of the oscillation circuit due to leak current across

OSC3 (OSC1) - VDD, be sure to locate OSC3(OSC1) sufficiently away from VDD power

supply and signal line on the substrate pattern.

• When feeding clock to PHY chip by use of OSCO pin, try to minimize the pattern length. And,

make sure that the clock satisfies the frequency accuracy required by PHY.

 Reset circuit

• Reset signal entered to RESET# pin at powering on is affected by factors (such as turn on

time of power supply, parts used and substrate patterns). Before employing the constants

such as capacitance and resistance, be sure to test them carefully using applied products. As

for the pull-up resister of RESET# pin, dispersion of resistance values must be carefully

studied before finalizing the constant.

• In order to prevent the reset due to noise during operation, be sure to connect the parts such

as capacitor and resistor to RESET# pin with the minimum distance.

 Power supply

• Sudden fluctuations in voltage due to noise can cause malfunctioning. In order to prevent

above trouble, following rules should be observed.

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(1) Use the shortest and thickest pattern as much as practicable for the connection between

power supply and VDD or VSS pin.

(2) Connect VDD pin and VSS pin with the minimum distance when connecting a bypass

capacitor across VDD - VSS.

 Layout of signal line

• Don’t route a large current signal line near to circuits susceptible to noise (such as oscillation

circuit). This rule must be observed in order to prevent electromagnetic induced noise

resulting from mutual inductance.

• If a HIGH-speed signal line is routed for a long distance in parallel with another signal line or

if such line is routed across another line, noises can be generated from mutual interference

between the signals resulting in the system malfunctioning. In particular, you must avoid

routing a HIGH-speed signal line near to the circuits susceptible to noises.

 Network block

• Don’t route the signal lines for signals input to and output from PHY (such as TXP, TXN,

RXP, and XN) near to the oscillation block.

 Processing Unused Pins

• Unused GPIO pins should either be set for output, or their input levels should be fixed with

pull-up or pull-down resistors. (Avoid connecting them directly to VDD or VSS.

Inadvertently setting output could result in over current flow and destruction of the chip.)

• If the environment contains lots of noise, pins should be provided with external

pull-up/pull-down resistors even if they are provided with internal pull-up/pull-down.

• Pins 76 and 77 are reserved for external circuit connections that will be required with planned

low-cost replacements (a mask ROM version).

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9. ELECTRIC CHARACTERISTICS

9.1 Absolute Maximum Rating (VSS=0V)

Item Symb

ol Condition Rating Unit Not

Supply voltage VDD -0.3 to +4.0 V

Input voltage VI Except FailSafe pin (*1) -0.3 to VDD+0.5 V

FailSafe pin (*1)

-0.3 to +7.0 V

HIGH level output

current IOH 1 pin -10 mA

Total of all pins -40 mA

LOW level output

current IOL 1 pin 10 mA

Total of all pins 40 mA

Storage temperature TSTG -65 to +150 °C

*1: FailSafe pin = HCS#,HA[2:0],HD[15:0],HRD0#,HRD1#,HWR0#,HWR1#,GPIO[7:0],EP_DI

9.2 Recommended Operating Conditions

(VSS=0V)

Item Symb

ol Condition Min. Typ. Max. Unit Note

Supply voltage VDD 3.00

3.60 V

Input voltage VI Except FailSafe pin

(*1) VSS

VDD V

FailSafe pin (*1) VSS

5.5 V 1

CPU operating frequency fCPU

50 MHz

LOW-speed oscillation operating

frequency fOSC1

32.76

kHz

Operating temperature Ta During normal

operation. -40 25 85 °C

When writing to Flash

ROM 0 25 70 °C

Input rise time (normal input) tri

50 ns

Input fall time (normal input) tfi

50 ns

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Fast Ethernet Controller with TCP/IP Stack

Input rise time (Schmitt input) tri

5 ms

Input fall time (Schmitt input) tfi

5 ms

*1: FailSafe pin=HCS#,HA[2:0],HD[15:0],HRD0#,HRD1#,HWR0#,HWR1#,GPIO[7:0],EP_DI

Note : When “HIGH” level output is turned on, don’t apply external voltage HIGHer than the

output voltage to FailSafe pin.

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9.3 DC Characteristics

(Except where otherwise specified: VDD=3.0V to 3.6V, Ta=-40°C to +85°C)

Item Symb

ol Condition Min. Typ. Max. Unit Note

Static current

consumption IDDS Static state, Tj=85°C

120 µA

Large leak current ILI -1

1 µA

Off-state leak current IOZ -1

1 µA

HIGH level output

voltage VOH

IOH=-2mA (Type1),

IOH=-6mA (Type2),

VDD=Min.

VDD

-0.4

LOW level output

voltage VOL IOL=2mA (Type1),

IOL=6mA (Type2), VDD=Min.

0.4 V

HIGH level input

voltage VIH CMOS level, VDD=Max. 2.4

LOW level input

voltage VIL CMOS level, VDD=Min.

0.4 V

Positive trigger input

voltage VT+ CMOS Schmitt, VDD=Max. 1.1

2.4 V

Negative trigger input

voltage VT- CMOS Schmitt, VDD=Min. 0.6

1.8 V

Hysteresis voltage VH CMOS Schmitt 0.1

Pull-up resistor RPU VI=0V Other than

DSIO 80 200 480

kΩ

DSIO 40 100 240 k　

Pull-down resistor RPD VI=VDD (TEST0,TEST1) 40 100 240 k　

Input pin capacitance CI f=1MHz, VDD =0V

10 pF

Output pin capacitance CO f=1MHz, VDD =0V

10 pF

Input/output pin

capacitance CIO f=1MHz, VDD =0V

10 pF

Note: For the characteristics of pins, refer to “Appendix B List of Pin Characteristics”.

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9.4 Current consumption

(Except where otherwise specified: VDD=3.0V to 3.6V, Ta=-40°C to +85°C)

Item Symb

ol Condition Min. Typ. Max. Unit Note

Current consumption IDD1 fCPU=50MHz

100 120 mA 1

When power save mode

turned on

IDD2 fCPU=12.5MHz

80 100 mA 2

When sleep mode is

turned

IDD3 OSC1 oscillation is 32.768kHz

30 120 mA 3

1: When transmission and reception are conducted at the same time by use f internal loop back.

2: OSC3 and OSC1 are operated.

3: OSC3 is stopped and OSC1 is operated.

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9.5 AC Characteristics

9.5.1 Description of Symbols

tCYC: Bus clock cycle time : Depends on OSC3 input value.

When OSC3 input = 25MHz, the internal bus clock = 50MHz : tCYC = 20ns

9.5.2 AC Characteristics Measuring Condition

Signal detection level: Input signal HIGH level VIH=VDD-0.4V

LOW level VIL=0.4V

Output signal HIGH level VOH=1/2 VDD

LOW level VOL=1/2 VDD

Following conditions are assumed when external clock is entered to OSC3

Input signal HIGH level VIH=1/2 VDD

LOW level VIL=1/2 VDD

Input signal waveform: Rise (10%→90%VDD) 5ns

Fall (90%→10%VDD) 5ns

Output load capacitance: CL=50pF

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9.5.3 AC Characteristics Table

 External clock input characteristics

(Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85°C)

Item Symbol Min. Max. Unit Note

HIGH-speed clock cycle time tC3 40 100 ns

OSC3 clock input duty tC3ED 45 55 %

OSC3 clock input rise time tIF

5 ns

OSC3 clock input fall time tIR

5 ns

Minimum reset pulse width tRST 6 tCYC

 Input, output and input/output port

(Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85°C)

Item Symbol Min. Max. Unit Note

Input data setup time tINPS 20

Input data hold time tINPH 10

Output data delay time tOUTD

20 ns

 Host interface

(Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85°C)

Item Symbol Min. Max. Unit Note

Host Interface access enabled period

(HCS#,HA[2:0],HWR0#,HWR1#,

HRD0#,HRD1#)

tHAV 2tCYC+5

Host Interface output data delay time tHOD

25 ns

Host Interface output floating delay

time

tHZD

25 ns

Host Interface interrupt output delay

time

tHIOD

20 ns

Host Interface interrupt floating delay

time

tHIZD

20 ns

Host Interface set input setup time tHIS 10

Host Interface set input hold time tHID 10

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Fast Ethernet Controller with TCP/IP Stack

 MII

(Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to (85(C)

Item Symbol Min. Max. Unit Note

MII output data delay time tTXD 0 15 ns

MII input data setup time tRXS 10

MII input data hold time tRXH 10

MDIO output delay tMOD tCYC tCYC+5 ns

MDIO data setup time tMIS 3

MDIO data hold time tMIH 0

 Serial EEPROM

(Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85°C)

Item Symbol Min. Max. Unit Note

Input data setup time tEIS 15

Input data hold time tEIH 0

Output data delay time tEOD

5 ns

 I

2C bus (Except where otherwise specified:VDD=3.0 to 3.6V,VSS=0V,Ta=-40 to +85°C)

Item Symbol Min. Max. Unit Note

SDA data setup time tIIS 5

SDA output delay time tIOD 5tCYC

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9.5.4 AC Characteristics Timing Chart

 Clock

 Input, output, input/output port

 Host interface (Write)

OSC3

(HIGH

speed clock)

tC3H

tC3

tIF tIR

Internal bus clock

tOUTD

tINPS

GPIO input

GPIO output

tINPH

HCS#

HA[2:0]

HWR0#,HWR1#

HRD0#,HRD1#

HDATA[15:0] Write DATA

Valid Invalid Invalid

Internal bus clock

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Fast Ethernet Controller with TCP/IP Stack

 Host interface (Read)

 Host interface (control line)

 Reset (set input)

 MII transmit

HCS#

HA[2:0]

HWR0#,HWR1#

HRD0#,HRD1#

HDATA[15:0]

Read

DATA

Valid

Invalid

tHOD tHZD

Internal bus clock

tHIS

Internal bus clock

HIFSEL[2:0]

HINTPOL

HWPOL

input

tHIH

RESET#

tHIOD

Internal bus clock

HINT

()

tHIZD

Status/Data Read valid

active

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Fast Ethernet Controller with TCP/IP Stack

MII

TXCLK

tTXD

(

Max.

)

MII_TXD[3:0]

MII TXEN

tTXD

(

Min.

)

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Fast Ethernet Controller with TCP/IP Stack

 MII receive

 MDIO output

 MDIO input

 Serial EEPROM (Read)

tRXS

MII

RXCLK

tRXH

MII_RXD[3:0]

MII_RXDV

MII

MDC

tMIH

MII MDIO

tMIS

MII

MDC

tMOD

MII MDIO

EP DO

EP DI

tEIH

tEIS

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 Serial EEPROM (Write)

 I

2C bus

EP DO

EP DI(Status)

tEOD

SCL

SDA

tIIS

HIGH(Pull

up)

tIOD

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10. PACKAGE

QFP15-100pin : Plastic QFP 100pin Body size 14 × 14 × 1.4mm

Dimension in Millimeters

Symbol Min. Nom. Max.

E 13.9 14 14.1

D 13.9 14 14.1

A 1.7

A1 0.1

A2 1.3 1.4 1.5

e 0.5

b 0.13 0.18 0.28

C 0.1 0.125 0.175

θ 0° 10°

L 0.3 0.5 0.7

L1 1

L2 0.5

HE 15.7 16 16.3

HD 15.7 16 16.3

θ2 12°

θ3 12°

R 0.2

R1 0.2

75 51

100

INDE

L2L1

θ2

θ3

Max.

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∗ Restrictions on Power Consumption

Chip temperature goes higher as power consumption of LSI grows larger. Temperature of LSI

chip in the package is calculated based on its ambient temperature Ta, heat resistance of package

θj-a and power consumption PD as shown below.

Chip temperature (Tj) = Ta + (PD × θj-a) (°C)

In the normal operation, it is recommended to maintain the chip temperature (Tj) below 85°C.

Following shows heat resistance of QFP15-100pin package.

Heat resistance θj-a = 100(°C /W)

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4F, NO.8, HSIN ANN RD., SCIENCE-BASED

INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C.

TEL: 886-3-5799500

FAX: 886-3-5799 558

Email: support@asix.com.tw

Web: http://www.asix.com.tw

Revision Date Comment

V.01 2003/11/1 Initial release