Integrated Silicon Solution, Inc. 1
Rev. D
05/18/2015
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
FEATURES
• VDDandVDDQ:2.5V±0.2V(-6)
• VDDandVDDQ:2.6V±0.1V(-5)
• SSTL_2compatibleI/O
• Double-dataratearchitecture;twodatatransfers
per clock cycle
• Bidirectional,datastrobe(DQS)istransmitted/
received with data, to be used in capturing data
at the receiver
• DQSisedge-alignedwithdataforREADsand
centre-alignedwithdataforWRITEs
• Differentialclockinputs(CKandCK)
• DLLalignsDQandDQStransitionswithCK
transitions
• CommandsenteredoneachpositiveCKedge;
data and data mask referenced to both edges of
DQS
• Fourinternalbanksforconcurrentoperation
• DataMaskforwritedata.DMmaskswritedata
at both rising and falling edges of data strobe
• BurstLength:2,4and8
• BurstType:SequentialandInterleavemode
• ProgrammableCASlatency:2,2.5and3
• AutoRefreshandSelfRefreshModes
• AutoPrecharge
• TRASLockoutSupported(tRAP = tRCD )
OPTIONS
• Conguration(s):16Mx32,32Mx16,and64Mx8
• Package(s):144BallBGA(x32),
66-pinTSOP-II
(x8,x16),and60BallBGA(x8,x16)
• Lead-freepackage
• TemperatureRange:
Commercial(0°Cto+70°C)
Industrial(-40°Cto+85°C)
Automotive,A1(-40°Cto+85°C)
Automotive,A2(-40°Cto+105°C)
16Mx32, 32Mx16, 64Mx8
512Mb DDR SDRAM
MAY 2015
DEVICE OVERVIEW
ISSI’s512-MbitDDRSDRAMachieveshighspeeddata
transfer using pipeline architecture and two data word
accessesperclockcycle.The536,870,912-bitmemory
arrayisinternallyorganizedasfourbanksof128Mbto
allowconcurrentoperations.ThepipelineallowsRead
and Write burst accesses to be virtually continuous, with
theoptiontoconcatenateortruncatethebursts.The
programmable features of burst length, burst sequence
andCASlatencyenablefurtheradvantages.Thedevice
isavailablein8-bit,16-bitand32-bitdatawordsize
InputdataisregisteredontheI/Opinsonbothedges
ofDataStrobesignal(s),whileoutputdataisreferenced
tobothedgesofDataStrobeandbothedgesofCLK.
CommandsareregisteredonthepositiveedgesofCLK.
AnAutoRefreshmodeisprovided,alongwithaSelf
Refreshmode.AllI/OsareSSTL_2compatible.
KEY TIMING PARAMETERS
Speed Grade -5 -6 Units
FckMaxCL=3 200 167 MHz
FckMaxCL=2.5 167 167 MHz
FckMaxCL=2 133 133 MHz
ADDRESS TABLE
Parameter
16M x 32 32M x 16 64M x 8
Configuration
4Mx32x4
banks
8Mx16x4
banks
16Mx8x4
banks
BankAddress
Pins
BA0,BA1 BA0,BA1 BA0,BA1
Autoprecharge
Pins
A8/AP A10/AP A10/AP
RowAddress
8K(A0–A12) 8K(A0–A12) 8K(A0–A12)
Column
Address
512(A0–A7,
A9)
1K(A0–A9) 2K(A0–A9,
A11)
RefreshCount
Com./Ind./A1
A2
8K/64ms
8K/16ms
8K/64ms
8K/16ms
8K/64ms
8K/16ms