IMP16C554-CJ68 - IMP, Inc.

The IMP16C554 is a universal asynchronous receiver and

transmitter with 16 byte transmit and receive FIFO. A

programmable baud rate generator is provided to select

transmit and receive clock rates from 50Hz to 1.5MHz.

The IMP16C554 is an improved version of the IMP16C550

UART with hi gher operating speed and lower acces s time.

The IMP16C554 on board status registers provides the

error conditions, type and status of the transfer operation

being performed. Included is complete MODEM control

capability, and a processor interrupt system that may be

software tailored to the user’s requirements. The

IMP16C554 provides internal loop-back capability for on

board diagnostic test i ng.

The IMP16C554 is fabricated in an advanced 1.2u CMOS

process to achieve low drain power and high speed

 16 byte receive FIFO with error flags

 Modem control signal (CTS*, RTS*, DSR*, DTR*,

RI* ,CD*)

 Programmable character lengths(5,6,7,8)

 Even, odd, or no parity bit generation and detection

 Status report register

 Independent transmit and receive control

 TLL compatible inputs. outputs

 Software compatible with Ei8250, 1Ei16C550

 460.8kHz transmit/receive operation with 7.372

MHz crystal or external cl ock source

IMP16C554

Data Communications

10

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26

DSRA•

CTSA•

DTRA•

VCC

RTSA•

INTA

CSA•

TXA

IOW•

TXB

CSB•

INTB

RTSB•

GND

DTRB

CTSD•

DSRB•

DSRA•

CTSA•

DTRA•

VCC

RTSA•

INTA

CSA•

TXA

IOW•

TXB

CSB•

INTB

RTSB•

GND

DTRB

CTSD•

DSRD•

CTSD•

DTRD•

GND

RTSD•

INTD

CSD•

TXD

IOR•

TXC

CSC•

INTC

RTSC•

VCC

DTRC•

CTSC•

DSRC•

DSRD•

CTSD•

DTRD•

GND

RTSD•

INTD

CSD•

TXD

IOR•

TXC

CSC•

INTC

RTSC•

VCC

DTRC•

CTSC•

CDB•

RIB•

RXB•

VCC

NC

A2

A1

A0

XTAL1

XTAL2

ERSET

RXRDY•

TXRD•

GND

RXC

RIC•

CDC•

DSBS•

CDS•

RIB•

RXB•

VCC

A2

A1

A0

XTAL1

XTAL2

RESET

GND

RXC

RIC•

CDC•

DSRC•

CDA•

RIA•

RXA

GND

D7

D6

D5

D4

D3

D2

D1

D0

INTSEL

VCC

RXD

RID•

CDO•

CDA•

RIA•

RXA

GND

D7

D6

D5

D4

D3

D2

D1

D0

VCC

RXD

RID•

COD•

27

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43

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1

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16C554

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16C554

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33

64-PIN QFP68-PIN PLCC

IMP

requirements.

Description

Key Features

Pin Configuration

Quad Universal Asynchronous

Receiver/Transmitter (UART)

with FIFO's

SYMBOL DESCRIPTION

symbol pin Signal Type Pin Description

D0-D7

RX A-B

RX C-D

TX A-B

TX C-D

CS*A-B

CS*C-D

XTAL1

XTAL2

LOW*

GND

IOR*

5-66

7.29

41.63

17.19

51.53

16.20

50.54

35

36

18

6.23

40.57

52

I/O

I

O

I

O

I

O

I

Bi-directional data bus. Eight bit, three state data bus to

transfer information to or from the CPU. Do is the least

significan t bit of the data b us and the first s erial data bit to be

received or transmitted.

Serial data input. The serial information (data) received from

serial port to IMP16C554 receive input circuit . A mark (high)

is logic one and a space (low)is logic zero. During the local

loopback mode the RX input is disabled from external

connection and to the TX output internally.

Serial data output. The serial data is transmitted via this pin

with additional start, stop and parity bits. The TX will be held

in mark(high) state during reset, local loopback mode or

when the transmitter is disable d.

Chip select. (active low) A low at this pin enables the

IMP16C554/CPU data transfer operation. Each UART sections

of the IMP16C554 can be accessed independently.

Crystal input 1 or external clock input. A crystal can be

connected to this pin and XTAL2 pin to utilize the internal

oscillator circuit. An external clock can be used to clock

internal circuit and baud rate generator for custom

transmission rates.

Crystal input 2 or buffered clock output. See XTAL1.

Write strobe.(active low)A low on this pin will transfer the

contents of the CPU data bus to the addressed register.

Signal and power ground.

Read strobe.(active low)A low level on this pin transfers the

contents of the IMP16C554 data bus to the CPU.

IMP16C554

SYMBOL DESCRIPTION

symbol pin Signal

Type Pin Descrip tion

TXRDY*

A2

A1

A0

RXRDY*

INTSEL

INT A-B

INT C-D

RTS*A-B

RTS*C-D

DTR*A-B

DTR*C-D

39

32

33

34

38

65

15.21

49.55

14.22

48.56

12.24

46.58

O

I

O

I

O

Transmit ready. (active low) This pin goes high when the

transmit FIFO of the IMP16C554 is full. It can be used as a

single or multi-tran sfer.

Address select lin e 2.To select internal regi sters.

Address select lin e 1.To select internal regi sters.

Address select lin e 0.To select internal regi sters.

Receive ready.(active low ) This pin goes low when the

receive FIFO is full. It can be used as a single or

multi-transfer.

Interrupt type select. Enable /disable the interrupt three state

function. Normal interrupt output can be selected by

connecting this pin to VCC(MCR bit-3 does not have any

effect on the interrupt output ).The three state interrupt output

is selected when this pin is left open or connected to GND

and MCR bit-3 is to “1”.

Interrupt output.( active high) this pin goes high (when enable

by the interrupt enable register)whenever a receiver error.

receiver data available. transmitter empty, or modem status

condition flag is dete cte d.

Request to send.(active low) To indicate that the transmitter

has data ready to send .Writing a “1” in the modem control

register(MCR bit-1) will set this pin to a low state. After the

reset this pin will be set to high. Note that this pin does not

have any effect on the transmit or receive operation.

Data terminal ready. (active low) To indicate that IMP16C554 is

ready to receive data. This pin can be controlled via the

modem control register (MCR bit-0).writing a “1” at the MCR

bit-0 will set the DTR* output to low.

IMP16C554

SYMBOL DESCRIPTION

symbol pin Signal Type Pin Description

RESET

CTS*A-B

CTS*C-D

DSR*A-B

DSR*C-D

CD*A-B

CD*C-D

RI*A-B

RI*C-D

37

11.25

45.59

10.26

44.60

9.27

43.61

8.28

42.62

I

This pin will be set to high state after writing a “0” to that

register or after the reset. Note that this pin does not

have any effect on the transmit or receive operation.

Master reset.(active high)A high on this pin will reset all

the outputs and internal registers. The transmitter

output and the receiver input will be disabled during

reset time.

Clear to send. (active low) The CTS* signal is a

MODEM control function input whose conditions can be

tested by reading the MSR BIT-4. CTS* has no effect

on the transmit or receive operation.

Data set ready. ( active low) A low on this pin indicates

the MODEM is ready to exchange data with UART. This

pin does not have any effect on the transmit or receive

operation.

Carrier detect.(active low) A low on this pin indicates the

carrier has been detected by the modem.

Ring detect indicator. ( active low) A low on this pin

indicates the modem has received a ringing signal from

telephone line.

Power supply input.

VCC

13.30

47.64

I

IMP16C554

IMP16C554 ACCESSIBLE REGISTERS

A2A1A0 Registe

r BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0

0 0 0 RHR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2

bit-1 bit-0

0 0 0 THR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0

0 0 1 IER 0 0 0 0 Modem

status

interrup

t

Receiv

e line

status

interru

pt

Transmi

t

holding

register

Receive

holding

register

0 1 0 FCR RCV

R

trigge

r

(MSB

)

RCV

R

trigge

r

(LSB)

0 0 DMA

Mode

select

XMITF

IFO

reset

RCVRF

IFO

reset

FIFO

enable

0 1 0 ISR 0/FIF

Os

enabl

ed

0/FIF

Os

enabl

ed

0 0 int

priority

bit-2

Int

priority

bit-1

Int

priority

bit-0

Int

status

0 1 1 LCR Divis

or

latch

enabl

e

Set

break Set

parity Even

parity Parity

enable Stop

bits Word

length

bit-1

Word

length

bit-0

1 0 0 MCR 0 0 0 Loop

back INT

enable Not

used RTS* DTR*

1 0 1 LSR o/FIF

O

error

trans

empt

y

trans

holdi

ng

empt

y

break

interr

upt

framing

error parity

error overrun

error receive

data

ready

1 1 0 MSR CD RI DSR CTS delta

CD* delta

RI* delta

DSR* delta

CTS*

1 1 1 SPR bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0

0 0 0 DLL bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0

0 0 1 DLM bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8

DLL and DLM are accessible only when LCR bit-7 is set to “1”.

IMP16C554

PROGAMMING TABLE

A2 A1 A0 READ MODE WRITE MODE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding

Register

Interrupt Status

Register

Line Status Register

Modem Status Register

Scratchpad Register

Transmit Holding

Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

Scratchpad Register

LSB of Divisor Latch

MSB of Divisor Latch

REGISTER FUNCTIONAL DESCRIPTIONS

TRANSMIT AND RECEIVE HOLDING

REGISTER

The serial transmitter section consists of a

Transmit Hold Register (THR) and Transmit

Shift Register (TSR).T he s tatus of the tr ansmit

hold register is provided in the Line status

Register(LSR).Writing to this register

(THR)will transfer the contents of data

bus(D7-D0) to the Transmitter shift register is

empty. The transmit holding register empty

flag will be set to “1” when the transmitter is

empty or data is transferred to the transmit

shift register. Note that a write operation

should be performed when the transmit

holding register empty flag is set.

On the falli ng ed ge of the s tart bit. th e rec ei ver

internal counter will start to count 7 1 /2 clock s

(16x clock) which is the ce nter of the start bit.

The s tart bit is valid if the RX is still low at the

mid-bit sample of the start bit. Verifying the

start bit prev ents t he r ec e iver f r om as sembling

a false data character due to a low going

noise spike on the RX input. Receiver status

codes will be posted in the Line Status

Register.

FIFO INTERRUPT MODE OPERATION

When the receive FIFO (FCR BIT-0=1) and

receive interrupts (IER BIT-0=1) are enabled.

receiver interrupt will occur as follows.

A)The receive data available interrupts will be

issued to the CPU when the FIFO has

reached its progr amm ed tr igger level ; it will be

cleared as soon as the FIFO drops below its

programmed trigger level.

B)The ISR receive data available indication

also occurs when the FIFO trigger level is

reached, and like the interrupt it is cleared

when the FIFO dorps below the trigger level.

C)The data ready bit (LSR BIT-0) is set as

soon as a character is transferred from the

shift register to the receiver FIFO. It is reset

when the FIFO is em pt y.

FIFO POLLED MODE OPERATION

When FCR BIT-0=1;resetting IER BIT 3-0 to

zero puts the IMP16C554 in the FIFO polled

mode of operation. Since the receiver and

IMP16C554

transmitter are controlled separately either

one or both can in the polled mode operation

by utilizing the Lin e status Regist er.

A) LSR BIT-0 will be set as long as there is

one byte in the receive FIFO.

B) LSR BIT 4-1 will spec ify whi ch error( s) has

occurred.

C) LSR BIT-5 will indicate when the

transmit FIFO is empty.

D) LSR BIT-6 will indicate when both transmit

FIFO and transmit shift register are empty.

E) LSR BIT-6 will indicate when there are

any errors in the receive FIFO.

The MS16C554 requires to have two step FIFO

enable operation in order to enable receive trigger

levels.

PROGRA MM ABLE BA UD RATE

GENERATOR

The IMP16C554 contains a programmable Baud

Rate Generator that is capable of taking any

clock input fr om DC-24 MHz and dividing it b y

any divisor from 1 to 216-1.The output

frequency of the Baud out* is equal to 16X of

transmission baud rate (Baudout*=16 x Baud

Rate). Customize Baud Rates can be

achieve d b y se lec ti ng proper div isor v alu es f or

MSB and LSB of baud rate generator.

INTERRUPT ENA BLE REGISTER (IER)

The interr upt Ena ble Regis ter ( IER) masks the

incoming interrupts from receiver ready,

transmitter empty, line status and modem

status registers to the INT output pin.

IER BIR-0

0=disable the receiver ready interrupt.

1=enable the receiver ready interrupt.

IER BIR-1

0=disable the transmitter empty interrupt.

1=enable the tr ans mitter em pt y interrupt.

IER BIR-2

0=disable the receiver line status interrupt.

1=enable the receiver line status interrupt.

IER BIR-3

0=disable the modem status register interrupt.

1=enable the modem status register interrupt.

IER BIR7-4

All these bits are set to logic zero.

INTERRUPT STATUS REGISTER (ISR)

The IMP16C554 provides four level prioritized

interrupt conditions to minimize software

overhead during data charac ter transfers . The

interrupt Status Register (ISR) provides the

source of the interrupt in prioritized matter.

During the read cycle the IMP16C554 provides

the highest interrupt level to be serviced by

CPU. No other interrupts are acknowledged

until the particular interrupt is serviced. The

following sre the prioritized interrupt levels:

Priori t y le ve l

P D3 D2 C1 D0 Source of the

interrupt

1

2

2*

3

4

0

1

0

1

0

1

0

1

0

LSR (Receiver Line

Status Register)

RXRDY (Received

Data Ready)

RXRDY (Received

Data time out)

TXRDY (Transmitter

Holding Register

Empty)

MSR (Modem Status

Register)

*RECEIVE TIME-OUT:

This mode is enabled when the

UART is operating in FIFO mode. Receive

time out will not occur if the receive FIFO is

empty. The time out counter will be reset at

the center of each stop bit received or each

time out value is T (Time out length in bits)=4

X P (Programmed word length)+12. To

convert time out value to a character value,

user has t o divide this num ber to its complete

word length + parity (if used)+number of stop

bits and start bit.

Example-A: if user programs the word

length=7,and no parity and one stop bit. Time

out will be:T=4x7(programmed word

length)+12=40 bits Character time =40 / 9

 (programmed word length=7)+(stop

bit=1)+(s tart bi=1)=4.4 character s.

Example-B: if user programs the word

length=7, with parity and one stop bit, the tim e

out will be: T=4x7 (programmed word

length)+12=40 bits Character time =40 / 10

(programmed word length=7) + (parity=1) +

IMP16C554

(stop bit=1) + (start bi=1) =4 characters.

ISR BIT-0:

0=an interrupt is pending and the ISR

contents may be used as a pointer to the

appropriate interrupt service routine.

1=no interrupt pending.

ISR BIT 1-3:

Logical c ombinat ion of thes e bits, provides th e

highest priority interrupt pending.

ISR BIT 4-7:

Thes e bits are not us ed and are set to zero in

MS16C450 mode. BIT 6-7:are set to “1” in

MS16C554 mode.

FIFO CONTROL REGISTER (FCR)

This register is used to enable the FIFOs,

clear the FIFOs, set the receiver FIFO trigger

level, and select the type of DMA signaling.

FCR BIT-0:

0=Diosable the transmit and receive FIFO.

1=Enable the transmit and receive FIFO.

This is bit should be enabled before setting

the FIFO trigger levels.

FCR BIT-1:

0=No change.

1=Clears the contents of receive FIFO and

resets its count er log ic to 0 ( the recei ve s hift

register is not cleared or altered). This bit will

return to zero after clearing the FIFOs.

FCR BIT-2:

0=No change.

1=Clears the contents of the transmit FIFO

and resets its counter logic to 0 (the transmit

shift regist er is not c leared or altered). T his bit

will return to zero after clearing the FIFOs.

FCR BIT-3:

0=No change.

1= Changes RXRDY and TXRDY pins from

mode “0” to mode “1”.

Transmit operation in mode “0”:

When IMP16C554 is in MS16C450 mode

(FCR bit-0=0) or in the FIFO mode (FCR

bit-0=1,FCR bit-3=0) when there are no

characters in the transmit FIFO or transmit

holding register, the TXRDY* pin will go low.

Once active the TXRDY* pin will go high

(inactive) after the f ir st c har acter is loa ded int o

the transmit holding register.

Receive operation in mode “0”:

When IMP16C554 is in IMP16C450 mode (FCR

bit-0=0) or in the FIFO mode (FCR

bit-1=1,FCR bit-3=0) and there is at least 1

character in the receive FIFO, the RXRDY*

pin will go low. Once active the RXRDY* pin

will go hi gh (inactive) when there ar e no more

characters in the receiver.

Transmit operation in mode “1”:

When IMP16C554 is in IMP16C550 mode (FCR

bit-0=1,FCR bit-3=1) the TXRDY* pin will

become high (inactive) when the transmit

FIFO is completely full. It will be low if one or

more FIFO locations are empty.

Receive operation in mode “0”:

When IMP16C554 is in IMP16C550 mode (FCR

bit-0=1,FCR bit-3=1) and the trigger level or

the timeout has been reached, the RXRDY*

pin will go low. Once it is activated it will go

high (inactive) when are no more characters

in the FIFO.

FCR BIT 4-5:

Not used.

FCR BIT 6-7:

These bits are used to set the trigger level for

the receiver FIFO interrupt.

BIT-7 BIT-6 FIFO trigger level

0

1

0

1

0

1

01

04

08

14

LINE CONTROL REGISTER (LCR)

The Line Control Register is used to specify

the asynchro nous data com munic ation form at.

The number of the word length, stop bits,

and parity can be selected by writing

appropriate bits in this register.

LCR BIT1-0:

These two bits specify the word length to be

transmitted or received.

BIT-1 BIT-0 Word length

0

1

0

1

0

5

6

7

IMP16C554

1 1 8

LCR BIT-2:

The number of stop bits can specified by this

bit.

BIT-2 Word length Stop bit(s)

0

1

5, 6, 7

5

6, 7, 8

1

1-1/2

2

LCR BIT-3:

Parity or no parity can be selected via this bit.

0= no parity

1=a parity bit is generated during the

transmission.

receiver also checks for received parity.

LCR BIT-4:

If the parity bit is enabled, LCR BIT-4 selects

the even or odd parity format.

0= ODD parity bit is generated by forcing an

odd number of 1`s in the transmitted data,

receiver also checks for same format.

1=EVEN parity bit is generated by forcing an

even number of 1`s in the transmitted data,

receiver also checks for same format.

LCR BIT-5:

If the parity bit is enabled, LCR BIT-5 selects

the forced parity format.

LCR BIT-5=1 and LCR BIT-4=0, parity bit is

forced to “1” in the transmitted and received

data.

LCR BIT-5=1 and LCR BIT-4=1, parity bit is

forced to “0” in the transmitted and received

data.

LCR BIT-6:

Break control bit. It causes a break condition

to be transmitted (the TX is forced to low

state).

0= normal operating condition.

1=forces the transmitter output (TX) to go low

to alert the communication terminal.

LCR BIT-7:

The internal baud rate counter latch enable

(DLAB).

0=normal operation.

1=select di visor latch register.

MODEM CONTROL REGISTER (MCR)

This register controls the interface with the

MODEM or a peripheral device (RS232).

MCR BIT-0:

0=force DTR* output to high.

1=force DTR* output to low.

MCR BIT-1:

0=force RTS* output to high.

1=force RTS* output to low.

MCR BIT-2:

No used, except in int erna l loo p- back mode.

MCR BIT-3:

0=set the INT A-D output pin to three state

mode.

1=Enable the INT A-D output pin.

MCR BIT-4:

0=normal operation mode.

1=enable local loop-back mode (diagnostics).

The transmitter output (TX) is set high (Mark

condition), the receiver input (RX), CTS*,

DSR*, CD*, and RI* are disabled. Internally

the transmitter output is connected to the

receiver input and DTR*, RTS*, MCR* bit-2

and INT enable are connected to modem

control inp uts.

In this mode, the receiver and transmitter

interrupts are fully operational. The Modem

Control i nterrupts are a lso operat ional. but the

interrupts sources are now the lower four bits

of the Modem Control Register instead of the

four Modem Control inputs. The interrupts are

still controlled by the IER.

MCR BIT 5-7:

Not used. Are set to zero p ermanentl y.

LINE STATUS REGISTER (LSR)

This register provides the status of data

transfer to CPU.

LSR BIT-0:

0=no data in receive holding register or FIFO.

1=data has been received and saved in the

receive holding register or FIFO.

LSR BIT-1:

0=no overrun error (normal).

1= overrun error , next character arrived

before r ec eive ho lding reg i st er was emptied or

if FIFOs are enabled. an overrun error will

occur only after the FIFO is full and the next

character has been c om pletel y rece ived in the

shift register. Note that character in the shift

register is over wri tten, but it is not transf erred

to the FIFO.

IMP16C554

LSR BIT-2:

0=no parity error (normal).

1= parity error, received data does not have

correct parity information. In the FIFO mode

this error is associated with the character at

the top of the FIFO.

LSR BIT-3:

0=no framing error (normal).

1=framing error received, received data did

not have a valid stop bit. In the FIFO mode

this error is associated with the character at

the top of the FIFO.

LSR BIT-4:

0=no break condition (normal).

1=receiver received a break signal (RX was

low for one character time frame). In FIFO

mode, only one zero character is loaded into

the FIFO.

LSR BIT-5:

0=transmit holding register is full. IMP16C554

will not accept any data for transmission.

1= trans m it holding reg ister (or FIFO ) is em pt y.

CPU can load the next character.

LSR BIT-6:

0=transmit holding register and shift register

are full.

1=transmit holding register and shift register

are empty. I n FIFO mode t his bit is set t o one

whenever the transmitter FIFO and transmit

shift register are empty.

LSR BIT-7:

0= Normal.

1= At least one parity error, framing error or

break indication in the FIFO. This bit is

cleared when LSR is read.

MODEM STATUS REGISTER (MSR)

This register provides the current state of the

control lines from the modem or peripheral to

the CPU. Four bits of this register are used to

indicate the changed information. These bits

are set to “1” whenever a control input from

the MODEM changes state. They are set to

“0” whenever the CPU reads this register.

MSR BIT-0:

Indicates that the CTS* input to the IMP16C554

has changed state since the last time it was

read.

MSR BIT-1:

Indicates that the DSR* input to the IMP16C554

has changed state since the last time it was

read.

MSR BIT-2:

Indicates that the RI* input to the IMP16C554

has changed from a low to a high state.

MSR BIT-3:

Indicates that the CD* input to the ST16C554

has changed state since the last time it was

read.

MSR BIT -4

This bit is equivalent to RTS in the MCR

during local loop-back mode. It is the

compliment of the CTS* input.

MSR BIT-5:

This bit is equivalent to DTR in the MCR

during local loop-back mode. It is the

compliment of the DSR* input.

MSR BIT-6:

This bit is equiva le nt to M CR bi t-2 d uring local

loop-back mode. It is the compliment of the

RI* input.

MSR BIT-7:

This bit is equivalent to INT enable in the

MCR during local loop-back mode. It is the

compliment of the CD* input.

Note: whenever MSR BIT3-0: is set to logic

“1”, a MODEM Status Interrupt is generated.

SCRATCHPAD REGISTER (SR)

IMP16C554 provides a temporary data register

to store 8 bits of information for variable use.

BAUD RATE GENERATOR PROGRAMMING

TABLE (1.8432 MHz CLOCK):

BAUD

RATE 16 x CLOCK

DIVISOR % ERROR

50

110

150

300

600

1200

2400

4800

7200

9600

2304

1047

768

384

192

96

48

24

16

12

0.026

IMP16C554

19.2K

38.4K

56K

115.2K

6

3

2

1

2.77

IMP16C554 EXTERNAL RESET CONDITION

REGISTER

RESET STATE

IER

ISR

LCR

MCR

LSR

IER BIT 0-7=0

ISR BIT-0=1, ISR BIT 1-7=0

LCR BITS 0-7=0

MCR BITS 0-7=0

LSR BITS 0-4=0,

LSR BITS 5-6=1 LSR,BIT

MSR

FCR

7=0

MSR BITS 0-3=0,

MSR BITS 4-7=input signals

FCR BIT 0-7=0

SIGNALS RESET STATE

TX A-D

RTS* A-D

DTR* A-D

RXRDY*

TXRDY*

INT A-D

High

Low

Three state mode

AC ELECT RIC AL CHARACT ERIST ICS

TA=0 –700C,Vcc= 5.0V±10% unless otherwise specified

Symbol Parameter Limits

Min Typ Max Units Conditions

T1

T2

T3

T8

T9

T12

T13

T14

T15

T16

T17

Tw

T19

T21

T23

T24

T25

Tr

T26

T28

T29

T30

T31

T32

T33

T34

T35

T44

T45

T46

T47

N

Clock high pulse duration

Clock low pulse duration

Clock rise/fall time

Chip select setup time

Chip setup time

Data setup time

Data hold time

IOW* delay from chip select

IOW* strobe width

Chip select hold time from IOW*

Write cycle delay

Write cycle =T15+T17

Data hold time

IOR* delay from chip select

IOR* strobe width

Chip select hold time from LOR*

Read cycle delay

Read cycle =T23+T25

Delay from IOR* to data

Delay from IOW* to output

Delay to set interrupt from MODEM

input

Delay to reset interrupt from IOR*

Delay from stop to set interrupt

Delay from IOR* to reset interrupt

Delay from initial INT reset to transmit

start

Delay from stop to interrupt

Delay from IOW* to reset interrupt

Delay from stop to set RxRdy

Delay from IOR* to reset RxRdy

Delay from IOW* to set TxRdy

Delay from start to reset TxRdy

Baud rate devisor

20

5

0

15

10

50

0

55

105

15

10

65

0

55

115

8

1

10

25

35

50

70

1Rck

200

24

100

175

1RCL

K

1

195

8

216-1

ns

*

ns

us

ns

*

100 pF load

Note 1: = Baudout cycle

IMP16C554

ABSOLUTE MAXIMUM RATINGS

Supply range 7 Volts

Voltage at any pin GND-0.3 V to VCC+0.3 V

Operating temperature 00C to +700 C

Storage temperature -400 C to 1500 C

Package dissipation 500 Mw

DC ELECTRICAL CHARACTERISTICS

TA=0*-70* C, Vcc= 5.0 V ±10% unless otherwise specified.

symbol Parameter

Limits

Min Typ Max Units

conditions

VILCK

VIHCK

VIL

VIH

VOL

VOH

ICC

IIL

ICL

VILCK

VIHCK

VIL

VIH

VOL

VOH

ICC

Clock input low level

Clock input high le vel

Input low level

Input high level

Output low level on all outputs

Output high le vel

Avg power supply current

Input leakage

Clock leakage

Clock input low level

Clock input high le vel

input low level

input high level

Output low level on all outputs

output high level

Avg power supply current

-0.5

3.0

-0.5

2.2

2.4

-0.3

2.4

-0.3

2.0

6

10

0.6

vcc

0.8

vcc

0.4

14

±10

0.8

vcc

0.8

vcc

0.4

12

V

mA

uA

V

mA

LOL=6 mA

LOH=-6 mA

VCC=3.0 V

V CC =3.0 V

Vcc=3.0V

VCC=3.0V,

loL=8.5 mA

VCC=3.0V,

loH=-4 mA

VCC=3.0 V

IMP16C554

A0-A2

CSx*

IOR*

D0-D7

T8 T9

T21 T23 T24 T25

T26 T19

162450-RD-1

A0-A2

CSx*

IOW*

D0-D7

T8 T9

T14 T15 T16 T17

T13

162450-WD-1

T12

IMP16C554

FIGURE 1 - GENERAL READ TIMING

FIGURE 2 - GENERAL WRITE TIMING

IOW*

RTS*

DTR*

CD

CTS

DSR

INTx

IOR*

RI

T28

T29 T29

T30 T29

162450-MD-1

T2

EXTERNAL

CLOCK

CLOCK PERIOD CLOCK PERIOD

T1

T3

161450-CK-1

IMP16C554

FIGURE 4 - CLOCK TIMING

FIGURE 3 - MODEM TIMING

TX

INTx

IOW*

5 DATA BITS

6 DATA BITS

7 DATA BITS

PARITY BIT NEXT

DATA

START BIT

T34

T33

T35

162450-TX-116 BAUD RATE CLOCK

D0 D1 D2 D3 D4 D5 D6 D7

IMP16C554

FIGURE 5

5 DATA BITS

6 DATA BITS

7 DATA BITS

PARITY BIT

D0 D1 D2 D3 D4 D5 D6 D7

START BIT

RX

(First byte)

RXRDY*

IOR*

T44

T45

16552-RX-2

IMP16C554

FIGURE 6 - RXRDY TIMING FOR MODE "0"

5 DATA BITS

6 DATA BITS

7 DATA BITS

PARITY BIT

D0 D1 D2 D3 D4 D5 D6 D7

START BIT

RX

RXRDY*

IOR*

T44

T45

16552-RX-3

First byte that reaches

the trigger level

IMP16C554

FIGURE 7 - RXRDY TIMING FOR MODE "1"

RX

INTx

IOR*

5 DATA BITS

6 DATA BITS

7 DATA BITS

PARITY BIT NEXT

DATA

START BIT

T31

T32

162450-RX-116 BAUD RATE CLOCK

D0 D1 D2 D3 D4 D5 D6 D7

IMP16C554

FIGURE 8 - RECEIVE TIMING

5 DATA BITS

6 DATA BITS

7 DATA BITS

PARITY BIT

D0 D1 D2 D3 D4 D5 D6 D7

START BIT

TX

IOW*

D0-D7

TXRDY*

BYTE#1

T46 T47

16552-TX-2

IMP16C554

FIGURE 9 - TXRDY TIMING FOR MODE "0"

Ordering Information

Part Number Package Operating Temperature

IMP16C554-CJ68 PLCC 68pins 0 to +70

IMP16C554-LJ68 PLCC 68pins -40 to +85

Life Support Policy: IMP’s products are not to be used in life support devices without

prior written authorization.

IMP Retains the right to make changes to these specifications at any

time without notice.

5 DATA BITS

6 DATA BITS

7 DATA BITS

PARITY BIT

D0 D1 D2 D3 D4 D5 D6 D7

START BIT

TX

IOW*

D0-D7

TXRDY*

BYTE#16

T46 T47

FIFO FULL

16552-TX-3

IMP16C554

FIGURE 10 - TXRDY TIMING FOR MODE "1"