Description
PBM 3960/1 is a dual 7-bit+sign, Digital-to-Analog Converter (DAC) especially
developed to be used together with the PBL 3771/1, Precision Stepper Motor driver
in micro-stepping applications. The circuit has a set of input registers connected to an
8-bit data port for easy interfacing directly to a microprocessor. Two registers are
used to store the data for each seven-bit DAC, the eighth bit being a sign bit (sign/
magnitude coding). A second set of registers are used for automatic fast/slow current
decay control in conjunction with the PBL 3771/1, a feature that greatly improves
high-speed micro-stepping performance. The PBM 3960/1 is fabricated in a high-
speed CMOS process.
Key Features
• Analog control voltages from 3 V
down to 0.0 V.
• High-speed microprocessor interface.
• Automatic fast/slow current decay
control.
• Full-scale error ±1 LSB.
• Interfaces directly with TTL levels and
CMOS devices.
• Fast conversion speed, 3 µs.
• Matches PBL 3771.
PBM 3960/1
Microstepping Controller/
Dual Digital-to-Analog Converter
February 1999
Figure 1. Block Diagram.
22-pin plastic DIP
28-pin plastic PLCC
V
DD
V
Ref
CS
A0
A1
WR
D7 - D0
RESET
Vss
Sign2
CD2
DA2
Sign1
CD1
DA1
E
CD
R
E
CD
E
CD
R
R
E
CD
R
Digit
Comp
Digit
Comp
E
CD
R
E
CD
R
D / A
D / A
E1
E2
E3
E4
POR
E1
E4
PBM 3960/1
DA- Data 1
DA- Data 2
Level 1
Level 2
R
PBM3960/1
PBM
3960/1
PBM 3960/1
2
Maximum Ratings
Parameter Pin no. * Symbol Min Max Unit
Voltage
Supply 5 VDD 6V
Logic inputs 6- 17 VI-0.3 VDD+ 0.3 V
Reference input 1 VR-0.3 VDD+ 0.3 V
Current
Logic inputs 6- 17 II-0.4 +0.4 mA
Temperature
Storage temperature TS-55 +150 °C
Operating ambient temperature TJ-20 +85 °C
* refers to DIP package
Recommended Operating Conditions
Figure 2. Timing.
Figure 3. Timing of Reset.
t
t
tt
t
tt
CS
A0-A1
D0-D7
WR
DA
Sign, CD
cs ch
as ah
ds dh
WR
t
DAC
t
pwr
t
t
Reset
Sign, CD
res
pres
Parameter Symbol Min Typ Max Unit
Supply voltage VDD 4.75 5.0 5.25 V
Reference voltage VR0 2.5 3.0 V
PBM 3960/1
3
Electrical Characteristics
Electrical characteristics over recommended operating conditions.
Ref.
Parameter Symbol fig Conditions Min Typ Max Unit
Logic Inputs
Reset logic HIGH input voltage VIHR 3.5 V
Reset logic LOW input voltage VILR 0.1 V
Logic HIGH input voltage VIH 2.0 V
Logic LOW input voltage VIL 0.8 V
Reset input current IIR VSS < VIR < VDD -0.01 1 mA
Input current, other inputs IIVSS < VI < VDD -1 1 µA
Input capacitance 3pF
Internal Timing Characteristics
Address setup time tas 2 Valid for A0, A1 60 ns
Data setup time tds 2 Valid for D0 - D7 60 ns
Chip select setup time tcs 270ns
Address hold time tah 20ns
Data hold time tdh 20ns
Chip select hold time tch 20ns
Write cycle length tWR 250ns
Reset cycle lenght tR380ns
Reference Input
Input resistance RRef 69 kΩ
Logic Outputs
Logic HIGH output current IOH VO = 2.4 V -13 -5 mA
Logic LOW output current IOL VO = 0.4 V 1.7 5 mA
Write propagation delay tpWR 2 From positive edge of WR. 30 100 ns
outputs valid, Cload = 120 pF
Reset propagation delay tpR3 From positive edge of Reset to 60 150 ns
outputs valid, Cload = 120 pF
DAC Outputs Reset open, VRef = 2.5 V
Nominal output voltage VDA 0V
Ref- 1LSB V
Resolution 7 Bits
Offset error 7 0.2 0.5 LSB
Gain error 7 0.1 0.5 LSB
Endpoint nonlinearity 7 0.2 0.5 LSB
Differential nonlinearity 5, 6 0.2 0.5 LSB
Load error (VDA, unloaded - VDA, loaded) 0.1 0.5 LSB
Rload = 2.5 kΩ, Code 127 to DAC
Power supply sensitivity Code 127 to DAC 0.1 0.3 LSB
4.75 V < VDD < 5.25 V
Conversion speed tDAC 2 For a full-scale transition to ±0.5 LSB 3 8 µs
of final value, Rload = 2.5 kohm, Cload = 50 pF.
PBM 3960/1
4
Figure 4. Pin configuration.
Pin Descriptions
Refer to figure 4.
DIP PLCC Symbol Description
19V
Ref Voltage reference supply pin, 2.5 V nominal (3.0 V maximum)
210DA
1Digital-to-Analog 1, voltage output. Output between 0.0 V and VR - 1 LSB.
3 12 Sign1Sign 1, TTL/CMOS level. To be connected directly to PBL 3771 Phase input.
Databit D7 is transfered non inverted from PBM 3960/1/1 data input.
413CD
1Current Decay 1, TTL/CMOS level. The signal is automatically generated when
decay level is programmed. LOW level = fast current decay.
514V
DD Voltage Drain-Drain, logic supply voltage. Normally +5 V.
6 15 WR Write, TTL/CMOS level, input for writing to internal registers.
Data is clocked into flip flops on positive edge.
7 16 D7 Data 7, TTL/CMOS level, input to set data bit 7 in data word.
8 17 D6 Data 6, TTL/CMOS level, input to set data bit 6 in data word.
9 19 D5 Data 5, TTL/CMOS level, input to set data bit 5 in data word.
10 20 D4 Data 4, TTL/CMOS level, input to set data bit 4 in data word.
11 21 D3 Data 3, TTL/CMOS level, input to set data bit 3 in data word.
12 23 D2 Data 2, TTL/CMOS level, input to set data bit 2 in data word.
13 24 D1 Data 1, TTL/CMOS level, input to set data bit 1 in data word.
14 25 D0 Data 0, TTL/CMOS level, input to set data bit 0 in data word.
15 27 A0 Address 0, TTL/CMOS level, input to select data transfer,
A0 selects between cannel 1 (A0 = LOW) and channel 2 (A0 = HIGH).
16 28 A1 Address 1, TTL/CMOS level, input to select data transfer. A1 selects between normal
D/A register programming (A1 = LOW) and decay level register programming (A1 = HIGH).
17 1 CS Chip Select, TTL/CMOS level, input to select chip and activate data transfer
from data inputs. LOW level = chip is selected.
18 2 VSS Voltage Source-Source. Ground pin, 0 V reference for all signals and
measurements unless otherwise noted.
19 3 CD2Current Decay 2, TTL/CMOS level. The signal is automatically generated
when decay level is programmed. LOW level = fast current decay .
20 4 Sign2Sign 2. TTL/CMOS level. To be connected directly to PBL 3771 sign input.
Data bit D7 is transfered non-inverted from PBM 3960/1 data input.
21 6 DA2Digital-to-Analog 2, voltage output. Output between 0.0 V and Vref - 1 LSB.
22 7 Reset Reset, digital input resetting internal registers.
HIGH level = Reset, VRes ≥ 3.5 V = HIGH level. Pulled low internally.
5 Not Connected
8 Not Connected
11 Not Connected
18 Not Connected
22 Not Connected
26 Not Connected
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
ref
DA
1
1
V
Reset
CS
V
Sign
CD
SS
1
PBM
3960/1N
DD
WR
D7
D6
D5
D4
D3 D2
D1
D0
A1
A0
V
2
CD
2
Sign
DA
2
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4
3
2
1
28
27
26
12
13
14
15
16
17
18
PBM
3960/1QN
ref
DA
1
1
V
V
Sign
CD
1
DD
WR
D7
D6
D5
D4
D3
Reset
CS
SS
D2
D1
D0
A1
A0
V
2
CD
2
Sign
DA
2
N/C
N/C
N/C
N/C
N/C N/C
PBM 3960/1
5
Figure 6. Errors in D/A conversion.
Differential non-linearity of less than 1 bit,
output is monotonic.
Figure 5. Errors in D/A conversion.
Differential non-linearity of more than 1
bit, output is non-monotonic.
Figure 7. Errors in D/A conversion. Non-
linearity, gain and offset errors.
More
than 2
bits
Negative
difference
Output
Input
Less
than 2
bits
Positive
difference
Output
Input
Endpoint
non-linearity
Offset error
Actual Gain
error
Output
Input
Full scale
Correct
Definition of Terms
Resolution
Resolution is defined as the reciprocal of
the number of discrete steps in the DAC
output. It is directly related to the
number of switches or bits within the
DAC. For example, PBM 3960/1 has 27,
or 128, output levels and therefor has 7
bits resolution. Remember that this is
not equal to the number of microsteps
available.
Linearity Error
Linearity error is the maximum deviation
from a straight line passing through the
end points of the DAC transfer
characteristic. It is measured after
adjusting for zero and full scale.
Linearity error is a parameter intrinsic to
the device and cannot be externally
adjusted.
Power Supply Sensitivity
Power supply sensitivity is a measure of
the effect of power supply changes on
the DAC full-scale output.
Settling Time
Full-scale current settling time requires
zero-to-full-scale or full-scale-to-zero
output change. Settling time is the time
required from a code transition until the
DAC output reaches within ±1/2LSB of
the final output value.
Full-scale Error
Full-scale error is a measure of the
output error between an ideal DAC and
the actual device output.
different levels for initiation of fast
current decay can be selected.
The sign outputs generate the phase
shifts, i.e., they reverse the current
direction in the phase windings.
Data Bus Interface
PBM 3960/1 is designed to be compat-
ible with 8-bit microprocessors such as
the 6800, 6801, 6803, 6808, 6809, 8051,
8085, Z80 and other popular types and
their 16/32 bit counter parts in 8 bit data
mode. The data bus interface consists of
8 data bits, write signal, chip select, and
two address pins. All inputs are TTL-
compatible (except reset). The two
address pins control data transfer to the
four internal D-type registers. Data is
transferred according to figure 10 and on
the positive edge of the write signal.
Current Direction, Sign1 & Sign2
These bits are transferred from D7 when
writing in the respective DA register. A0
and A1 must be set according to the data
transfer table in figure 10.
Current Decay, CD1 & CD2
CD1 and CD2 are two active low signals
(LOW = fast current decay). CD1 is
active if the previous value of DA-Data1
is strictly larger than the new value of
DA-Data1 and the value of the level
register LEVEL1 (L61 … L41) is strictly
larger than the new value of DA-Data1.
CD1 is updated every time a new value
is loaded into DA-Data1. The logic
definition of CD1 is:
CD1 = NOT{[(D6 … D0) < (Q61 … Q01)]
AND[(D6 …D4) < (L61 … L41)]}
Differential Non-linearity
The difference between any two
consecutive codes in the transfer curve
from the theoretical 1LSB, is differential
non-linearity
Monotonic
If the output of a DAC increases for
increasing digital input code, then the
DAC is monotonic. A 7-bit DAC which is
monotonic to 7 bits simply means that
increasing digital input codes will
produce an increasing analog output.
PBM 3960/1 is monotonic to 7 bits.
Functional Description
Each DAC channel contains two
registers, a digital comparator, a flip flop,
and a D/A converter. A block diagram is
shown on the first page. One of the
registers stores the current level, below
which, fast current decay is initiated.
The status of the CD outputs determines
a fast or slow current decay to be used
in the driver.
The digital comparator compares
each new value with the previous one
and the value for the preset level for fast
current decay. If the new value is strictly
lower than both of the others, a fast
current decay condition exists. The flip
flop sets the CD output. The CD output
is updated each time a new value is
loaded into the D/A register. The fast
current decay signals are used by the
driver circuit, PBL 3771/1, to change the
current control scheme of the output
stages. This is to avoid motor current
dragging which occurs at high stepping
rates and during the negative current
slopes, as illustrated in figure 9. Eight
PBM 3960/1
6
Where (L62 … L42) is the level pro-
grammed in channel 2’s level register.
(D6 … D0) and (Q62 … Q02) are the new
and old values of DA-Data2.
The two level registers, LEVEL1 and
LEVEL2, consist of three flip flops each
and they are compared against the
three most significant bits of the DA-
Data value, sign bit excluded.
DA1 and DA2
These are the two outputs of DAC1 and
DAC2. Input to the DACs are internal
data bus (Q61 … Q01) and (Q62 … Q02).
Reference Voltage VRef
VRef is the analog input for the two
DACs. Special care in layout, gives a
very low voltage drop from pin to
resistor. Any VRef between 0.0 V and VDD
can be applied, but output might be non-
linear above 3.0 V.
Power-on Reset
This function automatically resets all
internal flip flops at power-on. This
results in VSS voltage at both DAC
outputs and all digital outputs.
Figure 10. Table showing how data is transfered inside PBM 3960/1.
Figure 9. Motor current dragging at high
step rates and current decay influence.
Fast current decay will make it possible
for the current to follow the ideal sine
curve. Output shown without sign shift.
Figure 8b. An example of accessible
positions with a given torque deviation/
fullstep. Note that 1:st
µ
step sets highest
resolution. Data points are exaggerated
for illustration purpose.
TNom = code 127.
Where (D6 … D0) is the new value being
sent to DA-Data1 and (Q61 … Q01) is DA-
Data1’s old value. (L61 … L41) are the
three bits for setting the current decay
level at LEVEL1.
The logic definition of CD2 is analog to
CD1:
CD2 = NOT{[(D6 … D0) < (Q62 … Q02)]
AND[(D6 …D4) < (L62 … L42)]}
Reset
If Reset is not used, leave it disconnec-
ted. Reset can be used to measure
leakage currents from VDD.
Applications Information
How Many Microsteps?
The number of true microsteps that can
be obtained depends upon many
different variables, such as the number
of data bits in the Digital-to-Analog
converter, errors in the converter,
acceptable torque ripple, single- or
double-pulse programming, the motor’s
electrical, mechanical and magnetic
characteristics, etc. Many limits can be
found in the motor’s ability to perform
properly; overcome friction, repeatability,
torque linearity, etc. It is important to
realize that the number of current levels,
128 (27), is
not
the number of steps
available. 128 is the number of current
levels (reference voltage levels)
available from each driver stage.
Combining a current level in one winding
with any of 128 other current levels in
the other winding will make up 128
current levels. So expanding this, it is
possible to get 16,384 (128 • 128)
combinations of different current levels in
the two windings. Remember that these
16,384 micro-positions are not all useful,
the torque will vary from 100% to 0%
and some of the options will make up the
same position. For instance, if the
current level in one winding is OFF (0%)
you can still vary the current in the other
winding in 128 levels. All of these
combinations will give you the same
position
but
a varying torque.
Typical Application
The microstepper solution can be used
in a system with or without a micro-
processor.
Without a microprocessor, a counter
addresses a ROM where appropriate
step data is stored. Step and Direction
are the input signals which represent
clock and up / down of counter. This is
the ideal solution for a system where
there is no microprocessor or it is heavily
loaded with other tasks.
With a microprocessor, data is stored
in ROM / RAM area or each step is
successively calculated. PBM 3960/1 is
connected like any peripheral addressa-
ble device. All parts of stepping can be
tailored for specific damping needs etc.
T [mNm]
1
T [mNm]
2
max
T
nom
T
min
T
DA output [V]
t
Current dragging
Time
CD
CS A0 A1 Data Transfer
0 0 0 D7 —> Sign1, (D6—D0) —> (Q61—Q01), New value —> CD1
0 0 1 (D6—D4) —> (L61—L41)
0 1 0 D7 —> Sign2, (D6—D0) —> (Q62—Q02), New value —> CD2
0 1 1 (D6—D4) —> (L62—L42)
1 X X No Transfer
I [mA]
1
I [mA]
2
I
Figure 8a. Assuming that torque is
proportional to the current in resp.
winding it is possible to draw figure 8b.
PBM 3960/1
7
Figure 11. Double pulse programming, in- and output signals.
Figure 12. Single pulse programming, in- and output signals.
Time
Time when motor is in
an intermediate
position.
Time when micro
position is almost
correct.
Write
signal.
Motor position. Note
that position is always
a compromise.
Writing to
channel 1.
Writing to
channel 2.
Useful time = compromise position
with equally spaced angles Actual data = true position
Note increased resolution
Single pulse write signal
"Ideal data" = desired
position
Useful time = almost
correct position
Time
Time when motor is in
a compromise
position.
Time when micro
position is correct.
Write
signal.
Motor
position.
Writing to
channel 1.
Writing to
channel 2.
Write time = incorrect position
Actual data = true position
Normal resolution
Double pulse write signal Ideal data = desired position
Useful time = correct
position
PBM 3960/1
8
Figure 14. Typical application in a microprocessor based system.
D0
D7
A0
A1
WR
CS
RESET
VV
PBM 3960/1
21
2
19
4
20
3
18
5
1
15
6
22
16
17
7
14
To
mP
+2.5V
Sign
CD
DA
1
1
1
Sign
CD
DA
2
2
2
SS
VDD
Ref
7
8
9
16
15
14
Phase
CD
V
Phase
CD
V
1
1
2
2
R1
R2
ECECGND
RC
PBL 3771/1
15 kW
3 300 pF
1.0 W 1.0 W
M
M
M
M
A1
B1
A2
B2
V
CC
VV
MM1 MM2
+5 V
4
1
19
22
11 3 20
12 5, 6,
17, 18 213 21
10
11
22
R
S
STEPPER
MOTOR
V
MM
Pin numbers refer
to DIL package.
GND (V
)
1 kW 1 kW
820 pF 820 pF
RS
0.1 mF 0.1 mF
+
10 mF
V (+5 V)
CC
GND
(V )
CC MM
Figure 13. Typical blockdiagram of an application without a microprocessor. Available as testboard, TB 307i/2.
Counter PROM
PBM 3960/1 PBL 3771/1
Voltage
Reference
Control Logic
Step
Direction
Clock Up/Dn
CE
A0
WR
CS
A1 Vref
D0-D7
PBM 3960/1
9
increase on the positive edge of the sine-
cosine curves. Fast current decay is
used at higher speeds to avoid current
dragging with lost positions and incorrect
step angles as a result.
Ramping
Every drive system has inertia which
must be considered in the drive system.
The rotor and load inertia play a big role
at higher speeds. Unlike the DC motor,
the stepper motor is a synchronous
motor and does not change its speed
due to load variations. Examining a
typical stepper motor’s torque-versus-
speed curve indicates a sharp torque
drop-off for the “start-stop without error”
curve. The reason for this is that the
torque requirements increase by the
cube of the speed change. For good
motor performance, controlled accelera-
tion and deceleration should be conside-
red even though microstepping will
improve overall performance.
Programming PBM 3960/1
There are basically two different ways of
programming the PBM 3960/1. They are
called “single-pulse programming” and
“double-pulse programming.” Writing to
the device can only be accomplished by
addressing one register at a time. When
taking one step, at least two registers are
normally updated. Accordingly there
must be a certain time delay between
writing to the first and the second
register. This programming necessity
gives some special stepping advantages.
Double-pulse Programming
The normal way is to send two write
pulses to the device, with the correct
addressing in between, keeping the
delay between the pulses as short as
possible. Write signals will look as
illustrated in figure12. The advantages
are:
• low torque ripple
• correct step angles between each set
of double pulses
• short compromise position between
the two step pulses
• normal microstep resolution
Single-pulse Programming
A different approach is to send one
pulse at a time with an equally-spaced
duty cycle. This can easily be accom-
plished and any two adjacent data will
make up a microstep position. Write
signals will look as in figure 13. The
advantages are:
• higher microstep resolution
• smoother motion
The disadvantages are:
• higher torque ripple
• compromise positions with almost-
correct step angles
This is the ideal solution for a system
where there is an available micropro-
cessor with extra capacity and low cost
is more essential than simplicity. See
typical application, figure 14.
User Hints
Never disconnect ICs or PC Boards
when power is supplied.
Choose a motor that is rated for the
current you need to establish desired
torque. A high supply voltage will gain
better stepping performance even if the
motor is not rated for the VMM voltage,
the current regulation in PBL 3771/1
will take care of it. A normal stepper
motor might give satisfactory result, but
while microstepping, a “microstepping-
adapted” motor is recommended. This
type of motor has smoother motion due
to two major differences, the stator /
rotor teeth relationship is non-equal
and the static torque is lower.
The PBM 3960/1 can handle
programs which generate microsteps at
a desired resolution as well as quarter
stepping, half stepping, full stepping,
and wave drive.
Fast or Slow Current Decay?
There is a difference between static
and dynamic operation of which the
actual application must decide upon
when to use fast or slow current decay.
Generally slow decay is used when
stepping at slow speeds. This will give
the benefits of low current ripple in the
drive stage, a precise and high overall
average current, and normal current
PBM 3960/1
10
Ericsson Components AB
SE-164 81 Kista-Stockholm, Sweden
Telephone: +46 8 757 50 00
Specifications subject to change without
notice.
1522-PBM 3960/1 Uen Rev. B
© Ericsson Components AB 1999
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third
parties which may result from its use. No license is
granted by implication or otherwise under any patent
or patent rights of Ericsson Components. These
products are sold only according to Ericsson
Components' general conditions of sale, unless
otherwise confirmed in writing.
Ordering Information
Package Part No.
DIP Tube PBM 3960/1NS
PLCC Tube PBM 3960/1QNS
PLCC Tape & Reel PBM 3960/1QNT
