ADVANCE INFORMATION
128K x 24 Static RAM
CY7C1024AV33
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Ma y 1, 2000
33
Features
• High speed
—tAA = 9 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• A utomatic power-d ow n w hen deselected
• Easy memory e xpansion with CE1, CE2, CE3 and OE
options
Functional Description
The CY7C1 024A V33 is a high-per formance CMOS static RAM
organized as 131,072 words by 24 bits. Easy mem ory expan-
sion is provided by an active LOW CE1, CE3, active HIGH
CE2, an act ive LO W Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significant ly reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE1, CE2, CE3) active and Wr ite Enable (W E) inputs LOW.
Data on t he 24 I/O pi ns (I/O 0 thr ough I/O23) is t hen written into
the location specif ied on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enabl e (CE1, CE2, CE3) activ e a nd Output En ab le (OE) L O W
while forcing Write Enable (WE) HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the I /O pins.
The 24 input/output pins (I/O0 through I/O23) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabl ed (OE HIGH) , or during a write
operation (CE1, CE 3 LOW, CE2 HIGH, and W E LOW).
The CY7C1024AV33 is available in a standar d 119-ball BGA
package and a 100-pin TQFP package.
Functional Block Diagram
CE#
ADDRESS BUFFER
ROW DECODER
COLUMN DECODER
MEMORY ARRAY
128K X 24
I/O BUFFER
DQ0
CONTROL
A16
A0
DQ23
V
CC
V
SS
CE1#
CE2
BE0#
BE1#
BE2#
WE#
OE#
Selection Guide
7C1024AV33-9 7C1024AV33-10 7C1024AV33-12 7C1024AV33-15
Maximum Access Time (ns) 9 10 12 15
Maximum Oper ating Current (mA) 300 275 250 225
Maxim um Standby Curr ent (mA) 15 15 15 15
CY7C1024AV33
ADVANCE INFORMATION
2
Pin Configurations
119 BGA
Top View
1234567
ANCAAAAANC
BNC A A CE1 AANC
CDQ NC CE2 NC CE3 NC DQ
DDQ VDD VSS VSS VSS VDD DQ
EDQ VSS VDD VSS VDD VSS DQ
FDQ VDD VSS VSS VSS VDD DQ
GDQ VSS VDD VSS VDD VSS DQ
HDQ VDD VSS VSS VSS VDD DQ
JNCa VSS VDD VSS VDD VSS NC
KDQ VDD VSS VSS VSS VDD DQ
LDQ VSS VDD VSS VDD VSS DQ
MDQ VDD VSS VSS VSS VDD DQ
NDQ VSS VDD VSS VDD VSS DQ
PDQ VDD VSS VSS VSS VDD DQ
RDQ NC NC NC NC NC DQ
TNC A A WE AANC
UNC A A OE AANC
CY7C1024AV33
ADVANCE INFORMATION
3
Maximum Ratings
(Above which the useful l ife may be impaired. For user gui de-
li nes, not tes ted.)
Storage Temperature ... .. ......... ...... .............–65°C to +15 0°C
Ambient Temperature wi th
Power Applied.............................................–55°C to +12 5°C
Supply Voltage on VCC to Relative GND[1] ....–0.5V to +7.0V
DC Voltage Appli ed to Output s
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Volt age[1].................................–0.5V to VCC + 0.5V
Cu r re n t in to Outp ut s (L OW ) ........ .... ..... ........ .... ........ .... 2 0 mA
Static Discharge Voltage ..... ...... .. ......... ...... .. ......... ....>2001 V
(per MIL- STD-883, Method 3015 )
Latch-Up Current.....................................................>200 mA
Notes:
1. VIL (min .) = –2.0V for puls e durat ions of less than 20 ns.
2. TA is the “In st ant On” case temper at ure.
100-pin TQFP
Top View
Pin Configurations (continued)
100 99 98 97 96 95 94 93 92 91 90 89 88
1
2
3
4
5
6
7
8
9
10
31 32 33 34 35 36 37 38 39 40 41 42 43
87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44 45 46 47 48 49 50
NC
NC
A11
A3
NC
NC
CE#
A4
NC
NC
VSS
CE1#
A16
A5
VCC
NC
VCC
VSS
VSS
VCC
DQ4
DQ5
DQ6
DQ7
VCC
VSS
DQ8
DQ9
VCC
NC
NC
VSS
NC
NC
NC
A10
A9
A8
VSS
VCC
A0
BE1#
BE0#
A2
A1
NC
A7
OE#
WE#
A6
BE2#
NC
A12
A13
A14
A15
CE2
DQ0
DQ1
VSS
VCC
DQ2
DQ3
VCC
VSS
VCC
VSS
NC
DQ10
DQ11
NC
VCC
VSS
VSS
VCC
DQ20
DQ21
DQ22
DQ23
VCC
VSS
DQ12
DQ13
VSS
VCC
NC
NC
DQ16
DQ17
VSS
VCC
DQ18
DQ19
VCC
VSS
VCC
VSS
NC
DQ14
DQ15
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 3.3V ±10%
Industrial –40°C to +85 °C 3.3V ±10%
CY7C1024AV33
ADVANCE INFORMATION
4
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions[3] 1024AV33-9 1024AV33-10 1024AV33-12 1024AV33-15
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Vo ltage VCC = Min.,
IOH = –4.0 mA 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA 0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+ 0. 3 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –3+3–3+3–3+3–3+3µA
IOZ Output Leakage
Current GND < VI < VCC,
Output Di sabled –5+5–5+5–5+5–5+5µA
ICC VCC Operati n g
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
300 275 250 225 mA
ISB1 Au to m a ti c C E
Po wer-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
60 60 60 60 mA
ISB2 Au to m a ti c C E
Po wer-Down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
15 15 15 15 mA
Capacitance[4]
P arameter De scri ption Test Conditions Max. Unit
CIN Input Capac it ance TA = 25°C, f = 1 MHz,
VCC = 3.3V 10 pF
COUT Outpu t Capacitance 8 pF
Notes:
3. CE is a combination of CE1, CE2 and CE3
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads a nd Waveforms
1024V33–31024V33–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤ 3 n s ≤3ns
OUTPUT
R1 480ΩR1 480 Ω
R2
255ΩR2
255Ω
167 Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
CY7C1024AV33
ADVANCE INFORMATION
5
Switchi n g C h ar acteris t i cs[5] Over the Operating Range
7C1024AV33-9 7C1024AV33-10 7C1024AV33-12 7C1024AV33-15
Parameter Description[3] Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 9 10 12 15 ns
tAA Address to Data Valid 9 10 12 15 ns
tOHA Data Hold from Address Change 3 3 3 3 ns
tACE CE active to Data Valid 9 10 12 15 ns
tDOE OE LOW to D a ta Valid 4 5 6 7 ns
tLZOE OE LOW to Low Z 0 0 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 4566ns
tLZCE CE active to Low Z[7] 3333ns
tHZCE CE inactive to High Z[6, 7] 5566ns
tPU CE active to Power-Up 0 0 0 0 ns
tPD CE inactive to Power-Down 9 10 12 15 ns
WRITE CYCLE[8, 9]
tWC Write Cycle Time 9 10 12 15 ns
tSCE CE active to Write End 8 8 9 9 ns
tAW Address Set-Up to Write End 7 7 8 8 ns
tHA Address Hold from Write End 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 ns
tPWE WE Pulse Width 7 7 8 8 ns
tSD Data Se t-U p to W r ite En d 5 5 6 6 ns
tHD Data Hold from Write End 0 0 0 0 ns
tLZWE WE HIGH to Low Z[7] 3333ns
tHZWE WE LOW to High Z[6, 7] 5566ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30- pF lo ad capaci tance .
6. tHZOE, tHZCE, and tHZWE are specified with a l oad capaci tance of 5 p F as in part (b) of A C Test Loads. Transition is measured ±500 mV from s teady- state vol tage .
7. At any given temperature and voltage condition, tHZCE is l ess than t LZCE, tHZOE is less than tLZOE, and tHZWE is les s tha n tLZWE f or an y given d e vice .
8. The internal write time of the memory is defined by the overlap of CE LO W and WE LOW . CE and WE mus t be LO W t o ini tiate a write , and the tr ansi tion of any o f these
signals can t erminate t he write. The input dat a s et-up and hold ti ming shoul d be ref erenc ed t o the leading edg e of t he si gnal tha t terminat es the w rite.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C1024AV33
ADVANCE INFORMATION
6
Switching Wavefor ms
Read Cycle No. 1[10, 11]
Read Cycle No. 2 (OE Controll ed)[3, 1 1, 1 2 ]
Write Cycle No. 1 (CE Contr oll ed)[3 , 13, 1 4 ]
Notes:
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE tr ansitio n LO W.
13. Data I/O is high impedance if OE = VIH.
14. If CE goes HIGH simu ltaneousl y with WE g oing HI GH, the output remain s in a hi gh-impedanc e state.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
1024V33–6
ADDRESS
DATA OUT
1024V33–7
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
ADDRESS
WE
DATA I/O
1024V33–8
CY7C1024AV33
ADVANCE INFORMATION
7
Write Cycle No. 2 (WE Controlled, OE HIGH During Writ e)[13, 14]
Write Cycle No. 3 (WE Controlled, OE LOW)[3, 14 ]
Note:
15. During this period the I/Os are in the output state and input signals should not be applied.
Switching Wavefor ms (cont inued)
1024V33–9
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 15
1024V33–10
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 15
CY7C1024AV33
ADVANCE INFORMATION
8
Document #: 38-00983-**
Truth Ta ble
CE1 CE2 CE3 OE WE I/O0–I/O23 Mode Power
H X X X X High Z Power-Down Standby (I SB)
X L X X X High Z Power-Down Standby (ISB)
X X H X X High Z Power-Down Sta ndby (ISB)
L H L L H Data Out Read Active (ICC)
L H L X L Da ta In Write Active (ICC)
L H L H H High Z Selected, Outputs Disabl ed Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Name P ackage Type Operating
Range
9 CY7 C1024AV33-9AC A101 100-Pin Thin Plastic Quad Flatpack (1 4 x 20 x 1.4 mm) Commercial
CY7C 1024AV33-9BGC BG 119 119-Ball BGA
10 CY7C 1024AV33-10AC A1 01 100-Pin Thin Plast ic Quad Flatpac k (14 x 20 x 1.4 mm)
CY7C 1024AV33-10BGC BG119 119- Ball BGA
12 CY7C 1024AV33-12AC A1 01 100-Pin Thin Plast ic Quad Flatpac k (14 x 20 x 1.4 mm)
CY7C 1024AV33-12BGC BG119 119- Ball BGA
15 CY7C 1024AV33-15AC A1 01 100-Pin Thin Plast ic Quad Flatpac k (14 x 20 x 1.4 mm)
CY7C 1024AV33-15BGC BG119 119- Ball BGA
CY7C 1024AV33-15BGI BG119 119- Ball BGA Industrial
CY7C1024AV33
ADVANCE INFORMATION
9
Package D i ag ra ms
100-Pin Thin Plas ti c Qua d Flat pack (14 x 20 x 1.4 mm) A101
51-85050-A
CY7C1024AV33
ADVANCE INFORMATION
© Cypress Semiconductor Corporation, 2000. The i nformation contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it conv ey or im ply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The incl usion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag ra ms (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
