DATA SH EET
Preliminary specification
File under Integrated Circuits, IC02 1995 Mar 20
INTEGRATED CIRCUITS
Philips Semiconductors
TDA8761
9-bit analog-to-digital converter for
digital video
1995 Mar 20 2
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
FEATURES
•9-bit resolution
•Sampling rate up to 30 MHz
•DC sampling allowed
•One clock cycle conversion only
•High signal-to-noise ratio over a large analog input
frequency range (8.5 effective bits at 10 MHz full-scale
input at fclk = 30 MHz)
•No missing codes guaranteed
•In range (IR) 3-state TTL output
•TTL compatible digital inputs and outputs
•Low-level AC clock input signal allowed
•External reference voltage regulator
•Power dissipation only 360 mW (typical)
•Low analog input capacitance, no buffer amplifier
required
•No sample-and-hold circuit required.
APPLICATIONS
Analog-to-digital conversion for:
•Video data digitizing
•Digital Video Broadcasting (DVB)
•Cable TV.
GENERAL DESCRIPTION
The TDA8761 is a 9-bit analog-to-digital converter (ADC)
for professional video and digital video set box
applications. It converts the analog input signal into 9-bit
binary-coded digital words at a maximum sampling rate of
30 MHz. Its linearity performance ensures the required
conversion accuracy in case of 256QAM demodulator
concept and for all symbol frequencies. All digital inputs
and outputs are TTL compatible, although a low-level sine
wave clock input signal is allowed.
QUICK REFERENCE DATA
Note
1. fi= 11 MHz and fclk = 30 MHz; fi= 8 MHz and fclk = 20 MHz.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output stages supply voltage 4.4 5.0 5.25 V
ICCA analog supply current −30 tbf mA
ICCD digital supply current −22 tbf mA
ICCO output stages supply current −22 tbf mA
AINL AC integral non-linearity note 1; full scale input sine wave −±0.75 tbf LSB
note 1; 50% full scale input sine wave −±0.5 tbf LSB
ADNL AC differential non-linearity note 1; full scale input sine wave −±0.5 tbf LSB
note 1; 50% full scale input sine wave −±0.3 tbf LSB
fclk(max) maximum clock frequency 30 −−MHz
Ptot total power dissipation −360 tbf mW
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA8761M SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
1995 Mar 20 3
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
12
DGND
5
6
8
7
9
AGND2
VRB
VRM
VRT
VI
11
VCCD
3
26
VCCA
21
22
23
24
20 D3
D4
D5
D6
D7
19
18
25
2
D2
D1
17 D0
D8
IN RANGE LATCH
TTL OUTPUTSLATCHES
ANALOG -TO - DIGITAL
CONVERTER
CLOCK DRIVER
MGC355
TTL OUTPUT
1
CLK
10
CE
TC
TDA8761
13 VCCO1
4
AGND1
analog grounds digital ground
27
OGND2
14
OGND1
output grounds
analog
voltage input data outputs
LSB
MSB
28 VCCO2
IR
output
1995 Mar 20 4
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
PINNING
SYMBOL PIN DESCRIPTION
CLK 1 clock input
TC 2 two’s complement input (active LOW)
VCCA 3 analog supply voltage (+5 V)
AGND1 4 analog ground 1
AGND2 5 analog ground 2
VRB 6 reference voltage BOTTOM input
VRM 7 reference voltage MIDDLE
VI8 analog input voltage
VRT 9 reference voltage TOP input
CE 10 chip enable input (TTL level input,
active LOW)
VCCD 11 digital supply voltage (+5 V)
DGND 12 digital ground
VCCO1 13 supply voltage for output stages 1
(+5 V)
OGND1 14 output ground 1
n.c. 15 not connected
n.c. 16 not connected
D0 17 data output; bit 0 (LSB)
D1 18 data output; bit 1
D2 19 data output; bit 2
D3 20 data output; bit 3
D4 21 data output; bit 4
D5 22 data output; bit 5
D6 23 data output; bit 6
D7 24 data output; bit 7
D8 25 data output; bit 8 (MSB)
IR 26 in range data output
OGND2 27 output ground 2
VCCO2 28 supply voltage for output stages 2
(+5 V) Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
CLK
TC
CCA
AGND1
AGND2
RB
RM
I
RT
CE
CCD
DGND
CCO1
OGND1
CCO2
OGND2
IR
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
n.c.
V
V
V
V
V
V
V
V
TDA8761
MGC356
1995 Mar 20 5
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided the difference
between VCCA, VCCD and VCCO is between −1 and +1 V.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCCA analog supply voltage note 1 −0.3 +7.0 V
VCCD digital supply voltage note 1 −0.3 +7.0 V
VCCO output stages supply voltage note 1 −0.3 +7.0 V
∆VCC supply voltage differences between
VCCA and VCCD −1.0 +1.0 V
VCCO and VCCD −1.0 +1.0 V
VCCA and VCCO −1.0 +1.0 V
VIinput voltage referenced to AGND −0.3 +7.0 V
Vi(p-p) AC input voltage for switching
(peak-to-peak value) referenced to DGND −VCCD V
IOoutput current −10 mA
Tstg storage temperature −55 +150 °C
Tamb operating ambient temperature 0 +70 °C
Tjjunction temperature −+150 °C
SYMBOL PARAMETER VALUE UNIT
Rth j-a thermal resistance from junction to ambient in free air 110 K/W
1995 Mar 20 6
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
CHARACTERISTICS
VCCA =V
3to V4and V5= 4.75 to 5.25 V; VCCD =V
11 to V12 = 4.75 to 5.25 V; VCCO =V
13 and V28 to V14 and
V27 = 4.4 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at
VCCA =V
CCD =V
CCO =5V; V
i(p-p) = 1.5 V; CL= 15 pF and Tamb =25°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output stages supply voltage 4.4 5.0 5.25 V
∆VCC supply voltage differences between
VCCA and VCCD −0.25 −+0.25 V
VCCA and VCCO −0.4 −+0.4 V
VCCD and VCCO −0.4 −+0.4 V
ICCA analog supply current −30 tbf mA
ICCD digital supply current −22 tbf mA
ICCO output stages supply current −22 tbf mA
Inputs
CLOCK INPUT CLK (REFERENCED TO DGND); note 1
VIL LOW level input voltage 0 −0.8 V
VIH HIGH level input voltage 2.0 −VCCD V
IIL LOW level input current Vclk = 0.4 V −10 +1 µA
I
IH HIGH level input current Vclk = 2.7 V −−20 µA
ZIinput impedance fclk =30MHz −2−kΩ
C
Iinput capacitance fclk =30MHz −2−pF
INPUT CE (REFERENCED TO DGND); see Table 2
VIL LOW level input voltage 0 −0.8 V
VIH HIGH level input voltage 2.0 −VCCD V
IIL LOW level input current VIL = 0.4 V −400 −− µA
I
IH HIGH level input current VIH = 2.7 V −−20 µA
VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
IIL LOW level input current VI= 1.3 V −0−µA
I
IH HIGH level input current VI= 3.8 V −70 −µA
Z
Iinput impedance fi=10MHz −5−kΩ
C
Iinput capacitance fi=10MHz −8−pF
1995 Mar 20 7
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
Reference voltages for the resistor ladder; see Table 1
VRB reference voltage BOTTOM 1.2 1.3 −V
VRT reference voltage TOP −3.3 VCCA −0.8 V V
Vdiff differential reference voltage
VRT −VRB
1.8 2.0 3.0 V
Iref reference current −30 −mA
RLAD resistor ladder −85 −Ω
TCRLAD temperature coefficient of the resistor
ladder −1.86 −ppm
−158 −mΩ/K
VosB offset voltage BOTTOM note 2 −250 −mV
VosT offset voltage TOP note 2 −250 −mV
Vi(p-p) analog input voltage
(peak-to-peak value) note 3 1.3 1.5 2.5 V
Outputs
DIGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND)
VOL LOW level output voltage IO= 1 mA 0 −0.4 V
VOH HIGH level output voltage IO= 0 mA 2.7 −VCCO −0.5 V
IO=−0.4 mA 2.7 −VCCO −1.3 V
IO=−1 mA 2.4 −VCCO −1.4 V
IOZ output current in 3-state mode 0.4 V < VO<V
CCO −20 −+20 µA
Switching characteristics
CLOCK INPUT CLK; see Fig.3; note 1
fclk(max) maximum clock frequency 30 −− MHz
tCPH clock pulse width HIGH 10 −− ns
tCPL clock pulse width LOW 10 −− ns
Analog signal processing
LINEARITY
AINL AC integral non-linearity note 5; full scale input
sine wave −±0.75 tbf LSB
note 5; 50% full scale
input sine wave −±0.5 tbf LSB
ADNL AC differential non-linearity note 5; full scale input
sine wave −±0.5 tbf LSB
note 5; 50% full scale
input sine wave −±0.3 tbf LSB
OFER offset error middle code;
VRB = 1.3 V; VRT = 3.3 V −±1−LSB
GER gain error (from device to device) VRB = 1.3 V;
VRT = 3.3 V; note 4 −±0.1 −%
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1995 Mar 20 8
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
BANDWIDTH (fclk = 30 MHz)
B analog bandwidth full-scale sine wave;
note 6 −40 −MHz
75% full-scale sine
wave; note 6 −55 −MHz
small signal at
mid-scale;
VI=±10 LSB at
code 256; note 6
−700 −MHz
tSTLH analog input settling time
LOW-to-HIGH full-scale square wave;
Fig.5; note 7 −2.0 tbf ns
tSTHL analog input settling time
HIGH-to-LOW full-scale square wave;
Fig.5; note 7 −2.5 tbf ns
HARMONICS (fclk =30MHZ)
THD total harmonic distortion fi=10MHz −−64 −dB
SIGNAL-TO-NOISE RATIO; see Fig.7; note 8
S/N signal-to-noise ratio (full scale) without harmonics;
fclk = 30 MHz;
fi=10MHz
53 55 −dB
EFFECTIVE BITS; see Fig 6; note 8
EB effective bits fclk = 30 MHz;
fi=10MHz −8.5 −bits
TWO-TONE; note 9
TTIR two-tone intermodulation rejection fclk =30MHz −−64 −dB
BIT ERROR RATE
BER bit error rate fclk = 30 MHz;
fi= 10 MHz;
VI=±16 LSB at
code 256
−10−13 −times/
sample
DIFFERENTIAL GAIN; note 10
Gdiff differential gain fclk = 30 MHz;
PAL modulated ramp −tbf −%
DIFFERENTIAL PHASE; note 10
ϕdiff differential phase fclk = 30 MHz;
PAL modulated ramp −tbf −deg
Timing (fclk = 30 MHz; CL= 15 pF); see Fig.3; note 11
tds sampling delay time −−2ns
t
houtput hold time 5 −− ns
tdoutput delay time −10 14 ns
CLdigital output load −15 40 pF
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1995 Mar 20 9
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 511:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb =25°C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at Tamb =25°C.
3. Analog input voltage range can be derived from VRT −VRB difference. It is
4.
5. fi= 11 MHz and fclk = 30 MHz; fi= 8 MHz and fclk = 20 MHz.
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No
glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB ×6.02 + 1.76 dB.
9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.10 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
11. Output data acquisition: the output data is available after the maximum delay time of td.
3-state output delay times; see Fig.4
tdZH enable HIGH −tbf tbf ns
tdZL enable LOW −tbf tbf ns
tdHZ disable HIGH −tbf tbf ns
tdLZ disable LOW −tbf tbf ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VRT VRB
–()8×
9
-------------------------------------------
GER V511 V0
–()1.5 V–
1.5 V
--------------------------------------------------- 100×=
1995 Mar 20 10
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.3 V)
Table 2 Mode selection
STEP VI(p-p) IR BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
U/F <1.55 0 0 00000000000000000
0 1.55 1 0 00000000000000000
1 . 1000000001000000001
. . ...................
. . ...................
510 . 1111111111111111110
511 3.05 1 1 11111111111111111
O/F >3.05 0 1 11111111111111111
TC CE D8 TO D0 IR
X 1 high impedance high impedance
0 0 active; two’s complement active
1 0 active; binary active
Fig.3 Timing diagram.
handbook, full pagewidth
ds
t
sample N + 1
sample N
CLK
MGC357
sample N + 2
1.4 V
V
l
DATA
D0 to D8
td
th
CPH
tCPL
t
2.4 V
0.4 V
1.4 V
DATA
N + 1
DATA
N
DATA
N - 1
DATA
N - 2
1995 Mar 20 11
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
Fig.4 Timing diagram and test conditions of 3-state output delay time.
fCE = 100 kHz.
handbook, full pagewidth
MGC358
50 %
50 %
HIGH
LOW
dZH
t
dHZ
t
50 %
HIGH
LOW
dZL
t
dLZ
t
10 %
90 %
output
data
VCCD
output
data
3.3 kΩ
15 pF
S1
VCCD
TDA8761
CE
CE
TEST
dLZ
t
dZL
t
dHZ
t
dZH
S1
CCD
V
CCD
V
GND
GND
t
1995 Mar 20 12
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
Fig.5 Analog input settling-time diagram.
handbook, full pagewidth
MGC359
50 %
STLH
t
2 ns
code 0
code 511
I
50 %
0.5 ns
50 %
2 ns
STHL
t
50 %
0.5 ns
CLK
V
Fig.6 Fast Fourier Transform (fclk = 30 MHz; fi= 10 MHz).
Effective bits: 8.58; THD = −61.80 dB.
Harmonic levels (dB): 2nd = −64.77; 3rd = −79.30; 4th = −71.90; 5th = −66.12; 6th = −82.29.
handbook, full pagewidth
0
120 0 1.88 3.75
MGC360
40
80
9.375.63 7.50 11.3 13.1 15.0
f (MHz)
100
20
60
amplitude
(dB)
1995 Mar 20 13
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
INTERNAL PIN CONFIGURATIONS
Fig.7 TTL data and in-range outputs.
handbook, halfpage
MGC361
OGND1
D8 to D0
O/UF
VCCO1
VCCO2
Fig.8 Analog inputs.
handbook, halfpage
MGC040
AGND
VCCA
VI
Fig.9 CE (TC) 3-state input.
n
dbook, halfpage
MGC041
OGND2
VCCO1
(TC)
CE
Fig.10 VRB, VRM and VRT.
handbook, halfpage
R
MEA050
AGND
VRB
VRM
VCCA
VRT
LAD
1995 Mar 20 14
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
Fig.11 CLK input.
handbook, full pagewidth
V
VCCD
CLK
DGND
MGC042
ref(1.3 V)
1995 Mar 20 15
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
APPLICATION INFORMATION
Fig.12 Application diagram.
The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the
reference ladder voltages can be derived from a well regulated VCCA supply through a resistor bridge and a decoupled capacitor.
For applications where the input signal must remain well centred around middle scale, VRM must be decoupled and connected to analog input signal
(pin 8) through a resistor. The values must be defined in accordance with the input signal frequency in order to avoid direct coupling into the ADC ladder
(e.g. R = 5 kΩ and C = 100 nF).
(1) VRB, VRM and VRT are decoupled to AGND.
(2) Pins 15 and 16 should be connected to DGND in order to prevent noise influence.
handbook, halfpage
28
27
26
25
24
23
22
21
20
19
18
17
TDA8761
OGND2
VCCO1
D2
D3
D4
D5
D6
D7
D8
D1
D0
VCCD
VCCA
1
2
3
4
5
6
7
8
9
10
11
12
CLK
AGND1
AGND2
n.c.
VRB
VRM
VRT
MGC362
16
15
13
14
100 nF
100 nF
DGND
OGND1
IR
CE
TC
VCCO2
AGND
AGND
100 nF
AGND
VI
(1)
(1)
(1)
(2)
n.c.
(2)
1995 Mar 20 16
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
PACKAGE OUTLINE
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 10.4
10.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 1.1
0.7 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
1.03
0.63
SOT341-1 MO-150AH 93-09-08
95-02-04
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
114
28 15
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
A
max.
2.0
1995 Mar 20 17
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
SOLDERING
Plastic small outline packages
BYWAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1995 Mar 20 18
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
NOTES
1995 Mar 20 19
Philips Semiconductors Preliminary specification
9-bit analog-to-digital converter for
digital video TDA8761
NOTES
Philips Semiconductors – a worldwide company
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77621 BOGOTA, Tel. (571)249 7624/(571)217 4609,
Fax. (571)217 4549
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. (032)88 2636, Fax. (031)57 1949
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. (9)0-50261, Fax. (9)0-520971
France: 4 Rue du Port-aux-Vins, BP317,
92156 SURESNES Cedex,
Tel. (01)4099 6161, Fax. (01)4099 6427
Germany: P.O. Box 10 63 23, 20043 HAMBURG,
Tel. (040)3296-0, Fax. (040)3296 213.
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. (01)4894 339/4894 911, Fax. (01)4814 240
Hong Kong: PHILIPS HONG KONG Ltd., 15/F Philips Ind. Bldg.,
24-28 Kung Yip St., KWAI CHUNG, N.T.,
Tel. (852)424 5121, Fax. (852)480 6960/480 6009
India: Philips INDIA Ltd, Shivsagar Estate, A Block ,
Dr. Annie Besant Rd. Worli, Bombay 400 018
Tel. (022)4938 541, Fax. (022)4938 722
Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,
P.O. Box 4252, JAKARTA 12950,
Tel. (021)5201 122, Fax. (021)5205 189
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (01)7640 000, Fax. (01)7640 200
Italy: PHILIPS SEMICONDUCTORS S.r.l.,
Piazza IV Novembre 3, 20124 MILANO,
Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. (03)3740 5028, Fax. (03)3740 0580
Korea: (Republic of) Philips House, 260-199 Itaewon-dong,
Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,
Tel. 9-5(800)234-7381, Fax. (708)296-8556
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB
Tel. (040)783749, Fax. (040)788399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. (09)849-4160, Fax. (09)849-7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022)74 8000, Fax. (022)74 8341
Pakistan: Philips Electrical Industries of Pakistan Ltd.,
Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474
Portugal: PHILIPS PORTUGUESA, S.A.,
Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. (01)4163160/4163333, Fax. (01)4163174/4163366
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. (65)350 2000, Fax. (65)251 6500
South Africa: S.A. PHILIPS Pty Ltd.,
195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430, Johannesburg 2000,
Tel. (011)470-5911, Fax. (011)470-5494.
Spain: Balmes 22, 08007 BARCELONA,
Tel. (03)301 6312, Fax. (03)301 42 43
Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,
Tel. (0)8-632 2000, Fax. (0)8-632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. (01)488 2211, Fax. (01)481 77 30
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West
Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. (662)398-0141, Fax. (662)398-3319
Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. (0212)279 27 70, Fax. (0212)282 67 07
United Kingdom: Philips Semiconductors LTD.,
276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. (0181)730-5000, Fax. (0181)754-8421
United States:811 East Arques Avenue, SUNNYVALE,
CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
SCD39 © Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Philips Semiconductors
Printed in The Netherlands
533061/1500/01/pp20 Date of release: 1995 Mar 20
Document order number: 9397 750 00112
