FSL923A0D, FSL923A0R Data Sheet 5A, -200V, 0.670 Ohm, Radiation Hardened, SEGR Resistant, P-Channel Power MOSFETs The Discrete Products Operation of Intersil has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. June 1999 File Number 4359.2 Features * 5A, -200V, rDS(ON) = 0.670 * Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) * Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias * Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM * Photo Current - 3.0nA Per-RAD(Si)/s Typically * Neutron - Maintain Pre-RAD Specifications for 1E13 Neutrons/cm2 - Usable to 1E14 Neutrons/cm2 Symbol D G Reliability screening is available as either commercial, TXV equivalent of MIL-S-19500, or Space equivalent of MIL-S-19500. Contact Intersil for any desired deviations from the data sheet. Ordering Information RAD LEVEL SCREENING LEVEL S Package PART NUMBER/BRAND 10K Commercial FSL923A0D1 10K TXV FSL923A0D3 100K Commercial FSL923A0R1 100K TXV FSL923A0R3 100K Space FSL923A0R4 TO-205AF D G S Formerly available as type TA17797. (c)2001 Fairchild Semiconductor Corporation FSL923A0D, FSL923A0R Rev. A FSL923A0D, FSL923A0R Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSL923A0D, FSL923A0R -200 -200 UNITS V V TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation 5 3 15 20 A A A V TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100H, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS 25 10 0.20 15 5 15 -55 to 150 W W W/ oC A A A oC 300 oC Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS Drain to Source Breakdown Voltage BVDSS ID = 1mA, VGS = 0V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 1mA Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On-State Voltage Drain to Source On Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time IDSS IGSS VDS(ON) rDS(ON)12 td(ON) tr td(OFF) TYP MAX UNITS V -200 - - TC = -55oC - - -7.0 V TC = 25oC -2.0 - -6.0 V TC = 125oC -1.0 - - V VDS = 160V, VGS = 0V TC = 25oC - - 25 A TC = 125oC - - 250 A VGS = 20V TC = 25oC TC = 125oC - - 100 nA - - 200 nA - - -3.70 V - 0.560 0.670 - - 1.20 - - 30 ns - - 30 ns - - 60 ns - - 35 ns VGS = -12V, ID = 5A ID = 3A, VGS = -12V TC = 25oC TC = 125oC VDD = -100V, ID = 5A, RL = 20, VGS = -12V, RGS = 7.5 tf Qg(TOT) VGS = 0V to -20V Gate Charge at 12V Qg(12) VGS = 0V to -12V Threshold Gate Charge Qg(TH) VGS = 0V to -2V Total Gate Charge MIN VDD = -100V, ID = 5A - - 60 nC - 36 40 nC - - 2.4 nC Gate Charge Source Qgs - 6.0 7.6 nC Gate Charge Drain Qgd - 16 18 nC - -6 - V Plateau Voltage V(PLATEAU) Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS ID = 5A, VDS = -15V VDS = -25V, VGS = 0V, f = 1MHz - 890 - pF - 200 - pF - 55 - pF Thermal Resistance Junction to Case RJC - - 5 oC/W Thermal Resistance Junction to Ambient RJA - - 175 oC/W (c)2001 Fairchild Semiconductor Corporation FSL923A0D, FSL923A0R Rev. A FSL923A0D, FSL923A0R Source to Drain Diode Specifications PARAMETER SYMBOL Forward Voltage TEST CONDITIONS VSD Reverse Recovery Time ISD = 5A MIN TYP MAX -0.6 - -1.8 V - - 190 ns UNITS ISD = 5A, dISD/dt = 100A/s trr Electrical Specifications up to 100K RAD UNITS TC = 25oC, Unless Otherwise Specified MIN MAX Drain to Source Breakdown Volts PARAMETER (Note 3) SYMBOL BVDSS VGS = 0, ID = 1mA TEST CONDITIONS -200 - V Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA -2.0 -6.0 V Gate to Body Leakage (Notes 2, 3) IGSS VGS = 20V, VDS = 0V - 100 nA Zero Gate Leakage (Note 3) IDSS VGS = 0, VDS = -160V - 25 A Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = -12V, ID = 5A - -3.7 V Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = -12V, ID = 3A - 0.670 NOTES: 1. Pulse test, 300s Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = -12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) (Note 4) ENVIRONMENT (NOTE 5) TEST SYMBOL Single Event Effects Safe Operating Area SEESOA ION SPECIES TYPICAL LET (MeV/mg/cm) TYPICAL RANGE () APPLIED VGS BIAS (V) (NOTE 6) MAXIMUM VDS BIAS (V) Ni 26 43 20 -200 Br 37 36 5 -200 Br 37 36 10 -160 Br 37 36 15 -100 Br 37 36 20 -40 NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), T = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). Typical Performance Curves Unless Otherwise Specified LET = 26MeV/mg/cm2, RANGE = 43 1E-3 LET = 37MeV/mg/cm2, RANGE = 36 LIMITING INDUCTANCE (HENRY) FLUENCE = 1E5 IONS/cm2 (TYPICAL) -200 VDS (V) -160 -120 -80 -40 TEMP = 25oC 0 0 5 10 15 20 25 VGS (V) FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA (c)2001 Fairchild Semiconductor Corporation 1E-4 ILM = 10A 30A 1E-5 100A 300A 1E-6 1E-7 -10 -30 -100 -300 -1000 DRAIN SUPPLY (V) FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS FSL923A0D, FSL923A0R Rev. A FSL923A0D, FSL923A0R Typical Performance Curves Unless Otherwise Specified (Continued) 50 7 TC = 25oC ID , DRAIN CURRENT (A) 6 ID , DRAIN (A) 5 4 3 2 10 100s 1ms 1 10ms OPERATION IN THIS AREA MAY BE 1 100ms LIMITED BY rDS(ON) 0 -50 0 50 0.1 -1 150 100 -10 TC , CASE TEMPERATURE (oC) -500 -100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 2.5 PULSE DURATION = 250ms, VGS = -12V, ID = 3A 2.0 QGS NORMALIZED rDS(ON) QG -12V QGD VG 1.5 1.0 0.5 0.0 -80 CHARGE -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE NORMALIZED THERMAL RESPONSE (ZJC) 10 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC SINGLE PULSE 0.001 10-5 10-4 10-3 10-2 10-1 t1 100 t2 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE (c)2001 Fairchild Semiconductor Corporation FSL923A0D, FSL923A0R Rev. A FSL923A0D, FSL923A0R Typical Performance Curves Unless Otherwise Specified (Continued) IAS , AVALANCHE CURRENT (A) 30 STARTING TJ = 25oC 10 STARTING TJ = 150oC IF R = 0 tAV = (L) (IAS) / (1.3 RATED BV DSS - VDD) IF R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BV DSS - VDD) + 1] 1 0.01 0.1 1 10 tAV , TIME IN AVALANCHE (ms) FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK IAS 0V VDS IAS VDD + 50 - tP VDD 50V-150V DUT 50 VGS 20V tAV FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% VDS 0V 10% DUT VGS = -12V 10% 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 12. RESISTIVE SWITCHING WAVEFORMS FSL923A0D, FSL923A0R Rev. A FSL923A0D, FSL923A0R Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS = 20V 20 (Note 7) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID Gate Threshold Voltage VGS(TH) ID = 1.0mA 25 (Note 7) A 20% (Note 8) 20% (Note 8) V NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. Screening Information TEST JANTXV EQUIVALENT JANS EQUIVALENT Gate Stress VGS = -30V, t = 250s VGS = -30V, t = 250s Pind Optional Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 160 hours MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 10% 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A, Subgroups 2 and 3 NOTE: 9. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER Safe Operating Area Unclamped Inductive Switching SYMBOL SOA TEST CONDITIONS VDS = -160V, t = 10ms MAX UNITS 0.71 A IAS VGS(PEAK) = -15V, L = 0.1mH 15 A Thermal Response VSD tH = 10ms; VH = -25V; IH = 1A 60 mV Thermal Impedance VSD tH = 500ms; VH = -25V; IH = 1A 230 mV (c)2001 Fairchild Semiconductor Corporation FSL923A0D, FSL923A0R Rev. A FSL923A0D, FSL923A0R Rad Hard Data Packages - Intersil Power Transistors TXV Equivalent Class S - Equivalents 1. RAD HARD TXV EQUIVALENT - STANDARD DATA PACKAGE 1. RAD HARD "S" EQUIVALENT - STANDARD DATA PACKAGE A. Certificate of Compliance A. Certificate of Compliance B. Assembly Flow Chart B. Serialization Records C. Preconditioning - Attributes Data Sheet C. Assembly Flow Chart D. Group A - Attributes Data Sheet D. SEM Photos and Report E. Group B - Attributes Data Sheet F. Group C - Attributes Data Sheet G. Group D - Attributes Data Sheet E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data 2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA PACKAGE F. Group A - Attributes Data Sheet A. Certificate of Compliance G. Group B - Attributes Data Sheet B. Assembly Flow Chart H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet C. Preconditioning - Attributes Data Sheet - Precondition Lot Traveler - Pre and Post Burn-In Read and Record Data D. Group A - Attributes Data Sheet - Group A Lot Traveler E. Group B - Attributes Data Sheet - Group B Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup B3) - Bond Strength Data (Subgroup B3) - Pre and Post High Temperature Operating Life Read and Record Data (Subgroup B6) F. Group C G. Group D - Attributes Data Sheet - Group C Lot Traveler - Pre and Post Read and Record Data for Intermittent Operating Life (Subgroup C6) - Bond Strength Data (Subgroup C6) - Attributes Data Sheet - Group D Lot Traveler - Pre and Post RAD Read and Record Data 2. RAD HARD MAX. "S" EQUIVALENT - OPTIONAL DATA PACKAGE A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data I. Group D (c)2001 Fairchild Semiconductor Corporation - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data FSL923A0D, FSL923A0R Rev. A FSL923A0D, FSL923A0R TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE INCHES OD OD1 P A SEATING PLANE h L Ob e e1 2 e2 1 90o 3 45o j k MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.160 0.180 4.07 4.57 NOTES - Ob 0.016 0.021 0.41 0.53 2, 3 - OD 0.350 0.370 8.89 9.39 OD1 0.315 0.335 8.01 8.50 - e 0.095 0.105 2.42 2.66 4 e1 0.190 0.210 4.83 5.33 4 e2 0.095 0.105 2.42 2.66 4 h 0.010 0.020 0.26 0.50 - j 0.028 0.034 0.72 0.86 - k 0.029 0.045 0.74 1.14 - L 0.500 0.560 12.70 14.22 3 P 0.075 - 1.91 - 5 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. (c)2001 Fairchild Semiconductor Corporation FSL923A0D, FSL923A0R Rev. A