General Description
The MAX11904 is a 20-bit, 1Msps, single-channel, fully
differential SAR ADC with internal reference buffers. The
MAX11904 provides excellent static and dynamic perfor-
mance with best-in-class power consumption that directly
scales with throughput. The device has a unipolar differ-
ential ±VREF input range. Supplies include a 3.3V supply
for the reference buffers, a 1.8V analog supply, a 1.8V
digital supply, and a 1.5V to 3.6V digital interface supply.
This ADC achieves 99.2dB SNR and -123dB THD,
guarantees 20-bit resolution with no-missing codes and 6
LSB INL (max).
The MAX11904 communicates data using a SPI-
compatible serial interface. The MAX11904 is offered in a
20-pin, 4mm x 4mm, TQFN package and is specified over
the -40°C to +85°C operating temperature range.
Applications
●Test and Measurement
●Automatic Test Equipment
●Medical Instrumentation
●Process Control and Industrial Automation
●Data Acquisition Systems
●Telecommunications
●Battery-Powered Equipment
Benets and Features
●High DC/AC Accuracy Provides Better Measurement
Quality
• 20-Bit Resolution with No Missing Codes
• ±6 LSB INL and ±0.9 LSB DNL at 20 Bits
• 99.2dB SNR and 99.2dB SINAD at fIN = 10kHz
• 125dB SFDR and -123dB THD at fIN = 10kHz
●High Sampling Rate SAR Architecture Enables Fast
Settling and Acquisition
• 1Msps Throughput with No Pipeline Delay
●Integration Simplifies Design
• Integrated Reference Buffers
• ±VREF Unipolar Differential Analog Input Range
●Scalable Ultra-Low Power Supply Reduces Power
Consumption
• 6.7mW at 1Msps
• Scale as 6.7µW/ksps
●Flexible Low-Voltage Supplies Save Cost
• 1.8V Analog and Digital Core Supply
• 1.5V to 3.6V Digital Interface Supply
• 3.3V REFVDD Reference Buffer Supply
●Flexible, Industry-Standard Serial Interface and Small
Package Reduce Size
• SPI-/QSPI™-/MICROWIRE®/DSP-Compatible
• 20-Pin, 4mm x 4mm, TQFN Package
Ordering Information and Selector Guide appears at end of
data sheet.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
16-Bit to 20-Bit SAR ADC Family
2nF
C0G MAX11904
CNVST
DOUT
SCLK
DIN
AVDD DVDD OVDD
REFIN
REFVDD
AIN+
AIN-
4-WIRE
SPI
INTERFACE
3.3V 3.6V 1.8V 1.8V
1.5 TO
3.6V
10Ω
10Ω
3.3V TO 0
0 TO 3.3V
REF
GNDREF
D
GND
A
GND
10µF
REF
16-BIT 18-BIT 20-BIT
1.6Msps MAX11901 MAX11903 MAX11905
1Msps MAX11900 MAX11902 MAX11904
MAX11904 20-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
19-7449; Rev 2; 2/18
Application Diagram
EVALUATION KIT AVAILABLE
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
TABLE OF CONTENTS
General Description ............................................................................ 1
Applications .................................................................................. 1
Features and Benefits .......................................................................... 1
Application Diagram ............................................................................ 1
16-Bit to 20-Bit SAR ADC Family ................................................................. 1
Absolute Maximum Ratings ...................................................................... 4
Package Thermal Characteristics ................................................................. 4
Electrical Characteristics ........................................................................ 4
Typical Operating Characteristics ................................................................. 8
Pin Configuration ............................................................................. 12
Pin Description ............................................................................... 12
Functional Diagram ........................................................................... 13
Detailed Description........................................................................... 14
Analog Inputs ..............................................................................14
Input Settling ...............................................................................16
Input Filtering ..............................................................................16
Voltage Reference Configurations ..............................................................17
Transfer Function ...........................................................................17
Digital Interface .............................................................................. 19
SPI Timing Diagram .........................................................................20
Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register Read ..............................................................................22
Register Map ................................................................................ 23
Mode Register..............................................................................23
Conversion Result Register ...................................................................24
Chip ID Register ............................................................................24
Typical Application Circuit ...................................................................... 24
Single-Ended Unipolar Input to Differential Unipolar Output ..........................................24
Single-Ended Bipolar Input to Differential Unipolar Output ...........................................24
Layout, Grounding, and Bypassing ............................................................... 24
Definitions................................................................................... 27
Integral Nonlinearity.......................................................................27
Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Offset Error .............................................................................27
Gain Error...............................................................................27
Signal-to-Noise Ratio......................................................................27
Signal-to-Noise Plus Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
TABLE OF CONTENTS (continued)
LIST OF FIGURES
LIST OF TABLES
Figure 1. Signal Ranges........................................................................ 14
Figure 2. Simplified Model of Input Sampling Circuit.................................................. 15
Figure 3. Conversion Frame, SAR Conversion, Track and Read Operation ................................ 15
Figure 4. Ideal Transfer Characteristic ............................................................ 18
Figure 5. Read During Track Phase............................................................... 19
Figure 6. Read During SAR Conversion Phase...................................................... 19
Figure 7. Split Read Mode ...................................................................... 20
Figure 8. SPI Interface Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. DIN Timing for Register Write Operations .................................................. 21
Figure 10. Timing Diagram for Data Out Reading After Conversion ...................................... 21
Figure 11. Mode Register Write .................................................................. 22
Figure 12. Register Read ....................................................................... 22
Figure 13. Unipolar Single-Ended Input............................................................ 25
Figure 14. Bipolar Single-Ended Input............................................................. 25
Figure 15. Top Layer Sample Layout .............................................................. 26
Table 1. ADC Driver Amplifier Recommendation..................................................... 16
Table 2. Voltage Reference Configurations ......................................................... 17
Table 3. MAX11904 External Reference Recommendations............................................ 17
Table 4. Transfer Characteristic .................................................................. 18
Table 5. DOUT Driver Strength .................................................................. 23
Effective Number of Bits ...................................................................27
Total Harmonic Distortion ..................................................................27
Spurious-Free Dynamic Range ..............................................................27
Aperture Delay...........................................................................27
Aperture Jitter ...........................................................................27
Full-Power Bandwidth .....................................................................27
Selector Guide ............................................................................... 28
Ordering Information .......................................................................... 28
Chip Information .............................................................................. 28
Package Information .......................................................................... 28
Revision History .............................................................................. 29
REFVDD, REF, REFIN, OVDD to GND ..................-0.3V to +4V
AVDD, DVDD to GND .............................................-0.3V to +2V
DGND to AGND, REFGND ..................................-0.3V to +0.3V
AIN+, AIN- to GND ...... -0.3V to the lower of (VREF + 0.3V) and
+4V or ±130mA
SCLK, DIN, DOUT, CNVST, to GND ........... -0.3V to the lower of
(VOVDD + 0.3V) and +4V
Maximum Current into Any Pin...........................................50mA
Continuous Power Dissipation (TA = +70°C)
TQFN (derate 30.30mW/°C above +70°C).............2424.2mW
Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) ....................................... +260°C
TQFN
Junction-to-Ambient Thermal Resistance (θJA).... ......33°C/W
Junction-to-Case Thermal Resistance (θJC) ....... ........ 2°C/W
(Note 1)
(fSAMPLE = 1Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Input Voltage Range (Note 3) (AIN+) - (AIN-) -VREF +VREF V
Absolute Input Voltage Range AIN+, AIN- relative to AGND -0.1 VREF +
0.1 V
Common-Mode Input Range [(AIN+) + (AIN-)]/2 VREF/2 -
0.1 VREF/2 VREF/2
+ 0.1 V
Input Leakage Current Acquisition phase -1 0.001 +1 µA
Input Capacitance 32 pF
STATIC PERFORMANCE (Note 4)
Resolution N 20 Bits
Resolution LSB VREF = 3.3V 6.3 µV
No Missing Codes 20 Bits
O󰀨set Error (Note 4) -10 ±1 +10 LSB
O󰀨set Temperature Coe󰀩cient ±0.01 LSB/°C
Gain Error Referred to REFIN reference input -175 ±20 +175 LSB
Gain Error Temperature
Coe󰀩cient (Note 5) Referred to REFIN reference input ±0.2 LSB/°C
Gain Error Referred to REF pins -42 ±10 +42 LSB
Gain Error Temperature
Coe󰀩cient (Note 5) Referred to REF pins ±0.12 LSB/°C
Integral Nonlinearity INL -6 ±1.5 +6 LSB
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
Electrical Characteristics
(fSAMPLE = 1Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Di󰀨erential Nonlinearity
(Note 6) DNL -0.9 ±0.5 +0.9 LSB
Analog Input CMR CMR DC 16 LSB/V
Power-Supply Rejection
(Note 7) PSR PSR vs. AVDD 2 LSB/V
Power-Supply Rejection
(Note 7) PSR PSR vs. REFVDD 2 LSB/V
Transition Noise 4 LSBRMS
EXTERNAL REFERENCE
REF Voltage Input Range VREF 2.5 3.3 3.6 V
Load Current IREF 1Msps, VREF = 3.3V 350 µA
REF Input Capacitance 1 nF
REFERENCE BUFFER
REFIN Input Voltage Range VREFIN VREF < (VREFVDD - 200mV) 2.5 3
V
REFVDD
- 200mV
V
REFIN Input Current IREFIN 1 nA
Turn-On Settling Time CEXT = 10µF on REF pin,
CREFIN = 0.1µF on REFIN pin 20 ms
External Compensation
Capacitor CEXT REF pins 4.7 10 µF
DYNAMIC PERFORMANCE (Note 8)
Dynamic Range Internal RefBu󰀨er, -60dBFS input 99.4 dB
Signal-to-Noise Ratio SNR Internal RefBu󰀨er, fIN = 10kHz 98 99.2 dB
Signal-to-Noise Plus Distortion SINAD Internal RefBu󰀨er, fIN = 10kHz,
-0.1dBFs 98 99.2 dB
Spurious-Free Dynamic Range SFDR Internal RefBu󰀨er, fIN = 10kHz 125 dB
Total Harmonic Distortion THD Internal RefBu󰀨er, fIN = 10kHz -123 dB
Total Harmonic Distortion THD Internal RefBu󰀨er, fIN = 100kHz -115 dB
Total Harmonic Distortion THD Internal RefBu󰀨er, fIN = 250kHz -107 dB
SAMPLING DYNAMICS
Throughput 0 1 Msps
Full-Power Bandwidth -3dB point 20 MHz
-0.1dB point 3
Acquisition Time tACQ 150 ns
Aperture Delay
Time delay from CNVST rising edge
to time at which sample is taken for
conversion
1 ns
Aperture Jitter 3 psRMS
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Electrical Characteristics (continued)
(fSAMPLE = 1Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Analog Supply Voltage AVDD 1.7 1.8 1.9 V
Digital Supply Voltage DVDD 1.7 1.8 1.9 V
Reference Bu󰀨er Supply
Voltage REFVDD 2.7 3.3 3.6 V
Interface Supply Voltage OVDD 1.5 3.6 V
Analog Supply Current IAVDD VAVDD = 1.8V 1.75 2.3 mA
Digital Supply Current IDVDD VDVDD = 1.8V 1.5 1.9 mA
Reference Bu󰀨er Supply
Current IREFVDD
VREFVDD = 3.6V, internal bu󰀨ers
enabled 3.3 3.55 mA
Reference Bu󰀨er Supply
Current IREFVDD
VREFVDD = 3.6V, internal bu󰀨ers
powered down 0.2 mA
Interface Supply Current
(Note 9) IOVDD
VOVDD = 1.5V 0.27 mA
VOVDD = 3.6V 1
Shutdown Current For AVDD, DVDD, REFVDD 1 µA
Shutdown Current For DVDD 1 µA
Power Dissipation
VAVDD = 1.8V, VDVDD = 1.8V,
VREFVDD = 3.3V, internal reference
bu󰀨ers disabled
6.7 8.4 mW
DIGITAL INPUTS (DIN, SCLK, CNVST)
Input Voltage High VIH VOVDD = 1.5V to 3.6V 0.7 x
VOVDD
V
Input Voltage Low VIL VOVDD = 1.5V to 3.6V 0.3 x
VOVDD
V
Input Capacitance CIN 10 pF
Input Current IIN VIN = 0V or VOVDD 1 µA
DIGITAL OUTPUTS (DOUT)
Output Voltage High VOH ISOURCE = 2mA VOVDD -
0.4 V
Output Voltage Low VOL ISINK = 2mA 0.4 V
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Electrical Characteristics (continued)
(fSAMPLE = 1Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Note 2: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and device characterization.
Note 3: See the Analog Inputs section.
Note 4: See the Definitions section at the end of the data sheet.
Note 5: See the Definitions section at the end of the data sheet. Error contribution from the external reference not included.
Note 6: Parameter is guaranteed by design.
Note 7: Defined as the change in positive full-scale code transition caused by a ±5% variation in the supply voltage.
Note 8: Sine wave input, fIN = 10kHz, AIN = -0.1dB below full scale.
Note 9: CLOAD = 10pF on DOUT. fCONV = 1Msps. All data is read out.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING
DIN to SCLK Rising Edge
Setup t14 ns
DIN to SCLK Rising Edge Hold t21 ns
DOUT End-Of-Conversion
Low Time t315 ns
DOUT to SCLK Rising
Edge Hold t42.5 ns
DOUT to SCLK Rising
Edge Setup t5100MHz SCLK 1 ns
SCLK High t64.5 ns
SCLK Period t710 ns
SCLK Low t84.5 ns
CNVST Rising Edge To SCLK
Rising Edge t90 ns
SCLK Rising Edge to CNVST
Rising Edge t10 25 ns
CNVST High t11 25 ns
CNVST High to EOC t12 850 ns
Conversion Period t13 1000 ns
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Electrical Characteristics (continued)
(VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.8V, VREFVDD = 3.6V, fSAMPLE = 1Msps, VREF = 3.3V, Internal Ref Bu󰀨er On, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
-4
-3
-2
-1
0
1
2
3
4
-40 -25 -10 520 35 50 65 80 95 110 125
DNL (LSB)
TEMPERATURE (oC)
DNL vs. TEMPERATURE
MAX DNL (LSB)
MIN DNL (LSB)
toc4
-4
-3
-2
-1
0
1
2
3
4
1.70 1.73 1.75 1.78 1.80 1.83 1.85 1.88 1.90
DNL (LSB)
VAVDD (V)
DNL vs. AVDD SUPPLY VOLTAGE
MAX DNL (LSB)
MIN DNL (LSB)
VREFVDD = 3.6V
V
REF
= 3.3V
toc6
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
-40 -25 -10 520 35 50 65 80 95 110 125
INL (LSB)
TEMPERATURE (oC)
INL vs. TEMPERATURE
MAX INL (LSB)
MIN INL (LSB)
toc3
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
1.70 1.73 1.75 1.78 1.80 1.83 1.85 1.88 1.90
INL (LSB)
VAVDD (V)
INL vs. AVDD SUPPLY VOLTAGE
MAX INL (LSB)
MIN INL (LSB)
VREFVDD = 3.6V
VREF = 3.3V
toc5
toc1
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Typical Operating Characteristics
(VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.8V, VREFVDD = 3.6V, fSAMPLE = 1Msps, VREF = 3.3V, Internal Ref Bu󰀨er On, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
-20
-16
-12
-8
-4
0
4
8
12
16
20
-40 -25 -10 520 35 50 65 80 95 110 125
ERROR (LSB)
TEMPERATURE (°C)
OFFEST ERROR (LSB)
GAIN ERROR (LSB)
OFFSET AND GAIN ERROR vs. TEMPERATURE
VREF =3.3V
VREFVDD = 3.6V
toc9
-4
-2
0
2
4
6
8
10
12
-8
-6
-4
-2
0
2
4
6
8
2.7 2.8 2.9 33.1 3.2 3.3 3.4 3.5 3.6
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
VREFVDD (V)
Offset Error (LSB)
Gain Error (LSB)
VREF = 2.5V
VAVDD = 1.8V
OFFSET AND GAIN ERROR vs. REFVDD VOLTAGE
toc11
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
INL (LSB)
VREFVDD (V)
INL vs. REFVDD SUPPLY VOLTAGE
MAX INL (LSB)
MIN INL (LSB)
VAVDD = 1.8V
VREF = 2.5V
toc7
-4
-2
0
2
4
6
8
10
12
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
1.7 1.75 1.8 1.85 1.9
GAIN ERROR (LSB)
OFFSET ERROR (LSB)
VAVDD (V)
Offset Error (LSB)
Gain Error (LSB)
VREF = 3.3V
VREFVDD = 3.6V
OFFSET AND GAIN ERROR vs. AVDD SUPPLY VOLTAGE
toc10
0
1000
2000
3000
4000
5000
6000
7000
8000
524270
524274
524278
524282
524286
524290
524294
524298
524302
524306
NUMBER OF OCCURRENCES
OUTPUT CODE (DECIMAL)
OUTPUT NOISE HISTOGRAM
toc12
STDEV = 3.8 LSB
-4
-3
-2
-1
0
1
2
3
4
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
DNL (LSB)
VREFVDD (V)
DNL vs. REFVDD SUPPLY VOLTAGE
MAX DNL (LSB)
MIN DNL (LSB)
VAVDD = 1.8V
VREF = 2.5V
toc8
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Typical Operating Characteristics (continued)
(VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.8V, VREFVDD = 3.6V, fSAMPLE = 1Msps, VREF = 3.3V, Internal Ref Bu󰀨er On, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
115
117
119
121
123
125
127
129
131
133
135
-40 -25 -10 520 35 50 65 80 95 110 125
SFDR AND THD (dB)
TEMPERATURE (°C)
-THD
SFDR
SFDR AND THD vs. TEMPERATURE
toc18
96
97
98
99
100
101
102
-40 -25 -10 520 35 50 65 80 95 110 125
SNR AND SINAD (dB)
TEMPERATURE (°C)
SNR
SINAD
SNR AND SINAD vs. TEMPERATURE
toc17
0
4000
8000
12000
16000
20000
24000
524270
524274
524278
524282
524286
524290
524294
524298
524302
524306
OUTPUT CODE (DECIMAL)
OUTPUT NOISE HISTOGRAM
16 SAMPLES AVERAGE toc14
STDEV = 1.1 LSB
0
2000
4000
6000
8000
10000
12000
14000
524270
524274
524278
524282
524286
524290
524294
524298
524302
524306
NUMBER OF OCCURRENCES
OUTPUT CODE (DECIMAL)
OUTPUT NOISE HISTOGRAM
4 SAMPLES AVERAGE toc13
STDEV = 2.0 LSB
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Typical Operating Characteristics (continued)
(VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.8V, VREFVDD = 3.6V, fSAMPLE = 1Msps, VREF = 3.3V, Internal Ref Bu󰀨er On, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
-40 -25 -10 520 35 50 65 80 95 110 125
CURRENT (mA)
TEMPERATURE (°C)
IOVDD
IREFVDD (BUFFER OFF)
IREFVDD
IDVDD
IAVDD
CURRENT vs. TEMPERATURE
toc21
110
112
114
116
118
120
122
124
126
128
130
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3
SFDR AND THD (dB)
VREF (V)
SFDR
-THD
THD AND SFDR vs. REFERENCE VOLTAGE
toc20
94
95
96
97
98
99
100
22.2 2.4 2.6 2.8 33.2 3.4 3.6
SNR AND SINAD (dB)
VREF (V)
SINAD
SNR
SNR AND SINAD vs. REFERENCE VOLTAGE
toc19
0
5
10
15
20
25
30
-40 -25 -10 520 35 50 65 80 95 110 125
SHUTDOWN CURRENT (µA)
TEMPERATURE (°C)
IAVDD
IOVDD
IREFVDD
IDVDD
SHUTDOWN CURRENT vs. TEMPERATURE
toc22
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.3 0.5 0.8 1.0
CURRENT (mA)
SAMPLING RATE (Msps)
CURRENT vs. SAMPLING RATE
IDVDD
IOVDD
IAVDD
toc23
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Typical Operating Characteristics (continued)
PIN NAME I/O FUNCTION
1, 2 REF I/O Reference. REF is a bypass pin for the reference either driven by the internal reference bu󰀨ers
or the external reference directly. Bypass these pins with 10µF capacitors to REFGND.
3, 4 REFGND I Reference Ground
5 AIN- I Negative Analog Input
6 AIN+ I Positive Analog Input
7 AGND I Analog Ground
8 OVDD I Digital Interface Supply. Nominally at 1.8V. Bypass to DGND with a 10µF capacitor in parallel
with a 0.1µF capacitor (10µF || 0.1µF).
9 DOUT O Digital Output Data
10 DGND I Digital Ground
11 DVDD I Digital Supply. Nominally at 1.8V. Bypass with a 10µF capacitor in parallel with a 0.1µF
capacitor (10µF || 0.1µF).
12 SCLK I Serial Clock Input
13 CNVST I Conversion Start. The analog inputs (AIN+, AIN-) are sampled at the rising edge and conversion
process is started.
14 DIN I Serial Data Input. DIN data is latched into the serial interface on the rising edge of SCLK.
15 DGND I Digital Ground
REF
AIN-
REF
DIN
SCLK
DVDD
DGND
AGND
AVDD
REFIN
DOUT
OVDD
AGND
AIN+
+
REFGND CNVST
AGND
DGND
REFVDD
TQFN
4mm × 4mm
MAX11904
TOP VIEW
REFGND
10
9876
11
12
13
14
15
5
4
3
2
1
1617
18
1920
EXPOSED PAD IS GROUND. IT MUST BE SOLDERED TO PCB.
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12
MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Pin Description
Pin Conguration
PIN NAME I/O FUNCTION
16 REFVDD I Reference Bu󰀨er Supply. Nominally at 3.3V. Bypass to AGND with a 10µF capacitor in parallel
with a 0.1µF capacitor (10µF || 100nF).
17, 18 AGND I Analog Ground.
19 AVDD I Analog Supply. Nominally at 1.8V. Bypass to AGND with a 10µF capacitor in parallel with a
0.1µF capacitor (10µF || 100nF).
20 REFIN I Input for the Internal Reference Bu󰀨er. Voltage must be at least 200mV lower than
REFVDD voltage. If REFIN = 0V, reference bu󰀨er will be disabled.
— EP — Exposed Pad. Must be connected to the same plane as AGND.
20-BIT ADC
REFVDD
REFGND
REF
REF
AIN+
AIN-
INTERFACE
DIN
SCLK
DOUT
CNVST
REFIN AVDD DVDD
AGND DGND
MAX11904
OVDD
REFERENCE
BUFFER
REFERENCE
BUFFER
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13
MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Functional Diagram
Pin Description (continued)
Detailed Description
The MAX11904 is a 20-bit, 1Msps maximum sampling
rate, fully differential input, single-channel SAR ADC with
SPI interface. This part features industry-leading sample
rate and resolution, while consuming very low power. The
MAX11904 has an integrated reference buffer to minimize
board space, component count, and system cost. An
internal oscillator drives the conversion and sets conver-
sion time, easing external timing considerations.
Analog Inputs
Both analog inputs, AIN+ and AIN-, range from 0V to
VREF. Thus, the differential input interval VDIFF = (AIN+)
- (AIN-) ranges from -VREF to +VREF, and the full-scale
range is:
REF
FSR 2 x V=
The nominal resolution step width of the least significant
bit (LSB) is:
N
FSR
LSB ,N 20
2
= =
The differential analog input must be centered around
a signal common mode of VREF/2, with a tolerance of
±100mV.
The reference voltage can range from 2.5V to the refer-
ence supply, REFVDD, if an external reference buffer
is used. When using the on-board reference buffer the
reference voltage can range from 2.5V to 200mV below
reference supply REFVDD. This will guarantee adequate
headroom for the internal reference buffers.
Figure 1 illustrates signal ranges for AIN+/AIN-, reference
voltage VREF and reference supply voltage REFVDD.
Figure 2 shows the input equivalent circuit of MAX11904.
The ADC samples both inputs, AIN+ and AIN-, with a fully
differential on-chip track-and-hold exhibiting no pipeline
delay or latency.
The MAX11904 has dedicated input clamps to protect
the inputs from overranging. Diodes D1 and D2 provide
ESD protection and act as a clamp for the input voltages.
Diodes D1/D2 can sustain a maximum forward current
of 100mA. The sampling switches connect inputs to the
sampling capacitors.
Figure 3 shows the timing of the digitizing cycle: Conversion
frame, SAR conversion, Track and Read operations.
Figure 1. Signal Ranges
V
REF
0V
0.5 x V
REF
AIN+
AIN-
V
REF
≤ V
REFVDD
≤ 3.6V
IF BUFFER IS DISABLED
V
REF
+200mV ≤ V
REFVDD
≤ 3.6V
IF BUFFER IS ENABLED
200mV
REFVDD
V
time
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Figure 3. Conversion Frame, SAR Conversion, Track and Read Operation
Figure 2. Simplified Model of Input Sampling Circuit
R
ON
= 260Ω
AIN+
REFVDD
C
IN
= 30pF
D1
D2
V
DC
R
ON
= 260Ω
AIN-
REFVDD
D1
D2
C
IN
= 30pF
CNVST
SCLK
DOUT
Track
Read Data
Sample 1
SAR Conversion
1/Sample Rate
Sample 2
MSB MSB-1 LSB+1 LSB MSB MSB-1 LSB+1 LSB
Track
Read Data
SAR Conversion
1/Sample Rate
Reading sample1 during track Reading sample 2 during track
Sample 1 Sample 2
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Input Settling
During track phase (Figure 3), the sample switches are
closed and the analog inputs are directly connected to the
sample capacitors. The charging of the sample capacitor
to the input voltage is determined by the source resis-
tance and sampling capacitor size. The rising edge of
CNVST is the sampling instant for the ADC. At this instant,
the track phase ends, the sample switch opens, and the
device enters into the successive approximation (SAR)
conversion phase. In the conversion phase, a differential
comparator compares the voltage on the sample capaci-
tor against the CDAC value, which cycles through values
between VREF/2 and VREF/220 using the successive
approximation technique. The final result can be read via
the SPI bus. The ADC automatically goes back into track
phase at the end of SAR conversion and powers down its
active circuits. That is, the ADC consumes no static power
in track mode.
The conversion results will be accurate if the ADC tracks
the input signal for an interval longer than the input sig-
nal’s settling time. If the signal cannot settle within the
track time due to excessive source resistance, external
ADC drivers are required to achieve faster settling. Since
the MAX11904 has a fixed conversion time set by an
internal oscillator, track time can be increased by lowering
the sample rate for better settling.
The settling behavior is determined by the time constant
in the sampling network. The time constant depends upon
the total resistance (source resistance + switch resis-
tance) and total capacitance (sampling capacitor, external
input capacitor, PCB parasitic capacitors).
Modeling the input circuit with a single pole network, the
time constant, RTOTAL × CLOAD, of the input should not
exceed tTRACK/15, where RTOTAL is the total resistance
(source resistance + switch resistance), CLOAD is the
total capacitance (sampling capacitor, external input
capacitor, PCB parasitic capacitor), and tTRACK is the
track time.
When an ADC driver is used, it is recommended to use
a series resistance (typically 5Ω to 50Ω) between the
amplifier and the ADC input, as shown in the Application
Diagram. Below are some of the requirements for the
ADC driver amplifier:
1) Fast settling time: For a multichannel multiplexed cir-
cuit the ADC driver amplifier must be able to settle with
an error less than 0.5 LSB during the minimum track
time when a full-scale step is applied.
2) Low noise: It is important to ensure that the ADC driver
has a sufficiently low-noise density in the bandwidth
of interest of the application. When the MAX11904 is
used with its full bandwidth of 20MHz, it is preferable
to use an amplifier with an output noise spectral den-
sity of less than 3nV/√Hz, to ensure that the overall
SNR is not degraded significantly. It is recommended
to insert an external RC filter at the ADC input to
attenuate out-of-band input noise.
3) To take full advantage of the ADC’s excellent dynamic
performance, Maxim recommends the use of an ADC
driver with equal or even better THD performance.
This will ensure that the ADC driver does not limit
distortion performance in the signal path. Table 1 sum-
marizes the most important features of the MAX9632
when used as an ADC driver.
Input Filtering
Noisy input signals should be filtered prior to the ADC
driver amplifier input with an appropriate filter to minimize
noise. The RC network shown in the Application Diagram
is mainly designed to reduce the load transient seen by
the amplifier when the ADC starts the track phase. This
network also has to satisfy the settling time requirement
and provides the benefit of limiting the noise bandwidth.
Table 1. ADC Driver Amplifier Recommendation
AMPLIFIER INPUT-NOISE
DENSITY (nV/√Hz)
SMALL-SIGNAL
BANDWIDTH (MHz)
SLEW RATE
(V/µs) THD
(dB) ICC
(mA) COMMENTS
MAX9632 0.9 55 30 -128 3.9mA Ultra-low noise, wide
GBWP, single ended
MAX44205 3.1 180 180 -137 3.7mA Ultra-low distortion, wide
GBWP, fully di󰀨erential
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16
MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Voltage Reference Congurations
The MAX11904 features internal reference buffers,
helping to reduce component count and board space.
Alternatively, the user may drive the reference nodes REF
with an external reference. To use the internal reference
buffers, drive the REFIN pin with an external reference
voltage source. It will appear on the REF pin as a buffered
reference output. The internal reference buffers can be
disabled by writing to a register (see the Mode Register
section) or tying REFIN to 0V. Once the on-chip reference
buffers are disabled, REF pins can be directly driven by
external reference buffers. A simplified diagram is shown
to clarify the required connections for external reference.
A low-noise, low-temperature drift reference is required
to achieve high system accuracy. The MAX6126 and
MAX6325 are particularly well suited for use with the
MAX11904. The MAX6126 and MAX6325 offer, respec-
tively, 0.02% and 0.04% initial accuracy and 3ppm/°C and
1ppm/°C (max) temperature coefficient for high-precision
applications. Maxim recommends bypassing REFIN and
REF with a 2.2µF capacitor close to the ADC pins.
Transfer Function
Figure 4 shows the ideal transfer characteristics for the
MAX11904.
The default data format is two’s complement. However,
offset binary format can be chosen by setting mode regis-
ter BIT 1 (see the Mode Register section).
Table 4 shows the codes in terms of input voltage applied.
The data reported is with VREF of 3.0V, that gives a full-
scale range of 6V.
Table 3. MAX11904 External Reference Recommendations
Table 2. Voltage Reference Configurations
PART VOUT (V)
TEMPERATURE
COEFFICIENT
(ppm/°C, max)
INITIAL
ACCURACY
(%)
NOISE
(0.1Hz TO 10Hz)
(µVP-P)
PACKAGE
MAX6126 2.5, 3 3 0.02 1.45 µMAX-8, SO-8
MAX6325 2.5 1 0.04 1.5 SO-8
REFERENCE
CONFIGURATION
INTERNAL
REFERENCE BUFFERS REFIN VREF VREFVDD
Internal Reference Bu󰀨er ON 2.5V to VREFVDD - 0.2V 2.5V to VREFVDD - 0.2V 2.7V to 3.6V
External Reference
Bu󰀨er OFF Tie to 0V or disable
through serial interface 2.5V to VREFVDD 2.5V to 3.6V
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Table 4. Transfer Characteristic
Figure 4. Ideal Transfer Characteristic
MIDCODE VALUE DIFFERENTIAL ANALOG INPUT
FULL-SCALE RANGE = 6V (V)
HEXADECIMAL
TWO’S COMPLEMENT
HEXADECIMAL OFFSET
BINARY
FS - 1 LSB 2.99999428 0x7FFFF 0xFFFFF
Midscale + 1 LSB 0.00000572 0x00001 0x80001
Midscale 0.00000000 0x00000 0x80000
Midscale - 1 LSB -0.00000572 0xFFFFF 0x7FFFF
-FS + 1 LSB -2.99999428 0x80001 0x00001
-FS -3.00000000 0x80000 0x00000
111...111
111...110
111...101
000...000
000...001
000...010
OUTPUT CODE
(OFFSET
BINARY)
V
IN
= (AIN+) - (AIN-)
DIFFERENTIAL
ANALOG INPUT
(LSB)
FS - 1.5 x LSB
2 x V
REF
FULL SCALE
(FS)
V
IN
= +V
REF
ZERO SCALE
(ZS)
V
IN
= -V
REF
-2
19
-2
19
+1
-2
19
+2 2
19
2
19
-12
19
-2
011...111
011...110
011...101
100...000
100...001
100...010
OUTPUT CODE
(TWO'S COMPLEMENT)
V
IN
= (AIN+) - (AIN-)
DIFFERENTIAL
ANALOG INPUT
(LSB)
FS - 1.5 x LSB
-2
19
-2
19
+1
-2
19
+2 2
19
2
19
-12
19
-2
2 X V
REF
FULL SCALE
(FS)
V
IN
= +V
REF
ZERO SCALE
(ZS)
V
IN
= -V
REF
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Digital Interface
The MAX11904 has a SPI interface with CNVST control-
ling the sampling, and SCLK, DOUT, DIN forming the
standard SPI signals. The SAR conversion begins with
the rising edge of CNVST. The minimum CNVST high
time is 20ns and CNVST should be brought low before
DOUT goes low, which signals the completion of a SAR
conversion. The DOUT goes low for 10ns, followed by
the output of the MSB on the DOUT pin. The 20-bit con-
version result can then be read via the SPI interface by
sending 20 SCLK pulses. DOUT going low also signals
the start of the track phase. The ADC stays in track phase
until the next rising edge of CNVST.
The MAX11904 has three different modes to read the data:
● Reading during track phase (Figure 5)
● Reading during SAR conversion phase (Figure 6)
● Split reading (Figure 7)
When reading during track phase mode, the data is read
only while the ADC is in track mode. Figure 5 shows the
SPI signal for this reading mode.
In the reading during SAR conversion phase mode,
the data is read only in the SAR conversion phase.
Figure 6 illustrates all SPI signals for this mode. Note that
the data being read only during the SAR conversion phase
corresponds to the previous conversion frame.
Figure 5. Read During Track Phase
Figure 6. Read During SAR Conversion Phase
CNVST
SCLK
DOUT
Track
Read Data
Sample 1
SAR Conversion
1/Sample Rate
Sample 2
MSB MSB-1 LSB+1 LSB MSB MSB-1 LSB+1 LSB
Track
Read Data
SAR Conversion
1/Sample Rate
Reading sample1 during track Reading sample 2 during track
Sample 1 Sample 2
CNVST
SCLK
TRACK
READ DATA
SAMPLE 1
SAR CONVERSION
1/SAMPLE RATE
SAMPLE 2
MSB
DOUT MSB-1 LSB+1 LSB MSB MSB-1 LSB+1 LSB
TRACK
READ DATA
SAR CONVERSION
1/SAMPLE RATE
READING SAMPLE 0 DURING SAR
CONVERSION
SAMPLE 1SAMPLE 0
READING SAMPLE 1 DURING SAR
CONVERSION
MSB
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
In the split reading mode, the data is read during the track
phase and the following SAR conversion phase. Figure 7
shows the descriptive timing diagram.
At higher sampling rates, the track time may not be long
enough to allow reading all 20 bits of data. In this case,
the data read can be started in track mode, and then
continued in the subsequent SAR conversion phase. Note
that the read operation must be completed before DOUT
goes low, signaling the end of the SAR conversion phase.
Also note that no SCLK pulses should be applied close to
the sampling edge (rising edge of CNVST), to safeguard
the sampling edge from digital noise (see the Quiet Time
specification t10). This split reading feature can be used
to accommodate slower SPI clocks.
SPI Timing Diagram
Figure 8 shows the typical digital SPI interface connection
between the MAX11904 and host processor.
The dashed connections are optional.
Figure 9 shows the timing diagram for configuration reg-
isters.
Figure 10 shows the timing diagram for data output read-
ing after conversion.
Figure 7. Split Read Mode
Figure 8. SPI Interface Connection
CNVST
SCLK
DOUT
Track
Read Data
Sample 1
SAR Conversion
1/Sample Rate
Sample 2
MSB MSB-1 LSB+1 LSB MSB MSB-1
Track
Read Data
SAR Conversion
1/Sample Rate
Quiet Time
Reading sample 1
Sample 1 Sample 2
Host Processor
CNVST
DOUT
SCLK
DIN
MAX11904
CNVST
SCLK
DOUT
DIN
IRQ
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Figure 10. Timing Diagram for Data Out Reading After Conversion
Figure 9. DIN Timing for Register Write Operations
MSB MSB-1 MSB-2DOUT
t3t4
SCLK
t12
t5
0.7 x OVDD
0.3 x OVDD
t6t8
t11
t7
0.7 x OVDD
0.3 x OVDD
0.7 x OVDD
0.7 x OVDD
t
10
t
9
0.7 x OVDD
t
13
CNVST
0.7 x OVDD
t
1
t
2
0.7 x OVDD
SCLK
0.3 x OVDD
DIN
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Register Write
All SPI operations start with a command word. The structure of the command word is shown below. If there is no start
bit, i.e. DIN is low, the part will output the conversion result and then go idle (see Figures 5, 6, and 7). The 16-bit mode
register is the only register that can be written to. Figure 11 shows the waveform for a mode register write operation.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Start 0 Adr 3 Adr 2 Adr 1 Adr 0 R/W0
Register Read
A read operation is specified by setting the R/W bit high. Data will be output by the MAX11904 after the 8th rising SCLK
edge. Figure 12 shows the waveform for a mode register read.
Figure 11. Mode Register Write
Figure 12. Register Read
CNVST
SCLK
DIN
DOUT
0ST A3 A2 A0 D15 D14R/W 0 D1 D0A1
CNVST
SCLK
DIN
DOUT
0ST A3 A2 A0
D7 D6
0
D1 D0
A1 R/W
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Register Map
FUNCTION ADDRESS R/W BITS DATA WIDTH DATA
Read or Write Mode Register 0001 1 or 0 16 Mode Register
Read Conversion Result* 0010 1 20 Conversion Result
Read Chip ID 0100 1 8 Chip ID
Reserved, Do Not Use All other — — Reserved, Do Not Use
*Conversion result can also be read as shown in Figures 5, 6, and 7.
Mode Register
The reset state is: 0x0000. That is, the reference buffers are enabled if a valid reference voltage is applied at the REFIN
pin. If external reference buffers are used, tie REFIN low and the buffers will be automatically powered down.
DD[2:0] program the driver strength on DOUT pin. Higher driver strengths are for systems that have larger capacitive
loads on DOUT. The lowest driver strength that works should be chosen to save power and improve performance.
The driver strength is ordered from 1 to 6. The driver strength 1 is the weakest while the driver strength 6 is the strongest.
Table 5 shows the mapping between the register value D[2:0] and the correspondent driver strength.
Table 5. DOUT Driver Strength
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reset — — — — — DD2 DD1 DD0 — — PD
REF1
POR
pass
OTP
busy OB PD
REF2
Reset: Reset the part when high.
DD[2:0]: Program the driver strength on DOUT.
PD REF1: Power down the first reference buffer when set.
POR pass: High to indicate that POR was successful. If this bit is low, RESET should be asserted.
OTP busy: High to indicate that the device is powering up.
OB: Output data format is offset binary when high. two’s complement when low.
PD REF2: Power down the second reference buffer when set.
DD[2:0] DRIVER STRENGTH
000 4
001 5
010 6
011 Not Valid
100 1
101 2
110 3
111 Not Valid
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Conversion Result Register
A 20-bit read-only register, can be read directly or via a command read sequence.
Chip ID Register
This register holds a 4-bit code that can be used to verify the silicon revision. The ID = 1001b.
Typical Application Circuit
Real-world signals usually require conditioning before
they can be digitized by an ADC. The following outlines
common examples of analog signal processing circuits for
shifting, gaining, attenuating, and filtering signals.
Single-Ended Unipolar Input to Di󰀨erential
Unipolar Output
The circuit in Figure 13 shows how a single-ended, uni-
polar signal can interface with the MAX11904. This signal
conditioning circuit transforms a 0V to +VREF single-end-
ed input signal to a fully differential output signal with a
signal peak-to-peak amplitude of 2 x VREF and common-
mode voltage (VREF/2). In this case, the single-ended
signal source drives the high-impedance input of the first
amplifier. This amplifier drives the AIN+ input of ADC and
the second stage amplifier with peak-to-peak amplitude
of VREF and common-mode output voltage of VREF/2.
The second amplifier inverts this input signal and adds
an offset to generate an inverted signal with peak-to-peak
amplitude of VREF and common-mode output voltage of
VREF/2, which drives the AIN- input of ADC.
Single-Ended Bipolar Input to Di󰀨erential
Unipolar Output
The MAX11904 is a differential input ADC that accepts
a differential input signal with unipolar common mode.
Figure 14 shows a signal conditioning circuit that trans-
forms a -2 x VREF to +2 x VREF single-ended bipolar
input signal to a fully differential output signal with ampli-
tude peak-to-peak 2 x VREF and common-mode voltage
VREF/2.
The single-ended bipolar input signal drives the inverting
input of the first amplifier. This amplifier inverts and adds
an offset to the input signal. It also drives the AIN- input
of ADC and the second stage amplifier with peak-to-peak
amplitude of VREF and common-mode output voltage of
VREF/2. The second amplifier is also in inverting configu-
ration and drives the AIN+ input of the ADC. This ampli-
fier adds an offset to generate a signal with peak-to-peak
amplitude of VREF and common-mode output voltage
of VREF/2. The input impedance, seen by the signal
source, depends on the input resistor of the first-stage
inverting amplifier. Input impedance must be chosen care-
fully based on the output source impedance of the signal
source.
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and avoid run-
ning digital lines underneath the ADC package. A single
solid GND plane configuration with digital signals routed
from one direction and analog signals from the other pro-
vides the best performance. Connect the GND pin on the
MAX11904 to this ground plane. Keep the ground return
to the power supply for this ground low impedance and as
short as possible for noise-free operation.
A 2nF C0G ceramic chip capacitor should be placed
between AIN+ and AIN- as close as possible to the
MAX11904. This capacitor reduces the voltage transient
seen by the input source circuit.
For best performance, connect the REF output to the
ground plane with a 16V, 10µF ceramic chip capacitor
with a X5R dielectric in a 1210 or smaller case size.
Ensure that all bypass capacitors are connected directly
into the ground plane with an independent via.
Bypass AVDD, DVDD, and OVDD to the ground plane with
10µF ceramic chip capacitors on each pin as close as pos-
sible to the device to minimize parasitic inductance. For
best performance, bring the AVDD and DVDD power plane
in from the analog interface side of the MAX11904 and the
OVDD power plane from the digital interface side of the
device. Figure 15 shows the top layer of a sample layout.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
— — — — ID3 ID2 ID1 ID0
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Figure 13. Unipolar Single-Ended Input
Figure 14. Bipolar Single-Ended Input
V
REF
0V
0.5 x V
REF
R
+
-
R
S
R
S
C
S
COG MAX11904
CNVST
DOUT
SCLK
DIN
AVDD DVDD OVDD
REFIN
REFVDD
AIN+
AIN-
DSP
SPI
INTERFACE
2.5V TO
VREFVDD - 0.2V
2.7V
TO
3.6V 1.8V 1.8V
1.5V TO
3.6V
R
REF
GNDREF
D
GND
A
GND
10µF
VREF
2
REF
R
+
-
R
S
R
S
C
S
COG
MAX11904
CNVST
DOUT
SCLK
DIN
AVDD DVDD OVDD
REFIN
REFVDD
AIN+
AIN-
DSP
SPI
INTERFACE
2.5V TO
V
REFVDD
- 0.2V
2.7V
TO
3.6V 1.8V 1.8V
1.5V TO
3.6V
R
+2 x V
REF
0V
R
4R
R
+
-
4R
-2 x V
REF
V
REF
2
V
REF
2
REF
GNDREF
D
GND
A
GND
10µF
REF
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Figure 15. Top Layer Sample Layout
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MAX11904 20-Bit, 1Msps, Low-Power,
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Denitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. For these
devices, this straight line is a line drawn between the end
points of the transfer function, once offset and gain errors
have been nullified.
Di󰀨erential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification
of less than ±1 LSB guarantees no missing codes.
O󰀨set Error
The offset error is defined as the deviation between the
actual output and ideal output measured with 0V differen-
tial analog input voltage.
Gain Error
Gain error is defined as the difference between the
actual output range measured and the ideal output range
expected. It is measured with signal applied at the input
with an amplitude close to full-scale range.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the full-
scale analog input power to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization noise error only
and results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the signal power to
the noise power, which includes all spectral components
not including the fundamental, the first five harmonics,
and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s power to the power of all
the other ADC output signals:
Signal
SINAD(dB) 10 LOG Noise Distortion

= ×

+

E󰀨ective Number of Bits
The effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
SINAD - 1.76
ENOB 6.02
=
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the power
contained in the first five harmonics of the converted data
to the power of the fundamental. This is expressed as:
2345
1
PPPP
THD 10 log P

+++
= ×


where P1 is the fundamental power and P2 through P5 is
the power of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
power of the fundamental (maximum signal component)
to the power of the next-largest frequency component.
Aperture Delay
Aperture delay (tAD) is the time delay from the sampling
clock edge to the instant when an actual sample is taken.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
aperture delay.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as full-power
input bandwidth frequency.
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX11904ETP+ -40°C to +85°C 20 TQFN-EP*
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 TQFN-EP T2044+5 21-0139 90-0429
PART BITS SPEED
(ksps)
FULLY
DIFFERENTIAL
INPUT (MAX) (V)
REFERENCE
BUFFERS PACKAGE
MAX11900 16 1000 ±3.6 Internal/External 4mm x 4mm TQFN-20
MAX11901 16 1600 ±3.6 Internal/External 4mm x 4mm TQFN-20
MAX11902 18 1000 ±3.6 Internal/External 4mm x 4mm TQFN-20
MAX11903 18 1600 ±3.6 Internal/External 4mm x 4mm TQFN-20
MAX11904 20 1000 ±3.6 Internal/External 4mm x 4mm TQFN-20
MAX11905 20 1600 ±3.6 Internal/External 4mm x 4mm TQFN-20
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MAX11904 20-Bit, 1Msps, Low-Power,
Fully Di󰀨erential SAR ADC
Selector Guide
Chip Information
PROCESS: CMOS
Ordering Information Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/14 Initial release —
1 4/15 Removed future product references in the 16-Bit to 20-Bit SAR ADC Family table
and Selector Guide 1, 28
2 2/18 Updated Electrical Characteristics table 7
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc.
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MAX11904 20-Bit, 1Msps, Low-Power,
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Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.