IDT74FCT807BTPB - Integrated Device Technology, Inc.

Integrated Device Technology, Inc.

FEATURES:

• 0.5 MICRON CMOS Technology

• Guaranteed low skew < 250ps (max.)

• Very low duty cycle distortion < 350ps (max.)

• High speed: propagation delay < 2.5ns (max.)

• 100MHz operation

• TTL compatible inputs and outputs

• TTL level output voltage swings

• 1:10 fanout

• Output rise and fall time < 1.5ns (max.)

• Low input capacitance: 4.5pF typical

• High Drive: -32mA IOH, 48mA IOL

• ESD > 2000V per MIL STD-883, Method 3015;

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1995

1995 Integrated Device Technology, Inc. 9.3 DSC-4242/3

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FAST CMOS

1-TO-10

CLOCK DRIVER

IDT54/74FCT807BT/CT

3017 drw 01

O10

> 200V using machine model (C = 200pF, R = 0)

• Available in DIP, SOIC, SSOP, QSOP, Cerpack and

LCC packages

• Military product compliant to MIL-STD-883, Class B

GND

VCC

GND

VCC

GND

10 11

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

P20-1

D20-1

SO20-2

SO20-7

SO20-8

E20-1

INDEX

VCC

GND

VCC

GND

VCC

GND

VCC

O10

GND

LCC

TOP VIEW

3 2 20 19

910111213

L20-2

3017 drw 03

3017 drw 02

DESCRIPTION:

The IDT54/74FCT807BT/CT clock driver is built using

advanced dual metal CMOS technology. This low skew clock

driver features 1:10 fanout, providing minimal loading on the

preceding drivers. The IDT54/74FCT807BT/CT offers low

capacitance inputs with hysteresis for improved noise margins.

TTL level outputs and multiple power and grounds reduce

noise. The device also features -32/48mA drive capability for

driving low impedance traces.

FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS

IDT54/74FCT807BT/CT

FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.3 2

PIN DESCRIPTION

Pin Names Description

IN Input

Ox Outputs

CAPACITANCE (TA = +25°C, f = 1.0MHz)

ABSOLUTE MAXIMUM RATINGS(1)

3017 tbl 01

Symbol Parameter(1) Conditions Typ. Max. Unit

CIN Input

Capacitance VIN = 0V 4.5 6.0 pF

COUT Output

Capacitance VOUT = 0V 5.5 8.0 pF

NOTE:

1. This parameter is measured at characterization but not tested. 3017 lnk 02

Symbol Rating Commercial Military Unit

VTERM(2) Terminal Voltage

with Respect to

GND

–0.5 to +7.0 –0.5 to +7.0 V

VTERM(3) Terminal Voltage

with Respect to

GND

–0.5 to VCC

+0.5 –0.5 to VCC

+0.5 V

TAOperating

Temperature 0 to +70 –55 to +125 °C

TBIAS Temperature

Under Bias –55 to +125 –65 to +135 °C

TSTG Storage

Temperature –55 to +125 –65 to +150 °C

IOUT DC Output

Current –60 to +120 –60 to +120 mA

3017 lnk 03

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability. No terminal voltage may exceed VCC by

+0.5V unless otherwise noted.

2. Input and VCC terminals.

3. Output and I/O terminals.

IDT54/74FCT807BT/CT

FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.3 3

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified

Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. Duration of the condition can not exceed one second.

5. The test limit for this parameter is ± 5µA at TA = –55°C.

3017 lnk 04

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V

VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

II H Input HIGH Current(5) VCC = Max. VI = 2.7V — — ±1µA

II L Input LOW Current(5) VCC = Max. VI = 0.5V — — ±1µA

IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1µA

IOZL (3-State Output pins)(5) VO = 0.5V — — ±1µA

II Input HIGH Current(5) VCC = Max., VI = VCC (Max.) — — ±1µA

VIK Clamp Diode Voltage VCC = Min., IIN= –18mA — –0.7 –1.2 V

IOS Short Circuit Current VCC = Max.(3), VO = GND –60 –120 –225 mA

VOH Output HIGH Voltage VCC = Min.

VIN = VIH or VIL IOH = –12mA MIL.

IOH = –15mA COM'L. 2.4 3.3 — V

IOH = –24mA MIL.

IOH = –32mA COM'L.(4) 2.0 3.0 —

VOL Output LOW Voltage VCC = Min.

VIN = VIH or VIL IOL = 32mA MIL.

IOL = 48mA COM'L. — 0.3 0.55 V

IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V — — ±1µA

VHInput Hysteresis for all inputs — — 150 — mV

ICCL

ICCH

ICCZ

Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH VCC = Max.

VIN = 3.4V — 0.5 2.0 mA

ICCD Dynamic Power Supply Current(3) VCC = Max.

Input toggling

50% Duty Cycle

Outputs Open

VIN = VCC

VIN = GND — 0.4 0.6 mA/

MHz

ICTotal Power Supply Current(5) VCC = Max.

Input toggling

50% Duty Cycle

VIN = VCC

VIN = GND — 20.0 30.5(4) mA

Outputs Open

fi = 50MHz VIN = 3.4V

VIN = GND — 20.3 31.3(4)

3017 tbl 05

POWER SUPPLY CHARACTERISTICS

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient.

3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fi)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

fi= Input Frequency

All currents are in milliamps and all frequencies are in megahertz.

IDT54/74FCT807BT/CT

FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.3 4

IDT54/74FCT807BT IDT54/74FCT807CT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

tPLH

tPHL Propagation Delay CL = 30pF

f ≤ 67MHz 1.5 3.8 1.5 3.5 ns

tROutput Rise Time (See figure 3) — 1.5 — — 1.5 — ns

tFOutput Fall Time — 1.5 — — 1.5 — ns

tSK(o) Output skew: skew between outputs of

same package (same transition) — 0.5 — — 0.25 — ns

tSK(p) Pulse skew: skew between opposite

transitions of same output (|tPHL -– tPLH|) — 0.5 — — 0.35 — ns

tSK(t) Package skew: skew between outputs of

different packages at same power supply

voltage, temperature, package type and

speed grade

— 0.9 — — 0.75 — ns

3017 tbl 06

3017 tbl 07

3017 tbl 08

NOTES:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.

4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay

limits do not imply skew.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)

IDT54/74FCT807BT IDT54/74FCT807CT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

tPLH

tPHL Propagation Delay 50Ω to VCC/2,

CL = 10pF 1.3 2.7 1.3 2.5 ns

tROutput Rise Time (See figure 1) — 1.5 — — 1.5 — ns

tFOutput Fall Time or 50Ω ac — 1.5 — — 1.5 — ns

tSK(o) Output skew: skew between outputs of

same package (same transition) termination,

CL = 10pF — 0.5 — — 0.25 — ns

tSK(p) Pulse skew: skew between opposite

transitions of same output (|tPHL -– tPLH|) (See figure 2)

f ≤ 100MHz — 0.5 — — 0.35 — ns

tSK(t) Package skew: skew between outputs of

different packages at same power supply

voltage, temperature, package type and

speed grade

Outputs

connected in

groups of two

— 0.9 — — 0.65 — ns

IDT54/74FCT807BT IDT54/74FCT807CT

Com'l. Mil. Com'l. Mil.

Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

tPLH

tPHL Propagation Delay CL = 50pF

f ≤ 40MHz 1.5 3.8 1.5 3.5 ns

tROutput Rise Time (See figure 4) — 1.5 — — 1.5 — ns

tFOutput Fall Time — 1.5 — — 1.5 — ns

tSK(o) Output skew: skew between outputs of

same package (same transition) — 0.5 — — 0.35 — ns

tSK(p) Pulse skew: skew between opposite

transitions of same output (|tPHL -– tPLH|) — 0.60 — — 0.45 — ns

tSK(t) Package skew: skew between outputs of

different packages at same power supply

voltage, temperature, package type and

speed grade

— 1.0 — — 0.75 — ns

IDT54/74FCT807BT/CT

FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.3 5

TEST CIRCUITS

50Ω TO VCC/2, CL = 10pF

Pulse

Generator

D.U.T.

OUT

50pF

Pulse

Generator

D.U.T.

OUT

30pF

Pulse

Generator

D.U.T.

OUT

Ω

10pF

220pF

Pulse

Generator

D.U.T.

OUT

100

Ω

100

Ω

10pF

Pulse

Generator

D.U.T.

OUT

50pF 500

Ω

500

Ω

7.0V

3017 drw 05

The capacitor value for ac termination is determined by the operating

frequency. For very low frequencies a higher capacitor value should be

selected. Figure 2.Figure 1.

3017 drw 06

3017 drw 04

3017 drw 07

3017 drw 08

Figure 4.Figure 3.

Figure 5.

50Ω AC TERMINATION, CL = 10pF

CL = 50pF CIRCUITCL = 30pF CIRCUIT

ENABLE AND DISABLE TIME CIRCUIT ENABLE AND DISABLE TIME

SWITCH POSITION

Test Switch

Disable LOW

Enable LOW Closed

Disable HIGH

Enable HIGH Open

DEFINITIONS:

CL= Load capacitance: includes jig and probe capacitance.

RT =Termination resistance: should be equal to ZOUT of the Pulse

Generator.

3017 lnk 09

IDT54/74FCT807BT/CT

FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.3 6

TEST WAVEFORMS

PACKAGE DELAY OUTPUT SKEW- tSK(o)

PULSE SKEW - tSK(p) PACKAGE SKEW - tSK(t)

ENABLE AND DISABLE TIMES

3017 drw 10

3017 drw 09

3017 drw 11 Package 1 and Package 2 are same device type and speed grade

3017 drw 12

tPLH1

OUTPUT 1

OUTPUT 2

tSK(o)

tPLH2

VOH

1.5V

VOL

VOH

1.5V

VOL

INPUT tPHL1

tPHL2

tSK(o)

VOH

tPLH tPHL

VOL

1.5V

tRtF

2.0V

0.8V

INPUT tPLH1

PACKAGE 1 OUTPUT

PACKAGE 2 OUTPUT

tSK(t)

tPLH2

VOH

1.5V

VOL

VOH

1.5V

VOL

tPHL1

tPHL2

tSK(t)

CONTROL

INPUT

1.5V

3.5V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH

CLOSED

SWITCH

OPEN

VOL

VOH

0.3V

tPLZtPZL

tPZH tPHZ

3.5V

1.5V

ENABLE DISABLE

tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

tPLH tPHL

VOH

1.5V

VOL

tSK(p) = |tPHL - tPLH|

tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

INPUT

OUTPUT

INPUT

OUTPUT

3017 drw 13

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH

2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

IDT54/74FCT807BT/CT

FAST CMOS 1-TO-10 CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.3 7

ORDERING INFORMATION

1-to-10 Clock Driver

IDT XX

Temp. Range XXXX

Device Type X

Package X

Process

Blank

807BT

807CT

Commercial

MIL-STD-883, Class B

Plastic DIP

CERDIP

Small Outline IC

Leadless Chip Carrier

CERPACK

Shrink Small Outline IC

Quarter-size Small Outline IC

74 –55

C to +125

C to +70

FCT

3017 drw 14