Digital Delay Units series DDU-12 10 Taps ECL Interfaced Features: = Input & Output ECL Buffered = 10 Equally Spaced Taps = PC Board Economy Achieved Specifications: Total Delay Tolerance: + 5% or better, Test Conditions: Input pulse-width: 150% of total delay. Input pulse rise-time: =.6 ns. Input pulse voltage: .7V Rise-time measured from 20% to 80% of leading edge. Delay time measured at 50% of leading edge. All measurements taken Ve; - 5.2V and T, 25C. Unless otherwise specified, all time-delays are referenced to the input pin. or 2 ns whichever is greater. m No. Taps: 10 equally spaced. = Rise-time: 2 ns typical. = Supply voltage: - 5.2V = Operating Temperature: - 30 C to 85C. m Power Dissipation: | 400 mw typ. (no load). = Temperature coefficient: 100 PPM/C. m DC Parameters: See ECL-10K Lagic Table on Page 6. ft or case stand-offs + 1-650: O78 Total Tap Part No. Detay Delay (ns) (ns) % DDU-12-10 9 41 + 3 * DDU-12-20 18 2 t 4 * DDU-12-25 22.5 25+ 4 DDU-12-40 40 44 5 DDU-12-50 50 +10 DDU-12-75 75 75415 DDU-12-100 100 10 $2.0 DDU-12-150 150 15 +2.0 DDU-12-200 200 20 +20 DDU-12-250 250 25 +20 DDU- 12-300 300 30 +20 DDU- 12-400 400 49 +2.0 DDU- 12-500 500 50 +25 DDU-12-750 750 75 t44 DDU- 12-1000 1000 400 45.0 DDU-12-1500 1500 1680 +7.0 *Time delay measurements referenced to 1st tap. 3 ns + 1 ns inherent delay. Tap Ve Bg BB Be Be Pine 31 3 90-04! 99- 29 44 eR 42: 3} bow ol Pull-down resistoron oulpul taps. not provided inside the unit: 3 Mt. Prospect Avenue. Clifton. New Jersey 07013 @ (201) 773-2299 m FAX (201) 773-9672 # TWX 710-989-7008 15