1/72April 1999
DESCRIPTION
The TS68EN360 QUad Integrated Communication Controller
(QUICC) is a versatile one-chip integrated microprocessor and
peripheral combination that can be used in a variety of controller
applications. It particularly excels in communications activities.
The QUICC (pronounced ”quick”) can be described as a next-
generation TS68302 with higher performance in all areas of
device operation, increased flexibility , major extensions in capa-
bility, and higher integration. The term ”quad” comes from the fact
that there are four serial communications controllers (SCCs) on
the device; however, there are actually seven serial channels:
four SCCs, two serial management controllers (SMCs), and one
seral peripheral interface (SPI).
MAIN FEATURES
CPU32+ Processor (4.5 MIPS at 25 MHz)
- 32-Bit Version of the CPU32 Core (Fully Compatible with
the CPU32)
- Background Debug Mode
- Byte-Misaligned Addressing
Up to 32-Bit Data Bus
(Dynamic Bus Sizing for 8 and 16 Bits)
Up to 32 Address Lines (At Least 28 Always Available)
Complete Static Design (0-25 MHz Operation)
Slave Mode To Disable CPU32+
(Allows Use with External Processors)
- Multiple QUICCs Can Share One System Bus (One Master)
- TS68040 Companion Mode Allows QUICC To Be an
TS68040 Companion Chip and Intelligent Peripheral
(22 MIPS at 25 MHz)
- Peripheral device of TSPC603e (see DC415/D note)
Four General-Purpose Timers
- Superset of MC68302 Timers
- Four 16-Bit Timers or Two 32-Bit Timers
- Gate Mode Can Enable/Disable Counting
Two Independent DMAs (IDMAs)
System Integration Module (SIM60)
Communications Processor Module (CPM)
Four Baud Rate Generators
Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full
10-Mbps Support) (see § 6.4)
Two SMC
VCC = +5 V ± 5 %
fmax = 25 MHz and 33 MHz
Military temperature range : –55°C < TC < +125°C
PD = 1.4 W at 25 MHz ; 5.25 V
2 W at 33 MHz ; 5.25 V
R suffix
PGA 241
Ceramic Pin Grid Array
Cavity Up
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
Cavity Down
SCREENING / QUALITY
This product is manufactured in full compliance with :
MIL-STD-883 (class B)
QML (class Q)
or according to TCS standard
TS68EN360
32:BIT QUAD INTEGRATED
COMMUNICATION CONTROLLER
TS68EN360
2/72
SUMMARY
A. GENERAL DESCRIPTION 3. . . . . . . . . . . .
1. INTRODUCTION 3. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. PIN ASSIGNMENTS 4. . . . . . . . . . . . . . . . . . . . . . . . .
?+'* /3 7/* 77'>
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3. SIGNAL DESCRIPTION 6. . . . . . . . . . . . . . . . . . . . . .
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B. DETAILED SPECIFICATIONS 10. . . . . . . .
1. SCOPE 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. APPLICABLE DOCUMENTS 10. . . . . . . . . . . . . . . .
3. REQUIREMENTS 10. . . . . . . . . . . . . . . . . . . . . . . . . .
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4. QUALITY CONFORMANCE INSPECTION 12. . . .
5. ELECTRICAL CHARACTERISTICS 12. . . . . . . . . .
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6. FUNCTIONAL DESCRIPTION 65. . . . . . . . . . . . . . .
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7. PREPARATION FOR DELIVERY 67. . . . . . . . . . . . .
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8. HANDLING 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9. PACKAGE MECHANICAL DATA 68. . . . . . . . . . . . .
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10. ORDERING INFORMATION 70. . . . . . . . . . . . . . . . .
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TS68EN360
3/72
A.GENERAL DESCRIPTION
1. INTRODUCTION
QUICC ARCHITECTURE OVERVIEW
The QUICC is 32-bit controller that is an extension of other members of the TS68300 family . Like other members of the TS68300 f amily ,
the QUICC incorporates the intermodule bus (IMB). (The TS68302 is an exception, having an 68000 bus on chip). The IMB provides a
common interface for all modules of the TS68300 family, which allows the development of new devices more quickly by using the library of
existing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to
implement this option.
The QUICC is comprised of three modules : the CPU32+ core, the SIM60, and the CPM. Each module utilizes the 32-bit IMB.
The TS68EN360 QUICC block diagram is shown in Figure 1.
FOURTEEN SERIAL
DAMs
TWO
SEVEN
SERIAL
CHANNELS TIMER SLOT
ASSIGNER OTHER
FEATURES
INTERRUPT
CONTROLLER
RISC
CONTROLLER 2,5–KBYTE
DUAL–PORT
RAM
COMMUNICATIONS PROCESSOR
FOUR
GENERAL–
PURPOSE
TIMERS
IDMAs
EXTERNAL
BUS
INTERFACE
DRAM
CONTROLLER
AND
CHIP SELECTS
BREAKPOINT
LOGIC
JTAG
OTHER
FEATURES
CPU32+
CORE CLOCK
GENERATION
PERIODIC
TIMER
SYSTEM
PROTECTION
SIM 60
IMB (32BIT)
CPM
SYSTEM
I/F
Figure 1: QUICC Block Diagram
TS68EN360
4/72
2. PIN ASSIGNMENTS
2.1. 241-Lead Pin Grid Array (PGA)
123456789101112131415161718
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
D2
PA15
D4
D7
D10
D13
D16
D19
CLKO2
CLKO1
D21
D24
D27
D30
FC2
SIZ1
SIZ0
D0
PA12
D3
D6
D9
D12
D15
D18
Vcc
D20
D23
D26
D29
FC3
FC1
A29
A28
XTAL
PA13
PA9
D1
D5
D8
D11
D14
D17
GND
D22
D25
D28
D31
FC0
A30
EXTAL
MODCK0
NC4
PA10
PA6
PA14
GND
GND
GND
GND
Vcc
Vccclk
GND
GND
Vcc
GND
A31
XFC
MODCK1
GND
A26
PA7
PA3
PA11
GND
Vcc
GND
GNDclk
Vcc
GND
Vccsyn
Vcc
A27
A25
A24
PA5
PA2
PA8
GND
GND
GNDsyn
GND
A23
A22
A21
PA1
PB17
PA4
Vcc
GND
A20
A19
A18
PB16
PB15
PA0
Vcc
Vcc
A17
A16
A15
PB13
PB12
PB14
GND
NC
GND
Vcc
A14
A13
A12
PB10
PB11
PB9
GND
GND
A8
A10
A11
PB7
PB8
PB6
Vcc
GND
A4
A7
A9
PB4
PB5
PB3
Vcc
GND
A0
A5
A6
PB1
PB2
PB0
GND
Vcc
Vcc
GND
CS7
A1
A3
PC10
PC11
PC8
GND
GND
GND
Vcc
GND
Vcc
GNDs1
Vcc
CS4
IRQ7
A2
PC7
PC9
PC4
GND
GND
GND
Vcc
GND
Vcc
GND
GNDs2
Vcc
GND
Vcc
GND
CS1
CS5
TRIS
PC3
PC6
PC0
IRQ5
HALT
AVEC
TD1
TRST
IRQ4
IFETCH
NC2
IPIPE0
PRTY2
NC3
CAS0
CAS3
CS2
CS6
PC1
PC5
IRQ3
BERR
RMC
TDO
TCK
BKPT
BGACK
NC1
BCLRO
AS
PRTY1
DSACK1
R/W
FREEZE
CAS2
CS3
IRQ2
PC2
IRQ1
RESETS
PERR
TMS
RESETH
IRQ6
BG
BR
OE
IPIPE1
PRTY0
PRTY3
DSACK0
DS
CAS1
CS0
TS68EN360
(BOTTOM VIEW)
Note :
Pin P9 ”NC” is for guide purposes only.
Figure 2:
TS68EN360
5/72
2.2. 240-Lead Cerquad
IRQ1 240
BERR
GND
HALT
RESETS
Vcc
RMC
AVEC
GND
PERR
TDO 230
TDI
TMS
TCK
TRST
RESETH
BKPT
GND
IRQ6
IRQ4
Vcc 220
BGACK
BG
GND
Vcc
BR
NC1
IFETCH
OE
GND
BCLRO 210
NC2
Vcc
IPIPE1
GNDs2
AS
IPIPE0
PRTY0
PRTY1
Vcc
GND 200
PRTY2
PRTY3
GND
DSACK1
GND
DSACK0
Vcc
NC3
R/W
GND 190
DS
FREEZE
CAS0
GND
CAS1
Vcc
CAS2
CAS3
GNDs1 181
D061 D1
GND
D2
D3
D4
Vcc
D5
D6
GND70 D7
D8
D9
D10
D11
GND
D12
D13
D14
Vcc80 D15
D16
GND
D17
D18
D19
CLKO2
GNDclk
Vccclk
CLKO190 D20
D21
D22
GND
D23
D24
D25
Vcc
D26
D27100 D28
GND
D29
D30
D31
GND
Vcc
FC3
FC2
FC1110 GND
FC0
SIZ1
SIZ0
Vcc
A31
A30
GND
A29
A28120
CS0
180
CS1
CS2
CS3
Vcc
GND
CS4
CS5
CS6
CS7
IRQ7
170
TRIS
A0
A1
GND
A2
A3
Vcc
A4
A5
GND
160
A6
A7
Vcc
GND
A8
A9
GND
A10
A11
Vcc
150
A12
A13
GND
A14
A15
A16
A17
A18
GND
A19
140
A20
A21
Vcc
A22
A23
A24
GND
A25
A26
A27
130
NC4
GND
MODCK1
MODCK0
XTAL
EXTAL
GNDsyn
XFC
Vccsyn
121
IRQ5
1
IRQ3
IRQ2
PC0
PC1
PC2
GND
PC3
PC4
PC5
10
PC6
Vcc
PC7
PC8
PC9
PC10
GND
PC11
PB0
PB1
20
PB2
PB3
PB4
PB5
PB6
GND
PB7
PB8
PB9
PB10
30
Vcc
PB11
PB12
PB13
PB14
GND
PB15
PB16
PB17
PA0
40
GND
Vcc
PA1
PA2
PA3
PA4
GND
PA5
PA6
PA7
50
PA8
Vcc
PA9
PA10
PA11
PA12
GND
PA13
PA14
PA15
60
TS68EN360
(TOP VIEW)
PIN ONE INDICATOR
Figure 3:
TS68EN360
6/72
3. SIGNAL DESCRIPTION
3.1. Functional Signal Groups
QUICC
A31–A28/WE0–WE3
A27–A0
DATA BUSD31–D16
D15–D0
PRTY3/16BM
BUS CONTROL
SIZ0
SIZ1
R/W
AS
BUS ARBITRA TION
BR
BG
BCLRO/CONFIG1/RAS2DD
SYSTEM CONTROL
RESETH
RESETS
HALT
PERR
INTERRUPT CONTROL
AVEC/IACK5/AVECO
MEMORY CONTROLLER
CS6–CS0/RAS6–RAS0
CS/RAS7/IACK7
CAS3–CAS0/IACK6,3,2,1
TCK
TMS
TDI
TDO
TRST
CLOCK XTAL
EXTAL
XFC
MODCK1–MODCK0
CLKO2–CLKO1
ADDRESS BUS
RXD1/PA0
PORT A
TXD1/PA1
RXD2/PA2
TXD2/PA3
L1TXDB/RXD3/PA4
L1RXDB/TXD3/PA5
L1TXDA/RXD4/PA6
L1RXDA/TXD4/PA7
TIMERs/SCCs/SIs/CLOCKs/BRG
TIN1/L1RCLKA/BRGO1/CLK1/PA8
BRGCLK1/TOUT1/CLK2/PA9
TIN2/L1TCLKA/BRGO2/CLK3/PA10
TOUT2/CLK4/PA11
TIN3/BRGO3/CLK5/PA12
BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13
TIN4/BRGO4/CLK7/PA14
L1TCLKB/TOUT4/CLK8/PA15
PORT B (PIP)
RRJCT1/SPISEL/PB0
RSTRT2/SPICLK/PB1
RRJCT2/SPIMOSI(SPITXD)/PB2
BRGO4/SPIMISO(SPIRXD)/PB3
DREQ1/BRGO1/PB4
DACK1/BRGO2/PB5
DONE1/SMTXD1/PB6
DONE2/SMRXD1/PB7
DREQ2/SMSYN1/PB8
DACK2/SMSYN2/PB9
L1CLKOB/SMTXD2/PB10
L1CLKOA/SMRXD2/PB11
L1ST1/RTS1/PB12
L1ST2/RTS2/PB13
L1ST3/L1RQB/RTS3/PB14
L1ST4/L1RQA/RTS4/PB15
STRBO/BRGO3/PB16
STRBI/RSTRT1/PB17
PORT C (INTERRUPT PARALLEL I/O)
L1ST1/RTS1/PC0
L1ST2/RTS2/PC1
L1ST3/L1RQB/RTS3/PC2
L1ST4/L1RQA/RTS4/PC3
CTS1/PC4
TGATE1/CD1/PC5
CTS2/PC6
TGATE2/CD2/PC7
SDACK2/L1TSYNCB/CTS3/PC8
L1RSYNCB/CD3/PC9
SDACK1/L1TSYNCA/CTS4/PC10
L1RSYNCA/CD4/PC11
TS68360
240 PINS
TEST
FC2–FC0/
TM2–TM0
FC3/
TT0
PRTY1–PRTY2/
IOUT1–IOUT2
PRTY2/IOUT0/
RQOUT
DSACK0/
TBI
DSACK1/
TA
DS/
TT1
OE/AMUX
RMC/CONFIG0/
LOCK
BGACK/
BB
BERR/
TEA
IRQ1/
OUT0
/RQOUTIRQ1/
OUT0
/RQOUT
IRQ4/
OUT1
IRQ6/
OUT2
IRQ2,3,5,7
TRIS/
TS
BKPT/
BKPT0
/DSCLK
FREEZE/CONFIG2/
MBARE
IPIPE1/RAS1DD/
BCLRI
IPIPE0/
BADD2
/DSO
IFETCH/
BADD3
/DSI
Figure 4: QUICC Functional Signal Groups
TS68EN360
7/72
3.2. Signal Index
Table 1 : System Bus Signal Index (Normal Operation)
Group Signal Name Mnemonic Function
Address Address Bus A27-A0 Lower 27 bits of address bus. (I/O)
Address Bus/Byte
Write Enables A31-A28
WE3-WE0 Upper four bits of address bus (I/O), or byte write enable signals (O) for
accesses to external memory or peripherals.
Function Codes FC3-FC0 Identifies the processor state and the address space of the current bus cycle. (I/O)
Data Data Bus 31-16 D31-D16 Upper 16-bit data bus used to transfer byte or word data.
Used in 16-bit bus mode. (I/O)
Data Bus 15-0 D15-D0 Lower 16-bit data bus used to transfer 3-byte or long-word data (I/O).
Not used in 16-bit bus mode.
Parity Parity 2-0 PRTY2-PRTY0 Parity signals for byte writes/reads from/to external memory module. (I/O)
Parity 3/16BM PRTY3/16BM Parity signals for byte writes/reads from/to external memory module or
defines 16-bit bus mode. (I/O)
Parity Error PERR Indicates a parity error during a read cycle. (O)
Memory Controller Chip Select
Row Address Select 7
Interrupt Acknowledge 7
CS
RAS7
IACK7
Enables peripherals or DRAMs at programmed addresses (O) or interrupt
level 7 acknowledge line (O).
Chip Select 6-0
Row Address Select 6-0 CS6-CS0
RAS6-RAS0 Enables peripherals or DRAMs at programmed addresses. (O)
Column Address Select
3-0/Interrupt Acknowl-
edge 1,2,3,6
CAS3-CAS0
/
IACK6,3,2,1
DRAM column address select or interrupt level acknowledge lines. (O)
Bus Arbitration Bus Request BR Indicates that an external device requires bus mastership. (I)
Bus Grant BG Indicates that the current bus cycle is complete and the QUICC has relin-
quished the bus. (O)
Bus Grand Acknowledge BGACK Indicates that an external device has assumed bus mastership. (I)
Read-Modify-Write
Cycle
Initial Configuration 0
RMC
CONFIG0
Identifies the bus cycle as part of an indivisible read-modify-write operation
(I/O) or initial QUICC configuration select (I).
Bus Clear Out/Initial Con-
figuration 1/Row Address
Select 2 Double-Drive
BCLRO/CONFIG1
/
RAS2DD
Indicates that an internal device requires the external bus (Open-Drain O) or
initial QUICC configuration select (I) or row address select 2 double-drive out-
put (O).
Bus Control Data and Size
Acknowledge DSACK1-DSACK0 Provides asynchronous data transfer acknowledgement and dynamic bus
sizing (open-drain I/O but driven high before three-stated).
Address Strobe AS Indicates that a valid address is on the address bus. (I/O)
Data Strobe DS During a read cycle, DS indicates that an external device should place valid
data on the data bus. During a write cycle, DS indicates that valid data is on
the data bus (I/O).
Size SIZ1-SIZ0 Indicates the number of bytes remaining to be transferred for this cycle. (I/O)
Read/Write R/W Indicates the direction of data tranfer on the bus. (I/O)
Output Enable
Address Multiplex OE/AMUX Active during a read cycle indicates that an external device should place valid
data on the data bus (O) or provides a strobe for external address multiplexing
in DRAM accesses if internal multiplexing is not used (O).
Interrupt Control Interrupt Request
Level 7-1 IRQ7-IRQ1 Provides external interrupt requests to the CPU32+ at priority levels 7-1. (I)
Autovector/Interrupt
Acknowledge 5 AVEC/IACK5 Autovector request during an interrupt acknowledge cycle (open-drain I/O) or
interrupt level 5 acknowledge line (O).
TS68EN360
8/72
Table 1 : System Bus Signal Index (Normal Operation) (Continued)
Group Signal Name Mnemonic Function
System Control Soft Reset RESETS Soft system reset. (open-drain I/O)
Hard Reset RESETH Hard system reset. (open-drain I/O)
Halt HALT Suspends external bus activity. (open-drain I/O)
Bus Error BERR Indicates an erroneous bus operation is being attempted. (open-drain I/O)
Clock and Test System Clock Out 1 CLKO1 Internal system clock output 1. (O)
System Clock Out 2 CLKO2 Internal system clock output 2 - normally 2x CLKO1. (O)
Crystal Oscillator EXTAL, XTAL Connections for an external crystal to the internal oscillator circuit. EXT AL (I),
XTAL (O).
External Filter Capacitor XFC Connection pin for an external capacitor to filter the circuit of the PLL. (I)
Clock Mode Select 1-0 MODCK1-MODCK0 Selects the source of the internal system clock. (I) THESE PINS SHOULD
NOT BE SET TO 00
Instruction Fetch/
Development Serial Input IFETCH/DSI Indicates when the CPU32+ is performing an instruction word prefetch (O) or
input to the CPU32+ background debug mode (I).
Instruction Pipe 0/Deve -
lopment Serial Output IPIPE0/DSO Used to track movement of words through the instruction pipeline (O) or out-
put from the CPU32+ background debug mode (O).
Instruction Pipe 1/
Row Address Select 1
Double-Drive
IPIPE1/RAS1DD Used to track movement of words through the instruction pipeline (O), or a row
address select 1 ”double-drive” output (O).
Clock and Test
(Cont’d) Breakpoint/Develop-
ment Serial Clock BKPT/DSCLK Signals a hardware breakpoint to the QUICC (open-drain I/O), or clock signal
for CPU32+ background debug mode (I).
Freeze/
Initial Configuration 2 FREEZE/CONFIG2 Indicates that the CPU32+ has acknowledged a breakpoint (O), or initial
QUICC configuration select (I).
Three-State TRIS Used to three-state all pins if QUICC is configured as a master .
Always Sampled except during system reset. (I)
Test Clock TCK Provides a clock for Scan test logic. (I)
Test Mode Select TMS Controls test mode operations. (I)
Test Data In TDI Serial test instructions and test data signal. (I)
Test Data Out TDO Serial test instructions and test data signal. (O)
Test Reset TRST Provides an asynchronous reset to the test controller. (I)
Power Clock Synthesizer Power VCCSYN Power supply to the PLL of the clock synthesizer .
ClockSynthesizer
Ground GNDSYN Ground supply to the PLL of the clock synthesizer.
Clock Out Power VCCCLK Power supply to clock out pins.
Clock Out Ground GNDCLK Ground supply to clock out pins.
Special Ground 1 GNDS1 Special ground for fast AC timing on certain system bus signals.
Special Ground 2 GNDS2 Special ground for fast AC timing on certain system bus signals.
System Power Supply
and Return VCC, GND Power supply and return to the QUICC.
-- No Connect NC4-NC1 Four no-connect pins.
Note : I denotes input, O denotes output and I/O is input/output.
TS68EN360
9/72
Table 2 : Peripherals Signal Index
Group Signal Name Mnemonic Function
SCC Receive Data RXD4-RXD1 Serial receive data input to the SCCs. (I)
T ransmit Data TXD4-TXD1 Serial transmit data output from the SCCs. (O)
Request to Send RTS4-R TS1 Request to send outputs indicate that the SCC is ready to transmit data. (O)
Clear to Send CTS4-CTS1 Clear to send inputs indicate to the SCC that data transmission may begin. (I)
Carrier Detect CD4-CD1 Carrier detect inputs indicate that the SCC should begin reception of data. (I)
Receive Start RSTRT1 This output from SCC1 identifies the start of a receive frame. Can be used by
an Ethernet CAM to perform address matching. (O)
Receive Reject RRJCT1 This input to SCC1 allows a CAM to reject the current Ethernet frame after it
determines the frame address did not match. (I)
Clocks CLK8-CLK1 Input clocks to the SCCs, SCMs, SI, and the baud rate generators. (I)
IDMA DMA Request DREQ2-DREQ1 A request (input) to an IDMA channel to start an IDMA transfer. (I)
DMA Acknowledge DACK2-DACK1 An acknowledgement (output) by the IDMA that an IDMA transfer is
in progress. (O)
DMA Done DONE2-DONE1 A bidirectional signal that indicates the last IDMA transfer in a block of data. (I/O)
TIMER T imer Gate TGATE2-TGATE1 An input to a timer that enables/disables the counting function. (I)
T imer Input TIN4-TIN1 T ime reference input to the timer that allows it to function as a counter. (I)
T imer Output T OUT4 -T OUT1 Output waveform (pulse or toggle) from the timer as a result of a reference
value being reached. (O)
SPI SPI Master In Slave Out SPIMISO Serial data input to the SPI master (I); serial data output from an SPI slave (O).
SPI Master Out Slave In SPIMOSI Serial data output from the SPI master (O); serial data input to an SPI slave (I).
SPI Clock SPICLK Output clock from the SPI master (O); input clock to the SPI slave (I).
SPI Select SPISEL SPI slave select input. (I)
SMC SMC Receive Data SMRXD2-SMRXD1 Serial data input to the SMCs. (I)
SMC T ransmit Data SMTXD2-SMTXD1 Serial data output from the SMCs. (O)
SMC Sync SMSYN2-SMSYN1 SMC synchronization signal. (I)
SI SI Receive Data L1RXDA, L1RXDB Sérial input to the time division multiplexed (TDM) channel A or channel B.
SI T ransmit Data L1TXDA, L1TXDB Serial output from the TDM channel A or channel B.
SI Receive Clock L1RCLKA, L1RCLKB Input receive clock to TDM channel A or channel B.
SI T ransmit Clock L1TCLKA, L1TCLKB Input transmit clock to TDM channel A or channel B.
SI Transmit Sync Signals L1TSYNCA,L1TSYNCB Input transmit data sync signal to TDM channel A or channel B.
SI Receive Sync Signals L1RSYNCA,L1RSYNCB Input receive data sync signal to TDM channel A or channel B.
IDL Interface Request L1RQA, L1RQB IDL interface request to transmit on the D channel. Output from the SI.
SI Output Clock L1CLKOA, L1CLKOB Output serial data rate clock. Can output a data rate clock when the input
clock is 2x the data rate.
SI Data Strobes L1ST4-L1ST1 Serial data strobe outputs can be used to gate clocks to external devices that
do not have a built-in time slot assigner (TSA).
BRG Baud Rate Generator
Out 4-1 BRGO4-BRGO1 Baud rate generator output clock allows baud rate generator to be used exter-
nally.
BRG Input Clock CLK2, CLK6 Baud rate generator input clock from which BRG will derive the baud rates.
PIP Port B 15-0 PB15-BP0 PIP Data I/O Pins.
Strobe Out STRBO This input causes the PIP output data to be placed on the PIP data pins.
Strobe In STRBI This input causes data on the PIP data pins to be latched by the PIP as input
data.
SDMA SDMA Acknowledge 2-1 SDACK2-SDACK1 SDMA output signals used in RISC receiver to mark fields in the Ethernet
receive frame.
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B.DETAILED SPECIFICATIONS
1. SCOPE
This drawing describes the specific requirements for the microcontroller TS68EN360 - 25 MHz and 33 MHz in compliance with
MIL-STD-883 class B or TCS standard screening.
2. APPLICABLE DOCUMENTS
MIL-STD-883
1 - MIL-STD-883 : test methods and procedures for electronics.
2 - MIL-PRF-38535: general specifications for microcircuits.
3 - DESC 5962–SMD–97607
3. REQUIREMENTS
3.1. General
This microcircuits are in accordance with the applicable document and as specified herein.
3.2. Design and Construction
3.2.1. Terminal connections
Depending on the package, the terminal connections shall be is shown in Figures 2 and 3 (§ A).
3.2.2. Lead material and finish
Lead material and finish shall be as specified in MIL-STD-883 (see enclosed § 10).
3.2.3. Package
The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to case outlines of MIL-STD-1835 or as
follow :
- CMGA 10-241-PAK pin grid array, but see § 9.1
- CERQUAD
The precise case outlines are described at the end of the specification (§ 9) and into MIL-STD-1835.
3.3. Electrical Characteristics
3.3.1. Absolute maximum ratings
Table 3 : Absolute maximum ratings
Rating Symbol Value Unit This device contains protective circuitry against damage due
to high static voltages or electrical fields
;
however it is
Supply Voltage (1, 2) Vcc -0.3 to +6.5 V
to
high
static
voltages
or
electrical
fields
however
,
it
is
advised that normal precautions be taken to avoid application
of any voltages higher than maximum
-
rated voltages to this
Input Voltage (1, 2) Vin -0.3 to +6.5 V
of
any
voltages
higher
than
maximum-rated
voltages
to
this
high-impedance circuit. Reliability of operation is enhanced
if unused in
p
uts are tied to an a
pp
ro
p
riate logic voltage level
Storage Temperature Range Tstg -55 to +150 C
if
unused
in uts
are
tied
to
an
a ro riate
logic
voltage
level
(e.g., either GND or VDD).
Notes :
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device
reliability. Device modules may not operate normally while being exposed to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid
exposure to voltages higher than maximum-rated voltages.
3. The supply voltage Vcc must start and restart from 0.0V ; otherwise, the 360 will not come out of reset properly.
TS68EN360
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3.3.2. Recommended conditions of use
Table 4 : Recommended conditions of use
Unless otherwise stated, all voltages are referenced to the reference terminal.
Symbol Parameter Min. Typ. Max. Unit
VCC Supply voltage range +4.75 +5.25 V
VIL Logic low level input voltage range GND +0.8 V
VIH Logic high level input voltage range +2.0 Vcc V
Tcase Operating temperature -55 +125 C
VOH High level output voltage +2.4 V
fsys System frequency (For 25 MHz version) 25 MHz
(For 33 MHz version) 33 MHz
3.4. Thermal Characteristics
Symbol Parameter Value Unit
JC Thermal Resistance - Junction to Case 240-Pin Cerquad 2C/W
241-Pin PGA 7
JA Thermal Resistance - Junction to Ambient 240-Pin Cerquad 27.4 C/W
241-Pin PGA 22.8
TJ = TA + (PD JA)
PD = (VDD IDD) + PI/O
Where PI/O is the power dissipation on pins.
3.5. Power Considerations
The average chip-junction temperature, TJ, in C can be obtained from :
TA = Ambient Temperature, C
ΘJA = Package Thermal Resistance, Junction-to-Ambient, C/W
PD = P
INT + PI/O
PINT = ICC x VCC, Watts-Chip Internal Power
PI/O = Power Dissipation on Input and Output Pins-User Determined
(1) where :
For most applications, PI/O < 0.3* PINT and can be neglected.
An approximate relationship between PD and TJ (if PI/O is neglected) is :
Solving Equations (1) and (2) for K gives :
TJ = TA (PD DΘJA)(1)
PD = K ÷ (TJ + 273C) (2)
K = PD D (TA + 273C) + ΘJA DPD2(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at thermal equilibrium) for a
known T A. Using this value of K, the values of PD and TJ can be obtained by solving Equations (1) and (2) iteratively for any value of TA.
3.6. Mechanical and Environment
The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883 for class B devices or for TCS standard
screening.
TS68EN360
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3.7. Marking
The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and
permanently marked with the following information as minimum :
- Thomson logo,
- Manufacturer’s part number,
- Class B identification,
- Date-code of inspection lot,
- ESD identifier if available,
- Country of manufacturing.
4. QUALITY CONFORMANCE INSPECTION
DESC / MIL-STD-883
Is in accordance with MIL-M-38535 and method 5005 of MIL-STD-883. Group A and B inspections are performed on each production lot.
Group C and D inspections are performed on a periodical basis.
5. ELECTRICAL CHARACTERISTICS
5.1. General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given
below :
- Static electrical characteristics for the electrical variants,
- Dynamic electrical characteristics for TS68EN360 (25 MHz, 33 Mhz).
For static characteristics, test methods refer to IEC 748–2 method number, where existing.
For dynamic characteristics, test methods refer to clause 5.2 of this specification.
TS68EN360
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5.2. Static Characteristics
GND = 0 Vdc, TC = –55 to +125 C. The electrical specifications in this document are preliminary. (See numbered notes)
Characteristic Symbol Min. Max. Unit
Input High Voltage (except EXTAL) VIH 2.0 Vcc V
Input Low Voltage (5 V Part) VIL GND 0.8 V
Input Low Voltage (Part Only; PA8–15, PB1, PC5, PC7, TCK) VIL GND 0.5 V
Input Low Voltage (Part Only; All Other Pins) VIL GND 0.8 V
EXTAL Input High Voltage VIHC 0.8*(Vcc) Vcc +0.3 V
Undershoot – – – 0.8 V
Input Leakage Current (All Input Only Pins except for TMS, TDI and TRST) Vin = 0/5V Iin –2.5 2.5 mA
Hi–Z (Off–State) Leakage Current (All Noncrystal Outputs and I/O Pins except TMS,TDI and
TRST) Vin = 0/5 V IOZ –2.5 –2.5 mA
Signal Low Input Current VIL = 0.8 V (TMS, TDI and TRST Pins Only) IL–0.5 0.5 mA
Signal High Input Current VIH = 2.0 V (TMS, TDI and TRST Pins Only) IH–0.5 0.5 mA
Output High Voltage
IOH = –0.8 mA, Vcc = 4.75 V VOH 2.4 – V
AII Noncrystal Outputs Except Open Drain Pins
Output Low Voltage
IOL = 2.0 mA, CLKO1–2, FREEZE, IPIPE0–1, IFETCH, BKPTO 0.5
IOL = 3.2 mA, A31–A0, D31–D0, FC3–0, SIZ0–1, PA0, 2, 4, 6, 8–15, PB0–5, PB8–17,
PC0–11, TDO, PERR, PRTY0–3, IOUT0–2, AVECO, AS, CAS3–0, BLCRO, RAS0–7 VOL – 0.5 V
IOL = 5.3 mA, DSACK0–1, R/W, DS, OE, RMC, BG, BGACK, BERR 0.5
IOL = 7 mA, TXD1–4 0.5
IOL = 8.9 mA, PB6, PB7, HALT, RESET, BR (Output) 0.5
Input Capacitance
AII I/O Pins Cin – 20 pF
Load Capacitance (except CLKO1–2) CL– 100 pF
Load Capacitance (CLKO1–2) CLc 50 pF
Power Vcc 4.75 5.25 V
TS68EN360
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5.3. Dynamic Characteristics
The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified
relative to an appropriate edge of the clock and possibly to one or more other signals.
The measurement of the AC specifications is defined by the waveforms shown in Figure 5. To test the parameters guaranteed by TCS
inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as
appropriate, and are measured as shown. Inputs are specified with minimum setup and hold times and are measured as shown. Final ly ,
the measurement for signal–to–signal specifications are shown.
Note that the testing levels used to verify conformance to the AC specifications do not affect the guaranteed DC operation of the device as
specified in the DC electrical characteristics.
Figure 5: Drive Levels and test Points for AC Specifications
Note :
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
Legend :
a) Maximum output delay specification.
b) Minimum output hold time.
c) Minimum input setup time specification.
d) Minimum input hold time specification.
e) Signal valid to signal valid specification (maximum or minimum).
f) Signal valid to signal invalid specification (maximum or minimum).
TS68EN360
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5.4. AC Power Dissipation
TYPICAL CURRENT DRAIN
Mode of operation Symbol System Clock
Frequency BRGCLK Clock
Frequency SyncCLK Clock
Frequency Typ Unit
Normal mode (Rev A1 and Rev B2) IDD 25 MHz 25 MHz 25 mHz 250 ma
Normal Mode (Rev C3 and Newer) IDD 25 MHz 25 MHz 25 MHz 237 ma
Normal Mode IDD 33 MHz 33 MHz 33MHz 327 ma
Low Power Mode IDDSB Divide by 2
12.5 MHz Divide by 16
1.56 MHz Divide by 2
12.5 MHz 150 ma
Low Power Mode IDDSB Divide by 4
6.25 MHz Divide by 16
1.56 MHz Divide by 4
6.25 MHz 85 ma
Low Power Mode IDDSB Divide by 16
1.56 MHz Divide by 16
1.56 MHz Divide by 4
6.25 MHz 35 ma
Low Power Mode IDDSB Divide by 256
97.6 KHz Divide by 16
1.56 MHz Divide by 4
6.25 MHz 20 ma
Low Power Mode IDDSB Divide by 256
97.6 KHz Divide by 64
390 KHz Divide by 64
390 KHz 13 ma
Low Power Stop
VCO Off5IDDSP 0.5 ma
PLL Supply Current
PLL Disabled
PLL Enabled
IDDPD
IDDPE TBD
TBD
Notes :
1. Rev A mask is C63T
2. Rev B masks are C69T, and F35G
3. Current Rev C masks are E63C, E68C and F15W
4. EXTAL frequency is 32 KHz
All measurements was taken with only CLKO1 enabled, Vcc = 5.0 V, VIL = 0 V and VIH = Vcc
MAXIMUM POWER DISSIPATION
System Frequency Vcc Max PDUnit Mask
25 MHz 5.25 V 1.80 WREV A(1) and REV B(2)
25 MHz 5.25 V 1.45 WREV C(3) and Newer
25 MHz 3.6 V 0.65 WREV C(3) and Newer
33 MHz 5.25 V 2.00 WREV C(3) and Newer
Notes :
1. Rev A mask is C63T
2. Rev B masks are C69T, and F35G
3. Current Rev C masks are E63C, E68C and F15W
TS68EN360
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5.5. AC Electrical Specifications Control Timing
GND = 0 Vdc, TC = –55 to +125C. The electrical specifications in this document are preliminary. (See Figure 6 )
Num. Characteristic Symbol 25 MHz 33.34 MHz Unit
Min Max Min Max
System Frequency fsys dc (1) 25.00 33.34 MHz
Crystal Frequency fXTAL 25 6000 25 6000 KHz
On–Chip VCO System Frequency fsys 20 50 20 67 MHz
Start–up T ime
With external clock (oscillator disabled) or after changing the
multiplication factor MF
tpll 2500 clks
CLKO1–2 stability DCLK TBD TBD %
1CLKO1 Period tcyc 40 – 30 – ns
1A EXTAL Duty Cycle, MF tdcyc 40 60 40 60 %
1C External Clock Input Period tEXTcyc 40 – 30 – ns
2, 3 CLKO1 Pulse Width (Measured at 1.5 V) tCW1 19 – 14 – ns
2A, 3A CLKO2 Pulse Width (Measured at 1.5 V) tCW2 9.5 – 7 – ns
4, 5 CLKO1 Rise and Fall T imes (Full drive) tCrf1 – 2 – 2 ns
4A, 5A CLKO2 Rise and Fall Times (Full drive) tCrf2 – 2 – 1.6 ns
5B EXTAL to CLKO1 Skew–PLL enabled (MF< 5) tEXTP1 a a ns
5C EXTAL to CLKO2 Skew–PLL enabled (MF< 5) tEXTP2 a a ns
5D CLKO1 to CLKO2 Skew tCSKW a a ns
Note 1 : Note that the minimum VCO frequency and the PLL default values put some restrictions on the minimum system frequency.
The following calculation should be used to determine the actual value for specifications 5B, 5C and 5D.
5B : 25 MHz "(0.9ns + 0.25 x (rise time)) (1.4ns @ rise = 2ns; 1.9ns @ rise = 4ns)
33 MHz "(0.5ns + 0.25 x (rise time)) (1ns @ rise = 2ns; 1.5ns @ rise = 4ns)
5C 25/33 MHz "(2ns + 0.25 x (rise time)) (2.5ns @ rise = 2ns; 3ns @ rise = 4ns)
5D : 25 MHz "(3ns + 0.5 x (rise time)) (4ns @ rise = 2ns; 5ns @ rise = 4ns)
33 MHz "(2.5ns + 0.5 x (rise time)) (3.5ns @ rise = 2ns; 4.5ns @ rise = 4ns)
Figure 6: Clock Timing
TS68EN360
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5.6. External Capacitor For PLL
GND = 0 Vdc, TC = –55 to +125C. The electrical specifications in this document are preliminary
Characteristic Symbol Min Max Unit
PLL external capacitor (XFC to VCCSYN)
MF<5 (recommended value MF x 400 pF)
MF>4 (recommended value MF x 540 pF)
cXFC MF x 340
MF x 380 MF x 480
MF x 970 pF
pF
Note : MF – multiplication factor .
Examples:
1.
MODCK1 pin = 0, MF = 1 å CXFC = 400 pF
2.
MODCK1 pin = 1, crystal is 32.768 KHz (or 4.192 MHz), initial MF = 401, initial frequency = 13.14 MHz, later on MF is changed to
762 to support a frequency of 25 MHz.
Minimum CXFC is :762 x 380 = 289 nF, Maximum CXFC is :401 x 970 = 390 nF.
The recommended CXFC for 25 MHz is: 762 x 540 = 414 nF.
289 nF < CXFC < 390 nF and closer to 414 nF. The proper available value for CXFC is 390 nF.
3.
MODCK1 pin = 1, crystal is 32.768 KHz (or 4.192 MHz), initial MF = 401, initial frequency = 13.14 MHz, later on MF is changed to
1017 to support a frequency of 33.34 MHz.
Minimum CXFC is :1017 x 380 = 386 nF, Maximum CXFC is :401 x 970 = 390 nF å386 nF < CXFC < 390 nF.
The proper available value for CXFC is 390 nF.
4.
In order to get higher range, higher crystal frequency can be used (i.e. 50 KHz), in this case:
Minimum CXFC is :667 x 380 = 253 nF, Maximum CXFC is :401 x 970 = 390 nF å253 nF < CXFC < 390 nF.
TS68EN360
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5.7. Bus Operation AC Timing Specifications
GND = 0 Vdc, TC = –55 to +125C. The electrical specifications in this document are preliminary (see Figure 7 to Figure 23)
Num. Characteristic Symbol 25 MHz 33.34 MHz Unit
Min Max Min Max
6CLKO1 High to Address, FC, SIZ, RMC Valid tCHAV 0 15 0 12 ns
6A CLKO1 High to Adrress Valid (GAMX=1) tCHAV 0 20 0 15 ns
7CLKO1 High to Address, Data, FC, SIZ, RMC High Impedance tCHAZx 0 40 0 30 ns
8CLKO1 High to Address, Data, FC, SIZ, RMC Invalid tCHAZn –2 – –2 – ns
9CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE, IACKx
Asserted tCLSA 3 20 3 15 ns
9 (10) CLKO1 Low to CSx/RASx Asserted tCLSA 4 16 4 12 ns
9B (11) CLKO1 High to CSx/RASx Asserted tCHCA 4 16 4 12 ns
9A (2,10) AS to DS or CSx/RASx or OE Asserted (Read) tSTSA –6 6 –5.625 5.625 ns
9C (2,11) AS to CSx/RASx Asserted tSTCA 14 26 9 21 ns
11 (10) Address, FC, SIZ, RMC, valid to AS, CSx/RASx, OE, WE, (and
DS Read) Asserted tAVSA 10 – 8 – ns
11A (11) Address, FC, SIZ, RMC, Valid to CSx/RASx Asserted tAVCA 30 – 22.5 – ns
12 CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE, IACKx Negated tCLSN 3 20 3 15 ns
12 (16) CLKO1 Low to CSx/RASx Negated tCLSN 4 16 4 12 ns
12A (13,16) CLKO1 High to CSx/RASx Negated tCHCN 4 16 4 12 ns
12B CS negate to WE negate (CSNTQ=1) tCSTW 15 – 12 – ns
13 (12) AS, DS, CSx, OE, WE, IACKx Negated to Address, FC, SIZ
Invalid (Address Hold) tSNAI 10 – 7.5 – ns
13A (13) CSx Negated to Address, FC, SIZ, Invalid (Address Hold) tCNAI 30 – 22.5 – ns
1410, (12) AS, CSx, OE, WE (and DS Read) Width Asserted tSWA 75 – 56.25 – ns
14C (11,13) CSx Width Asserted tCWA 35 – 26.25 – ns
14A DS Width Asserted ( Write) tSWAW 35 – 26.25 – ns
14B AS, CSx, OE, WE, IACKx, (and DS Read) Width Asserted (Fast
Termination Cycle) tSWDW 35 – 26.25 – ns
14D (13) CSx Width Asserted (Fast Termination Cycle) tCWDW 15 – 10 – ns
153, (10,12) AS, DS, CSx, OE, WE Width Negated tSN 35 – 26.25 – ns
16 CLKO1 High to AS, DS, R/W High Impedance tCHSZ – 40 – 30 ns
17 (12) AS, DS, CSx, WE Negated to R/W High tSNRN 10 – 7.5 – ns
17A (13) CSx Negated to R/W High tCNRN 30 – 22.5 – ns
18 CLKO1 High to R/W High tCHRH 0 20 0 15 ns
20 CLKO1 High to R/W Low tCHRL 3 20 3 15 ns
21 (10) R/W High to AS, CSx, OE Asserted tRAAA 10 – 7.5 – ns
21A (11) R/W High to CSx Asserted tRACA 30 – – ns
22 R/W Low to DS Asserted (Write) tRASA 47 – 36 – ns
23 CLKO1 High to Data–Out. tCHDO – 23 – 18 ns
23A CLKO1 High to Parity Valid tCHPV – 25 – 20 ns
23B Parity Valid to CAS Low tPVCL 3 – 3 – ns
24 (12) Data–Out, Parity–Out Valid to Negating Edge of AS, CSx, WE,
(Fast Termination W rite) tDVASN 10 – 7.5 – ns
25 (12) DS, CSX, WE Negated to Data–Out, Parity–Out Invalid (Data–
Out, Parity–Out Hold) tSNDOI 10 – 7.5 – ns
25A (13) CSx Negated to Data–Out, Parity–Out Invalid (Data–Out, Parity–
Out Hold) tCNDOI 35 – 25 – ns
TS68EN360
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Num. Unit33.34 MHz25 MHzSymbolCharacteristic
MaxMinMaxMin
26 Data–Out, Parity–Out Valid to DS Asserted (Write) tDVSA 10 – 7.5 – ns
27 (15) Data–In, Parity–In to CLKO1 Low (Data–Setup) tDICL 1 – 1 – ns
27B (14) Data–In, Parity–In Valid to CLKO1 Low (Data–Setup) tDICL 20 – 15 – ns
27A Late BERR, HALT, BKPT Asserted to CLKO1 Low (Setup Time) tBELCL 10 – 7.5 – ns
28 (18) AS, DS Negated to DSACKx, BERR, HALT Negated tSNDN 0 50 0 37.5 ns
29 (4) DS, CSx, OE, Negated to Data–In Parity–In Invalid (Data–In,
Parity–In Hold) tSNDI 0 – 0 – ns
29A (4) DS, CSx, OE Negated to Data–In High Impedance tSHDI – 40 – 30 ns
30 (4) CLKO1 Low to Data–In, Parity–In Invalid (Fast T ermination Hold) tCLDI 10 – 7.5 – ns
30A (4) CLKO1 Low to Data–In High Impedance tCLDH – 60 – 45 ns
31 (5,15) DSACKx Asserted to Data–in, Parity–In Valid tDADI – 32 – 24 ns
31A DSACKx Asserted to DSACKx Valid (Skew) tDADV – 10 – 7.5 ns
31B (5,14) DSACKx Asserted to Data–in, Parity–In Valid tDADI – 35 – 26 ns
32 HALT an RESET Input Transition Time tHRrf – 140 – ns
33 CLKO1 High to BG Asserted tCLBA – 20 – 15 ns
34 CLKO1 High to BG Negated tCLBN – 20 22.5 15 ns
35 (6) BR Asserted to BG Asserted (RMC Not Asserted) tBRAGA 1 – 1 – CLKO1
37 BGACK Asserted to BG Negated tGAGN 1 2.5 1 2.5 CLKO1
39 BG Width Negated tGH 2 – 2 – CLKO1
39A BG Width Asserted tGA 1 – 1 – CLKO1
46 R/W Width Asserted (Write or Read) tRWA 100 – 75 – ns
46A R/W Width Asserted (Fast Termination Write or Read) tRWAS 75 – 56 – ns
47A Asynchronous Input Setup T ime tAIST 5 – 4 – ns
47B Asynchronous Input Hold T ime tAIHT 10 – 7.5 – ns
48 (5,7) DSACKx Asserted to BERR, HALT Asserted tDABA – 30 – 22.5 ns
53 Data–Out, Parity–Out Hold from CLKO1 High tDOCH 0 – 0 – ns
54 CLKO1 High to Dat–Out, Parity–Out High Impedance tCHDH – 20 – 15 ns
55 R/W Asserted to Data Bus Impedance Change tRADC 25 – 19 – ns
56 RESET Pulse Width (Reset Instruction) tHRPW 512 – 512 – CLKO1
56A RESET Pulse Width (Input from External Device) tRPWI 20 – 20 – CLKO1
57 BERR Negated to HALT Negated (Return) tBNHN 0 – 0 – ns
58 CLKO1 High to BERR, RESETS, RESETH Driven Low tCHBRL – 30 26 ns
58A CLKO1 Low RESETS Driven Low (upon Reset Instruction
execution only) tCLRL – 30 26 ns
58B CLKO1 High to BERR, RESETS, RESETH tri–stated tCLRL – 20 – 15 ns
60 CLKO1 High to BCLRO Asserted tCHBCA – 20 – 15 ns
61 CLKO1 High to BCLRO Negated tCHBCN – 20 – 15 ns
62 (9) BR Synchronous Setup Time tBRSU 5 – 3.75 – ns
63 (9) BR Synchronous Hold Time tBRH 10 – 7.5 – ns
64 (9) BGACK Synchronous Setup Time tBGSU 5 – 3.75 – ns
65 (9) BGACK Synchronous Hold Time tBGH 10 – 7.5 – ns
66 BR Low to CLKO1 Rising Edge (040 comp. mode) tBRCH 5 – 5 – ns
70 CLKO1 Low to Data Bus Driven (Show Cycle) tSCLDD 0 30 0 22.5 ns
TS68EN360
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Num. Unit33.34 MHz25 MHzSymbolCharacteristic
MaxMinMaxMin
71 Data Setup Time to CLKO1 Low (Show Cycle) tSCLDS 10 – 7.5 – ns
72 Data Hold from CLKO1 Low (Show Cycle) tSCLDH 6 – 3.75 – ns
73 BKPT Input Setup T ime tBKST 10 – 7.5 – ns
74 BKPT Input Hold T ime tBKHT 6 – 3.75 – ns
75 RESETH Low to Config2–0, MOD1–0, B16M Valid tMST – 500 – 500 CLKO1
76 Config2–0 tMSH 0 – 0 – ns
77 MOD1–0 Hold T ime, B16M Hold Time tMSH 10 – 10 – CLKO1
80 DSI Input Setup T ime tDSISU 10 – 7.5 – ns
81 DSI Input Hold T ime tDSIH 6 – 3.75 – ns
82 DSCLC Setup T ime tDSCSU 10 – 7.5 – ns
83 DSCLC Hold T ime tDSCH 6 – 3.75 – ns
84 DSO Delay T ime tDSOD – tcyc+20 – tcyc+20 ns
85 DSCLK Cycle tDSCCYC 2 – 2 – CLKO1
86 CLKO1 High to Freeze Asserted tFRZA 0 35 0 26.25 ns
87 CLKO1 High to Freeze Negated tFRZN 0 35 0 26.25 ns
88 CLKO1 High to IFETCH High Impedance tIFZ 0 35 0 26.25 ns
89 CLKO1 High to IFETCH Valid tIF 0 35 0 26.25 ns
90 CLKO1 High to PERR Asserted tCHPA 0 20 0 15 ns
91 CLKO1 High to PERR Negated tCHPN 0 20 0 15 ns
92 Vcc Ramp–Up T ime At Power–On Reset tRMIN 5 – 5 – ns
Notes :
1. All AC timing is shown with respect to 0.8 V and 2.0 V levels unless otherwise noted.
2. This number can be reduced to 5ns if strobes have aqual loads.
3. If multiple chip selects are used, the CSx width negated (#15) applies to the time from the negation of a heavily loaded chip select to the assertion of
a lightly loaded chip select.
4. These hold times are specified with respect to DS or CSx on asynchronous reads and with respect to CLKO1 on fast termination reads. The user is
free to use either hold time for fast termination reads.
5. If the asynchronous setup (#17) requirements are satisfied, the DSACKx low to data setup time (#31) and DSACKx low to BERR low setup time (#48)
can be ignored. The data must only satisfy the data–in to CLKO1 low setup time (#27) for the following clock cycle : BERR must only satisty the late
BERR low to CLKO1 low setup time (#27A) for the following clock cycle.
6. To ensure coherency during every operand transfer , BG will not be asserted in response to BR until after cycles of the current operand transfer are
complete and RMC is negated.
7. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous setup time (#47).
8. During interrupt acknowledge cycles, the processor may insert up to two wait states between states S0 and S1.
9. These specs are for Synchronous Arbitration only. ASTM=1.
10.These CSx specs are for TRLX=0.
11.These CSx specs are for TRLX=1.
12.These CSx specs are for CSNTQ=0.
13.These CSx specs are for CSNTQ=1; or RASx specs for DRAM accesses.
14.These specs are read cycles with parity check and PBEE=1.
15.These specs are read cycles with parity check and PBEE=0, PAREN=1.
16.These RASx specs are for page miss case.
17.These specifications only apply to CSx/RASx pins.
18.This specification applies to non fast termination cycles. In fast termination cycles, the BERR signal must be negated by 20ns after negation of AS, DS.
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Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 7: Read Cycle
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Figure 8: Fast Termination Read Cycle (Parity Check PAREN = 1, PBEE = 0)
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Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 9: Read Cycle (With Parity Check, PBEE = 1)
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Figure 10: SRAM: read Cycle (TRLX = 1)
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Note : *Up to two wait states may be inserted by the processor between states S0 and S1
Figure 11: CPU32+ IACK Cycle
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Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 12: Write Cycle
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Figure 13: Fast Termination Write Cycle
Figure 14: SRAM: Fast Termination Write Cycle (CSNTQ = 1)
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Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 15: SRAM: Write Cycle
(TRLX = 1, CSNTQ = 1, TCYC = 0)
Figure 16: ASYNC Bus Arbitration – IDLE Bus Case
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Figure 17: ASYNC Bus Arbitration – Active Bus Case
Figure 18: SYNC Bus Arbitration – IDLE Bus Case
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Figure 19: SYNC Bus Arbitration – Active Bus Case
Figure 20: Configuration And Clock Mode Select Timing
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Figure 21: Show Cycle
Figure 22: Background Debug Mode FREEZE Timing
Figure 23: Background Debug Mode Serial Port Timing
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5.8. Bus Operation - DRAM Accesses AC Timing Specifications
GND = 0 Vdc, TC = –55 to +125C. The electrical specifications in this document are preliminaryà (See Figure 24 to Figure 28)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
100 RASx Asserted to Row Address Invalid 15 11.25 ns
101 RASx Asserted to column Address Valid 20 15 ns
102 RASx Width Asserted 75 56.25 ns
103A RASx width Negated (Back to back Cycle) Non page modeWBTQ = 0 75 56.25 ns
103B RASx width Negated (Back to back Cycle) Page mode WBTQ = 0 55 41.25 ns
103C RASx width Negated (Back to back Cycle) Non page mode WBTQ = 1 115 86.25 ns
103D RASx width Negated (Back to back Cycle) Page mode WBTQ = 1 95 69.23 ns
104 RASx Asserted to CASx Asserted 35 26.25 ns
105 CLKO1 Low to CASx Asserted 3 13 2 10 ns
105A CLKO1 High to CASx Asserted (Refresh Cycle) 3 13 2 10 ns
106 CLKO1 High to CASx Negated 3 13 2 10 ns
107 Column Address Valid to CASx Asserted 15 11.25 ns
108 CASx Asserted to Column Address Negated 40 30 ns
109 CASx Asserted to RASx Negated 35 27 ns
110 CASx Width Asserted 50 37.5 ns
1111CASx Width Negated (Back to Back Cycles) 95 71.25 ns
111A CASx Width Negated (Page Mode) 20 15 ns
113 WE Low to CASx Asserted 35 27 ns
114 CASx Asserted to WE Negated 35 27 ns
115 R/W Low to CASx Asserted (Write) 52.5 40 ns
116 CASx Asserted to R/W High (Write) 55 41.25 ns
117 Data–Out, Parity–Out Valid to CASx Asserted 10 7.5 ns
119 CLKO1 High to AMUX Negated 3 16 2 12 ns
120 CLKO1 High to AMUX Asserted 3 16 2 12 ns
121 AMUX High to RASx Asserted 15 11.25 ns
122 RASx Asserted to AMUX Low 15 11.25 ns
123 AMUX Low to CASx Asserted 15 11.25 ns
124 CASx Asserted to AMUX High 55 41.25 ns
125 RAS/CASx Negated to R/W change 0 0 ns
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PARITY3–PARITY0
Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 24: DRAM: Normal Read Cycle
(Internal Mux, TRLX = 0)
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Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 25: DRAM: Normal Write Cycle
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Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 26: DRAM: Refresh Cycle
Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 27: DRAM: Page Mode – Page–Hit
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Note : All timing is shown with respect to 0.8V and 2.0V levels.
Figure 28: DRAM: Page Mode – Page–Miss
5.9. 040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C. The electrical specifications in this document are preliminary (See Figure 29)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
231 Address, T ransfer Attributes High Impedance to Clock High 7 – 6 – ns
2321Clock High to BG Low – 20 – 15 ns
233 Clock High to BG High 4 20 4 15 ns
234 BB High to Clock High (040 output) 7 – 6 – ns
235 BB High Impedance to Clock High (040 output) 0 – 0 – ns
236 Clock High to BB Low (360 Output) – 20 – 15 ns
237 Clock High to BB High (360 Output) – 20 – 15 ns
238 Clock Low to BB High Impedance (360 output) – 20 – 15 ns
Note 1 : BG remains low until either the SDMA or the IDMA requests the external bus.
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Notes :
1.
TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
2. BG always remains asserted until either the SDMA or the IDMA requests the external bus.
Figure 29: TS68040 Companion Mode Arbitration
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5.10. 040 Bus Type Slave Mode Internal Read/Write/Iack Cycles AC Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C. The electrical specifications in this document are preliminary (See Figure 30 to 33)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
2511Address, Transfer Attributes Valid to Clock Low 15 – 11.25 – ns
252 TS Low to Clock High 7 – 6 – ns
253 Clock High to TS High 5 – 3 – ns
254 Clock high to Address, T ransfer Attributes Invalid 0 – 0 – ns
255 Data–In, MBARE Valid to Clock High (040 Write) 0 – 0 – ns
256 Clock High to Data–In, MBARE Hold T ime 0 – 0 – ns
257 Clock High to TA, TBI Low (External to External) 4 20 4 15 ns
257 Clock High to TA, TBI Low (External to Internal) 4 23 4 18 ns
2582 3Clock High to TA, TBI High 4 20 4 15 ns
259 TA, TBI High to TA, TBI High Impedance – 15 – 11.25 ns
260 Clock Low to Data–Out Valid (040 Read) – 20 – 15 ns
262 Clock Low to Data–Out Invalid – 20 – 15 ns
263 Clock Low to Data–Out High Impedance – 15 – ns
264 Clock High to AVECO Low – 20 – 15 ns
265 Clock Low to AVECO High Impedance – 30 – 23 ns
266 Clock Low to IACK Low – 30 – 23 ns
267 Clock High to IACK High – 30 – 23 ns
268 Clock Low to AVEC Low – 30 – 23 ns
Notes :
1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK.
2. When TS68040 is accessing the internal registers, specification 258 is from clock low not clock high.
3. The clock reference is EXTAL, not CLK01.
(040 READ)
(OUTPUT)
Note :
1. Three wait states are inserted when reading the SIM, dual–port RAM, and CPM. Four wait states are inserted when reading the SI RAM. Additional
wait states may be inserted when the SHEN1–SHEN0=10 and one of the internal masters is accessing an internal peripheral.
2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
Figure 30: TS68040 Internal Registers Read Cycles
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Notes :
1. T wo wait states are inserted when writing. Three wait states are inserted when writing to the dual–port RAM and CPM. Four wait states are inserted
when writing to the SI RAM. Additional wait states may be inserted when the SHEN1–SHEN0=10 and one of the internal masters is accessing an inter-
nal peripheral.
2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
Figure 31: TS68040 Internal Registers Write Cycles
Note :
1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
2. Up to two wait states may be inserted for internal peripheral.
Figure 32: TS68040 IACK Cycles (Vector Driven)
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Note 1 : TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W , LOCK.
Figure 33: TS68040 IACK Cycles (No Vector Driven)
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5.11. 040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C. The electrical specifications in this document are preliminary (See Figure 34 to Figure 38)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
280 Address Valid to BADD2–3 Valid – 20 – 15 ns
280A BADD2–3 Valid to CAS Assertion 15 – 10 – ns
281 Address Invalid to BADD2–3 Invalid 0 – 0 – ns
282 Clock High to CSx/RASx Low (TSS40=0) 4 16 4 12 ns
283 Clock High to CSx/RASx High (CSNT40=0) 4 16 4 12 ns
284 Clock High to BRK Low – 20 – 15 ns
284A Clock Low to BRK Low – 20 – 15 ns
285 Clock high to BRK High – 20 – 15 ns
286 Clock Low to CSx/RASx Low (TSS40=1) 4 16 4 12 ns
287 Clock Low to CSx/RASx High (CSNT40=1) 4 16 4 12 ns
2881Address Transfer Attributes Valid to Clock High (TSS40=0) 10 – 10 – ns
2892TA Low to Clock High (External Termination) 11 – 9 – ns
2902Clock High to TA High (External Termination) – 20 – 15 ns
291 Clock High to OE Low (Read Cycles) – 20 – 15 ns
292 Clock High to OE High (Read Cycles) – 20 – 15 ns
293 Clock High to WE Low (Write Cycles) – 20 – 15 ns
294 Clock High to WE High (Write Cycles) – 20 – 15 ns
295 Clock High to CASx Low 4 13 4 10 ns
295A Clock Low to CASx Low (040 Burst Read only) 4 13 4 10 ns
2963Clock High to CASx High 4 13 4 10 ns
297 Clock Low to AMUX Low 3 16 3 12 ns
298 Clock High to AMUX High 3 16 3 12 ns
299 Clock High to BADD2–3 Valid (040 Burst Cycles) 4 20 4 15 ns
3002TEA Low to Clock High 11 – – ns
3012Clock High to TEA High 2 20 2 15 ns
302 Data, Parity Valid to Clock High (Data, Parity Setup) 7 – 6 – ns
303 Clock High to Data, Parity Invalid (Data, Parity Hold) 7 – 5 – ns
305 CLKO1 High (After TS Low) to Parity Valid – 20 – 15 ns
306 CLKO1 High (After TA Low) to Parity Hi–Z 4 20 15 ns
Notes :
1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK.
2. TEA/TA should not be asserted on a DRAM burst access, or on the same clock or before RASx/CSx is asserted.
3. The clock reference is EXTAL, not CLK01.
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Note 1 : TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
Figure 34: TS68040 SRAM Read/Write Cycles
(TSS40=0, CSNT40=0)
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Figure 35: TS68040 SRAM Read/Write Cycles
(TSS40 = 1, CSNT40 = 1)
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Figure 36: External TS68040 DRAM Cycles Timing Diagram
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Figure 37: External TS68040 DRAM Burst Cycles Timing Diagram
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Figure 38: External TS68040 Parity Bit Checking Timing Diagram
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5.12.IDMA AC Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 39 and Figure 40)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
1CLKO1 Low to DACK, DONE Asserted 3 24 3 18 ns
2CLKO1 Low to DACK, DONE Negated 3 24 3 18 ns
3(1) DREQx Asserted to AS Asserted (for DMA Bus Cycle) 3tcyc + tAIST + tCLSA
4(1) Asynchronous Input Setup T ime to CLKO1 Low 12 – 9 – ns
51Asynchronous Input Hold T ime from CLKO1 Low 0 – 0 – ns
6 AS to DACK Assertion Skew 0 20 0 15 ns
7 DACK to DONE Assertion Skew –8 8 –6 6 ns
8 AS, DACK, DONE Width Asserted 70 – 52.5 – ns
8A AS, DACK, DONE Width Asserted (Fast Termination Cycle) 28 – 20.5 – ns
10(1) Asynchronous Input Setup T ime to CLKO1 Low 5 – 4 – ns
11(1) Asynchronous Input Hold T ime from CLKO1 Low 10 – 7.5 – ns
12(2) DREQ Input Setup Time to CLKO1 Low 20 – 15 – ns
13(2) DREQ Input Hold Time from CLKO1 Low 5 – 3.75 – ns
14(2) DONE Input Setup Time to CLKO1 Low 20 – 15 – ns
15(2) DONE Input Hold Time From CLKO1 Low 5 – 3.75 – ns
16(2) DREQ Asserted to AS Asserted 2 – 2 – clk
Notes :
1. These specifications are for asynchronous mode.
2. These specifications are for synchronous mode.
Figure 39: IDMA Signal Asynchronous Timing Diagram
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Figure 40: IDMA Signal Synchronous Timing Diagram
5.13.PIP/PIO Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 41 to Figure 45)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
21 Data–In Setup Time to STBI Low 0 – 0 – ns
22 Data–In Hold T ime to STBI High 2.5–t3 – 2.5–t3 – clk
23 STBI Pulse Width 1.5 – 1.5 – clk
24 STBO Pulse Width 1 CLKO1
–5ns – 1CLKO1
–5ns – –
25 Data–Out Setup Time to STBO Low 2 – 2 – clk
26 Data–Out Hold T ime from STBO High 5 – 5 – clk
27 STBI Low to STBO Low (Rx Interlock) – 2 – 2 clk
28 STBI Low to STBO High (Tx Interlock) 2 – 2 – clk
29 Data–In Setup Time to Clock Low 20 – 15 – ns
30 Data–In Hold T ime from Clock Low 10 – 7.5 – ns
Clock High to Data–Out Valid (CPU Writes Data, Control, or Direction) – 25 – 25 ns
Note 1 : t3 = spec. 3 on § 5.5
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Figure 41: PIP Rx (Interlock Mode)
Figure 42: PIP Tx (Interlock Mode)
Figure 43: PIP Tx (Pulse Mode)
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Figure 44: PIP Tx (Pulse Mode)
Figure 45: Parallel I/O Data–in/Data–Out Timing Diagram
5.14.INterrupt Controller AC Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 46 and Figure 47 )
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
35 Port C Interrupt Pulse Width Low (Edge Triggered Mode) 70 – 55 – ns
36 Minimum Time Between Active Edges Port C 70 – 55 – clk
37 Clock High to IOUT Valid (Slave Mode) – 20 – 17 ns
38 Clock High to RQOUT Valid (Slave Mode) – 20 – 17 ns
Figure 46: Interrupts Timing Diagram
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Figure 47: Slave Mode: Interrupts Timing Diagram
5.15.BAUD Rate Generator AC Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 48 )
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
50 BRGO Rise and Fall T ime – 10 – 7.5 ns
51 BRGO Duty Cycle 40 60 40 60 %
52 BRGO Cycle 40 30 ns
Figure 48: Baud Rate Generator Output Signals
5.16.Timer Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 49 )
Num. Characteristic Symbol 25.0 MHz 33.34 MHz Unit
Min Max Min Max
61 TIN/TGATE Rise and Fall Time trf 10 – 10 – ns
62 TIN/TGATE Low Time – 1 – 1 – clk
63 TIN/TGATE High Time – 2 – 2 – clk
64 TIN/TGATE Cycle Time – 3 – 3 – clk
65 CLKO1 High to TOUT Valid tTO 3 25 3 22 ns
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Figure 49: CPM General Purpose Timers
5.17.SI Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 50 to Figure 54 )
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
70(1, 3) L1RCLK, L1TCLK Frequency (DCS=0) – 10 – 10 MHz
71(1) L1RCLK, L1TCLK Width Low (DCS=0) P+10 – P+10 – ns
71A(2) L1RCLK, L1TCLK Width High (DCS=0) P+10 – P+10 – ns
72 L1TXD, L1ST(1–4), L1RQ, L1CLKO Rise/Fall T ime – 15 – 15 ns
73 L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time) 20 – 20 – ns
74 L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold T ime) 35 – 35 – ns
75 L1RSYNC, L1TSYNC Rise/Fall T ime – 15 – 15 ns
76 L1RXD Valid to L1CLK Edge (L1RXD Setup Time) 42 – 42 – ns
77 L1CLK Edge to L1RXD Invalid (L1RXD Hold T ime) 35 – 35 – ns
78 L1CLK Edge to L1ST(1–4) Valid 10 45 10 45 ns
78A(4) L1SYNC Valid to L1ST(1–4) Valid 10 45 10 45 ns
79 L1CLK Edge to L1ST(1–4) Invalid 10 45 10 45 ns
80 L1CLK Edge to L1TXD Valid 10 65 10 65 ns
80A(4) L1TSYNC Valid to L1TXD Valid 10 65 10 65 ns
81 L1CLK Edge to L1TXD High Impedance 0 42 0 42 ns
82 L1RCLK, L1TCLK Frequency (DSC=1) – 12.5 – 16 MHz
83 L1RCLK, L1TCLK Width Low (DSC=1) P+10 – P+10 – ns
83A(2) L1RCLK, L1TCLK Width High (DSC=1) P+10 – P+10 – ns
84 L1CLK Edge to L1CLKO Valid (DSC=1) – 30 – 30 ns
85(3) L1RQ Valid Before Falling Edge of L1TSYNC 1 – 1 – L1TCLK
86(3) L1GR Setup T ime 42 – 42 – ns
87(3) L1RG Hold Time 42 – 42 – ns
88 L1CLK Edge to L1SYNC Valid (FSD=00, CNT=0000, BYT=0, DSC=0) – 0 – 0 ns
Notes :
1. The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2. Where P=1/CLKO1. Thus for a 25 MHz CLKO1 rate, P=40ns.
3. These specs are valid for IDL mode only.
4. The strobes and Txd on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
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Figure 50: SI Receive Timing with Normal Clocking
(DSC=0)
Figure 51: SI Receive Timing with Double Speed Clocking
(DSC=1)
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Figure 52: SI Transmit Timing with Normal Clocking
(DSC=0)
L1TCLK
L1TCLK
Figure 53: SI Transmit Timing with Double Speed Clocking
(DSC=1)
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Figure 54: IDL Timing
5.18.SCC in NMSI Mode-external Clock Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 55 to Figure 57)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
100(1) RCLK1 and TCLK1 Width High CLKO1 – CLKO1 –
101 RCLK1 and TCLK1 Width Low CLKO1
+5ns – CLKO1
+5ns –
102 RCLK1 and TCLK1 Rise/Fall T ime – 15 – 15 ns
103 TXD1 Active Delay (From TCLK1 Falling Edge) 0 50 0 50 ns
104 RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) 0 50 0 50 ns
105 CTS1 Setup T ime to TCLK1 Rising Edge 40 – 40 – ns
106 RXD1 Setup T ime to RCLK1 Rising Edge 40 – 40 – ns
107(2) RXD1 Hold Time from RCLK1 Rising Edge 0 – 0 – ns
108 CD1 Setup T ime to RCLK1 Rising Edge 40 – 40 – ns
Notes :
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1.
2. Also applies to CD and CTS hold time when they are used as an external sync signals.
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5.19.SCC in NMSI Mode-internal Clock Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 55 to Figure 57)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
100(1) RCLK1 and TCLK1 Frequency 0 8.3 0 11 MHz
102 RCLK1 and TCLK1 Rise/Fall T ime – – – – ns
103 TXD1 Active Delay (From TCLK1 Falling Edge) 0 30 0 30 ns
104 RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) 0 30 40 – ns
105 CTS1 Setup T ime to TCLK1 Rising Edge 40 – 40 – ns
106 RXD1 Setup T ime to RCLK1 Rising Edge 40 – 0 – ns
107(2) RXD1 Hold Time from RCLK1 Rising Edge 0 – 40 – ns
108 CD1 Setup T ime to RCLK1 Rising Edge 40 – 0 30 ns
Notes :
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
2. Also applies to CD and CTS hold time when they are used as an external sync signals.
Figure 55: SCC NMSI Receive
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Figure 56: SCC NMSI Transmit
Figure 57: HDLC BUS Timing
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5.20.EThernet Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 58 – Figure 63)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
120 CLSN Width High 40 – 40 – ns
121 RCLK1 Rise/Fall T ime – 15 – 15 ns
122 RCLK1 Width Low CLKO1+
5ns – CLKO1+
5ns –
123(1) RCLK1 Width High CLKO1 – CLKO1 –
124 RXD1 Setup T ime 20 – 20 – ns
125 RXD1 Hold T ime 5 – 5 – ns
126 RENA Active Delay (from RCLK1 rising edge of the last data bit) 10 – 10 – ns
127 RENA Width Low 100 – 100 – ns
128 TCLK1 Rise/Fall T ime – 15 – 15 ns
129 TCLK1 Width Low CLKO1+
5ns – CLKO1+
5ns –
130(1) TCLK1 Width High CLKO1 – CLKO1 –
131 TXD1 Active Delay (from TCLK1 rising edge) 10 50 10 50 ns
132 TXD1 Inactive Delay (from TCLK1 rising edge) 10 50 10 50 ns
133 TENA Active Delay (from TCLK1 rising edge) 10 50 10 50 ns
134 TENA Inactive Delay (from TCLK1 rising edge) 10 50 10 50 ns
135 RSTRT Active Delay (from TCLK1 falling edge) 10 50 10 50 ns
136 RSTRT Inactive Delay (from TCLK1 falling edge) 10 50 10 50 ns
137 RRJCT Width Low 1 – 1 – CLKO1
138(2) CLKO1 Low to SDACK Asserted – 20 – 20 ns
139(2) CLKO1 Low to SDACK Negated – 20 – 20 ns
Notes :
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1.
2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Figure 58: Ethernet Collision Timing
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Figure 59: Ethernet Receive Timing
Notes :
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transit, then CSL bit is set in the buffer descriptor at the end of frame transmission.
Figure 60: Ethernet Transmit Timing
Note : V alid for the ethernet protocol only.
Figure 61: CAM Interface Receive Start Timing
Note : V alid for the ethernet protocol only.
Figure 62: CAM Interface Reject Timing
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Note : SDACKx is asserted when the SDMA writes the received Ethernet frame into memory.
Figure 63: SDACK Timing Diagram
5.21.SMC Transparent Mode Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 64)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
150(1) SMCLK Clock Period 100 – 100 – ns
151 SMCLK Width Low 50 – 50 – ns
151A SMCLK Width High 50 – 50 – ns
152 SMCLK Rise/Fall T ime – 15 – 15 ns
153 SMTXD Active Delay (from SMCLK falling edge) 10 50 10 50 ns
154 SMRXD/SYNC1 Setup T ime 20 – 20 – ns
155 SMRXD/SYNC1 Hold T ime 5 – 5 – ns
Note 1 : The ratio SyncCLK/SMCLK must be greater or equal to 2/1.
Note : This delay is equal to an integer number of ”Character length” clocks.
Figure 64: SMC Transparent
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5.22.SPI Master Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 65 and Figure 66 )
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
160 Master Cycle Time 4 1024 4 1024 tcyc
161 Master Clock (SPICLK) High or Low T ime 2 512 2 512 tcyc
162 Master Data Setup T ime (Inputs) 50 – 50 – ns
163 Master Data Hold T ime (Inputs) 0 – 0 – ns
164 Master Data Valid (after SPICLK Edge) – 20 – 20 ns
165 Master Data Hold T ime (Outputs) 0 – 0 – ns
166 Rise Time : Output 15 15 ns
167 Fall T ime : Ouput 15 15 ns
Figure 65: SPI Master (CP=0)
Figure 66: SPI Master (CP=1)
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5.23.SPI Slave Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 67 and Figure 68)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
170 Slave Cycle Time 2 – 2 – tcyc
171 Slave Enable Lead T ime 15 15 ns
172 Slave Enable Lag T ime 15 15 ns
173 Slave Clock (SPICLK) High or Low T ime 1 – 1 – tcyc
174 Slave Sequential Transfer Delay (Does Not Require Deselect) 1 1 tcyc
175 Slave Data Setup T ime (Inputs) 20 – 20 – ns
176 Slave Data Hold T ime (Inputs) 20 – 20 – ns
177 Slave Access Time 50 50 ns
178 Slave SPIMISO Disable T ime 50 50 ns
179 Slave Data Valid (after SPICLK Edge) – 50 – 50 ns
180 Slave Data Hold T ime (Outputs) 0 – 0 – ns
181 Rise Time : Input 15 15 ns
182 Fall T ime : Input 15 15 ns
Figure 67: SPI Slave (CP=0)
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Figure 68: SPI Slave (CP=1)
5.24.JTAG Electrical Specifications
GND = 0 Vdc, TC = –55 to +125C.The electrical specifications in this document are preliminary (See Figure 69 and Figure 72)
Num. Characteristic 25.0 MHz 33.34 MHz Unit
Min Max Min Max
TCK Frequency of Operation 0 25 0 25 MHz
1TCK Cycle Time in Crystal Mode 40 – 40 – ns
2TCK Clock Pulse Width Measured at 1.5 V 18 – 18 – ns
3TCK rise and Fall T imes 0 3 0 3 ns
6Boundary Scan Input Data Setup T ime 10 – 10 – ns
7Boundary Scan Input Data Hold T ime 18 – 18 – ns
8TCK Low to Output Data Valid 0 30 0 30 ns
9TCK Low to Output High Impedance 0 40 0 40 ns
10 TMS, TDI Data Setup T ime 10 – 10 – ns
11 TMS, TDI Data Hold T ime 10 – 10 – ns
12 TCK Low to TDO Data Valid 0 20 0 20 ns
13 TCK Low to TDO High Impedance 0 20 0 20 ns
14 TRST Assert Time 100 – 100 – ns
15 TRST Setup T ime to TCK Low 40 – 40 – ns
Figure 69: Test Clock Input Timing Diagram
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Figure 70: TRST Timing Diagram
Figure 71: Boundary Scan (JTAG) Timing Diagram
Figure 72: Test Access Port Timing Diagram
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6. FUNCTIONAL DESCRIPTION
6.1. CPU32+ Core
The CPU32+ core is a CPU32 that has been modified to connect directly to the 32–bit IMB and apply the larger bus width. Although the
original CPU32 core had a 32–bit internal data path and 32–bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core
can operate on 32–bit external operands with one bus cycle. This allows the CPU32+ core to fetch a long–word instruction in one bus
cycle an to fetch two word–length instructions in one bus cycle, filling the internal instruction queue more quickly . The CPU32+ core can
also read and write 32–bits of data in one bus cycle.
Although the CPU32+ instruction timings are improved, its instruction set is identical to that of the CPU32. It will also execute the entire
68000 instruction set. It contains the same background debug mode (BDM) features as the CPU32. No new compilers, assemblers or
other software support tools need be implemented for the CPU32+; standard CPU32 tools can be used.
The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted) assumption that a 10–MHz 68000 delivers 1
VAX MIPS. If an application requires more performance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an
intelligent peripheral to a faster processor. The QUICC provides a special mode called TS68040 companion mode to allow it to
conveniently interface to members of the TS68040 family. This two–chip solution provides a 22–MIPS performance at 25 MHz.
The CPU32+ also offers automatic byte alignment features that are not offered on the CPU32. These features allow 16 or 32–bit data to be
read or written at an odd address. The CPU32+ automatically performs the number of bus cycles required.
6.2. System Integration Module (SIM60)
The SIM60 integrates general–purpose features that would be useful in almost any 32–bit processor system. The term ”SIM60” is derived
from the QUICC part number, TS68EN360. The SIM60 is an enhanced version of the SIM40 that exists on the TS68332 device.
First, new features, such as a DRAM controller and breakpoint logic, have been added. Second, the SIM40 was modified to support a
32–bit IMB as well as a 32–bit external system bus. Third, new configurations, such as slave mode and internal accesses by an external
master, are supported.
Although the QUICC is always a 32–bit device internally , it may be configured to operate with a 16–bit data bus. Regardless of the choice
of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8–16–, and 32–bit peripherals and memory to exist in the 32–bit
system bus mode and 8– and 16–bit peripherals and memory to exist in the 16–bit system bus mode.
6.3. Communications Processor Module (CPM)
The CPM contains features that allow the QUICC to excel in communications and control applications. These features may be divided into
three sub-groups:
.Communications Processor (CP)
.Two IDMA Controllers
.Four General–Purpose Timers
The CP provides the communication features of the QUICC. Included are a RISC processor, four SCCs, two SMCs, one SPI, 2.5 Kbytes of
dual–port RAM, an interrupt controller, a time slot assigner, three parallel ports, a parallel interface port, four independent baud rate
generators, and fourteen serial DMA channels to support the SCCs, SMCs, and SPI.
The IDMAs provide two channels of general–purpose DMA capability. They offer high–speed transfers, 32–bit data movement, buffer
chaining, and independent request and acknowledge logic. The RISC controller may access the IDMA registers directly in the buffer
chaining modes. The QUICC IDMAs are similar to, yet enhancements of, the one IDMA channel found on the TS68302.
The four general–purpose timers on the QUICC are functionally similar to the two general–purpose timers found on the TS68302.
However, they offer some minor enhancements, such as the internal cascading of two timers to form a 32–bit timer. The QUICC also
contains a periodic interval timer in the SIM60, bringing the total to five on-chip timers.
6.4. Ethernet on QUICC
The Ethernet protocol is available only on the Ethernet version of the QUICC called the TS68EN360. The non-Ethernet version of the
QUICC is the MC68360. The term ”QUICC” is the overall device name that denotes all versions of the device.
The TS68EN360 is a superset of the MC68360, having the additional option allowing Ethernet operation on any of the four SCCs. Due to
performance reason not ass SCCs can be configured as Ethernet controller at the same time. The TS68EN360 is not restricted only to
Ethernet operation. HDLC, UART , and other protocols may be used to allow dynamic switching between protocols. See Appendix A Serial
Performance for available SCC perfrormance.
When the MODE bits of the SCC GSMR select the Ethernet protocol, then that SCC performs the full set of IEEE 802.3/Ethernet
CSMA/CD media access control and channel interface functions (see Figure 73 ).
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Figure 73: Ethernet Block Diagram
6.5. Upgrading Designs from the TS68302
Since the QUICC is a next–generation TS68302, many designers currently using the TS68302 may wish to use the QUICC in a follow–on
design. The following paragraphs briefly discuss this endeavor in terms of architectural approach, hardware issues, and software issues.
6.5.1.Architectural Approach
The QUICC is the logical extension of the TS86302, but the overall architecture and philosophy of the TS86302 design remains intact in
the QUICC. The QUICC keeps the best features of the TS86302, while making the changes required to provide for the increased flexibility,
integration, and performance requested by customers. Because the CPM is probably the most difficult module to learn, anyone who has
used the TS86302 can easily become familiar with the QUICC since the CPM architectural approach remains intact.
The most significant architectural change made on the QUICC was the translation of the design into the standard 68300 family IMB
architecture, resulting in a faster CPU and different system integration features.
Although the features of the SIM60 do not exactly correspond to those of the TS86302 SIM, they are very similar.
Because of the similarity of the QUICC SIM60 and CPU to other members of the 68300 family, such as the TS68332, previous users of
these devices will be comfortable with these same features on the QUICC.
6.5.2.Hardware Compatibility Issues
The following list summarizes the hardware differences between the TS86302 and the QUICC:
- Pinout – The pinout is not the same. The QUICC has 240 pins ; the TS86302 has 132 pins.
- Package–Both devices offer PGA and PQFP packages. However, the QUICC QFP package has a 20–mil pitch; whereas, the
TS86302 QFP package has a 25–mil pitch.
- System Bus – The system bus signals now look like those of the TS68020 as opposed to those of the 68000. It is still possible to
interface 68000 peripherals to the QUICC, utilizing the same techniques used to interface them to a TS68020.
- System Bus in Slave Mode – A number of QUICC pins take on new functionality in slave mode to support an external TS68EC040.
On the TS68302, the pin names generally remained the same in slave mode.
- Peripheral Timing – The external timings of the peripherals (SCCs, timers, etc.) are very similar (if not identical) to corresponding
peripherals on the TS68302.
- Pin Assignments – The assignment of peripheral functions to I/O pins is different in several ways. First, the QUICC contains more
general–purpose parallel I/O pins than the TS68302. However , the QUICC offers many more functions than even a 240–pin package
would normally allow, resulting in more multifunctional pins than the TS68302.
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6.5.3.Software Compatibility Issues
The following list summarizes the major software differences between the TS68302 and the QUICC:
- Since the CPU32+ is a superset of the 68000 instruction set, all previously written code will run. However, if such code is accessing
the TS68302 peripherals, it will require some modification.
- The QUICC contains an 8–Kbyte block of memory as opposed to a 4–Kbyte block on the TS68302. The register addresses within
that memory map are different.
- The code used to initialize the system integration features of the TS68302 has to be modified to write the corresponding features on
the QUICC SIM60.
- As much as possible, QUICC CPM features were made identical to those of the TS68302 CP. The most important benefit is that the
code flow (if not the code itself) will port easily from the TS68302 to the QUICC. The nuances learned from the TS68302 will still be
useful in the QUICC.
- Although the registers used to initialize the QUICC CPM are new (for example, the SCM on the TS68302 is replaced with the GSMR
and PSMR on the QUICC), most registers retain their original purpose such as the SCC event, SCC mask, SCC status, and command
registers. The parameter RAM of the SCCs is very similar, and most parameter RAM register names and usage are retained. More
importantly, the basic structure of a buffer descriptor (BD) on the QUICC is identical to that of the TS68302, except for a few new bit
functions that were added. (In a few cases, a bit in a BD status word had to be shifted.)
- When porting code from the TS68302 CP to the QUICC CPM, the sofware writer may find that the QUICC has new options to simplify
what used to be a more code–intensive process. For specific examples, see the INIT TX AND RX P ARAMETERS, GRACEFUL STOP
TRANSMIT, and CLOSE BD commands.
7. PREPARATION FOR DELIVERY
7.1. Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535 or TCS standard.
7.2. Certificate of compliance
TCS offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL–STD–883 or
TCS standard and guarantying the parameters not tested at temperature extremes for the entire temperature range.
8. HANDLING
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices
have been designed in the chip to minimize the effect of this static buildup. However , the following handling practices are recommended :
a) Devices should be handled on benches with conductive and grounded surfaces.
b) Ground test equipment, tools and operator.
c) Do not handle devices by the leads.
d) Store devices in conductive foam or carriers.
e) Avoid use of plastic, rubber, or silk in MOS areas.
f) Maintain relative humidity above 50 percent if practical.
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9. PACKAGE MECHANICAL DATA
9.1. 241 pins – PGA
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 1.840 1.880 46.74 47.75
C 0.110 0.140 2.79 3.56
D 0.016 0.020 0.41 0.51
E 0.045 0.055 1.143 1.4
F 0.045 0.055 1.143 1.4
G0.100 BASIC 2.54 BASIC
K 0.150 0.170 3.81 4.32
118
A
T
(BOTTOM VIEW)
A1
A K
E
C
DF
G
G
A
(top view)
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9.2. 240 pins – CERQUAD
Notes :
1. Dimensioning and tolerancing per ASME Y 14.5, 1994.
2. Controlling dimension : millimeter .
3. Datum plane –H– is located at bottom of lead and is coincident with
the lead where the lead exits the ceramic body at the bottom of the
parting line.
4. Datums –L–, –M– and –N– to be determined at datum plane –H–.
5. Dimensions S and V to be determined at seating plane –T–.
6. Dimensions A and B define maximum ceramic body dimensions
including glass protrusion and top and bottom mismatch.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 30.86 31.75 1.215 1.250
B 30.86 31.75 1.215 1.250
C 3.67 4.15 0.144 0.163
D 0.18 0.30 0.007 0.012
E 3.10 3.90 0.122 0.154
F 0.17 0.23 0.007 0.009
G0.50 BSC 0.019 BSC
J 0.13 0.175 0.005 0.007
K 0.45 0.55 0.018 0.021
P0.25 BSC 0.010 BSC
R0.15 BSC 0.006 BSC
S 34.41 34.75 1.355 1.37
U17.30 BSC 0.681 BSC
V 34.41 34.75 1.355 1.37
W 0.25 0.75 0.01 0.03
Y17.30 BSC 0.681 BSC
Z 0.12 0.13 0.005 0.005
AA 1.80 REF 0.071 REF
AB 0.95 REF 0.037 REF
2 1° 7° 1° 7°
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÉÉÉ
ÉÉÉ
ÉÉÉ
240
181
61
120
180 121
1 60
U
S
Y
V
A
B
0.25 (0.010)
-M-
-L-
-N-
T L-N MHMS
L-N S
0.20 (0.008)M
W
E
C
0.10 (0.004)
-H- DATUM
PLANE
SEATING
PLANE
ÉÉÉ
ÉÉÉ
ÉÉÉ
G
P
-X-
AD
AD
X=L, M or N
VIEW AC
F
J
D
Z
T M S
L-N S
0.08 (0.003)M
SECTION AD
240 PLACES
VIEW AC
4 PLACES
AB
2
K
AA
VIEW AE
-H- DATUM
PLANE
VIEW AE
-T-
4 X60 TIPS
TS68EN360
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10.ORDERING INFORMATION
10.1. Hi–REL product
Commercial TCS Part–Number
(See Note)
Norms Package Temperature range
Tc (C) Frequency
(MHz) Drawingnumber
TS68EN360MRB/C25 MIL–STD–883 PGA 241 Gold –55 / +125 25 –
TS68EN360MRB/C33 MIL–STD–883 PGA 241 Gold –55 / +125 33 –
TS68EN360MR1B/C25 MIL–STD–883 PGA 241 T inned –55 / +125 25 –
TS68EN360MR1B/C33 MIL–STD–883 PGA 241 T inned –55 / +125 33 –
TS68EN360MAB/C25 MIL–STD–883 CERQUAD 240 –55 / +125 25 –
TS68EN360MAB/C33 MIL–STD–883 CERQUAD 240 –55 / +125 33 –
TS68EN360DESC01MXC DSCC PGA 241 Gold –55 / +125 25 5962-9760701MXC
TS68EN360DESC02MXC DSCC PGA 241 Gold –55 / +125 33 5962-9760702MXC
TS68EN360DESC01MXA DSCC PGA 241 Tinned –55 / +125 25 5962-9760701MXA
TS68EN360DESC02MXA DSCC PGA 241 Tinned –55 / +125 33 5962-9760702MXA
TS68EN360DESC01MYA DSCC CERQUAD 240 –55 / +125 25 5962-9760701MYA
TS68EN360DESC02MYA DSCC CERQUAD 240 –55 / +125 33 5962-9760702MYA
10.2. Standard product
Commercial TCS Part–Number
(See Note)
Norms Package Temperature range
Tc (C) Frequency
(MHz) Drawingnumber
TS68EN360VR25 TCS Standard PGA 241 –40 / +85 25 Internal
TS68EN360MR25 TCS Standard PGA 241 –55 / +125 25 Internal
TS68EN360VA25 TCS Standard CERQUAD 240 –40 / +85 25 Internal
TS68EN360MA25 TCS Standard CERQUAD 240 –55 / +125 25 Internal
TS68EN360VR33 TCS Standard PGA 241 –40 / +85 33 Internal
TS68EN360MR33 TCS Standard PGA 241 –55 / +125 33 Internal
TS68EN360VA33 TCS Standard CERQUAD 240 –40 / +85 33 Internal
TS68EN360MA33 TCS Standard CERQUAD 240 –55 / +125 33 Internal
Note :
THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
TS68EN360
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Operating frequency :
Generic
TS68EN360 M R B/C
M : –55°C, + 125°C
V : –40°C, + 110°C
C : 0°C/ +70°C
25
Temperature range : (TC )
R = Pin grid array 241 (gold)
A = CERQUAD 240 (tin)
Package : 25 : 25 MHz
33 : 33 MHz
––– = Standard
B/C = MIL STD 883 Class B
B/T = According to MIL-STD883
D/T = Standard + Burn in
Screening :
_ = Gold (for PGA)
_ = Hot solder dip (for CERQUAD)
1 = Hot solder dip (for PGA - On request)
Hirel lead finish :
(TSX)
Prototype version
1
TS68EN360
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Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of THOMSON-
CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to change without notice. This pub-
lication supersedes and replaces all information previously supplied. THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES products
are not authorized for use as critical components in life support devices or systems without express written approval from THOMSON-
CSF SEMICONDUCTEURS SPECIFIQUES.
1999 THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Printed in France - All rights reserved.
This product is manufactured and commercialized by THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - PO Box 123 -
38521 SAINT-EGREVE Cedex - FRANCE.
For further information please contact :
THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Route Départementale 128 - PO Box 46 - 91401 ORSA Y Cedex - FRANCE -
Phone (33) 01 69 33 00 00 - Telex 616780 F TCS - Fax (33) 01 69 33 03 21 E–mail : lafriquetcs.thomson–csf.com.
