PE94302-11 - Peregrine Semiconductor Corp.

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28-lead CQFP

Figure 2. Package Type

The PE94302 is a high linearity, 6-bit UltraCMOS™ RF Digital

Step Attenuator (DSA). This 50-ohm RF DSA covers a 31.5 dB

attenuation range in 0.5 dB steps. It provides both parallel and

serial CMOS control interface. The PE94302 maintains high

attenuation accuracy over frequency and temperature and

exhibits very low insertion loss and power consumption.

The PE94302 is optimized for commercial space applications.

Single Event Latch up (SEL) is physically impossible and

Single Event Upset (SEU) is better than 10-9 errors per bit /

day. Fabricated in Peregrine’s UltraCMOS™ technology, a

patented variation of silicon-on-insulator (SOI) technology on a

sapphire substrate, the PE94302 offers excellent RF

performance and intrinsic radiation tolerance.

Product Specification

50 Ω RF Digital Step Attenuator

For Rad-Hard Space Applications

6-bit, 31.5 dB, DC – 4.0 GHz

Product Description

Figure 1. Functional Schematic Diagram

PE94302

Features

• Attenuation: 0.5 dB steps to 31.5 dB

• Flexible parallel and serial programming

interfaces

• 100 Krads (Si) Total Dose

• Positive CMOS control logic

• High attenuation accuracy and linearity

over temperature and frequency

• Low power - 100 µA at 3.0V

• 50  impedance

Control Logic Interface

Parallel Control

Serial Control

RF Input RF Output

Switched Attenuator Array

6

3

Table 1. Electrical Specifications @ -40°C ≤ Temp ≤ +85°C, 2.7V ≤ VDD ≤ 3.30V

Notes: 1. Device Linearity will begin to degrade below 1 MHz

2. Maximum Operating Power = +12 dBm

3. Specs are guaranteed to 2.2 GHz, Characterized to 4.0 GHz

Parameter Test Conditions Frequency Min Typical Max Units

Operation Frequency DC - 4000 MHz

Insertion Loss DC - 2.2 GHz 1.5 2.75 dB

Attenuation Accuracy

0.5 dB - 8.0 dB Atten. DC - 1.0 GHz - (0.55 + 3.7% of atten. setting) + (0.55 + 3.7% of atten. setting)

dB

8.5 dB - 31.5 dB Atten. + 0.9

0.5 dB - 4.0 dB Atten.

1.0 - 2.2 GHz

+ (0.70 + 3.0% of atten. setting)

4.5 dB - 31.5 dB Atten. + 0.9

0.5 dB - 23.0 dB Atten. - (0.7+ 3.0% of atten. setting)

23.5 dB - 31.5 dB Atten. - (0.6 + 9.0% of atten. setting)

1 dB Compression 1 MHz - 2.2 GHz 33 dBm

Input IP3 Two-tone inputs 52 dBm

Return Loss DC - 2.2 GHz 15 dB

RF Input Power (50 ) 12 dBm

Switching Speed Min to Max Atten. State 1 µs

Product Specification

PE94302

Page 2 of 6

Table 2. Pin Descriptions

Table 3. Absolute Maximum Ratings

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS™ de vice, observe the

same precautions that you would use with other ESD-

sensitive devices. Although this device contains

circuitry to protect it from damage due to ESD,

precautions should be taken to avoid exceeding the

rate specified.

Exposed Solder Pad Connection

The exposed solder pad on the bottom of the package

must be grounded for proper device operation.

Table 4. Operating Ranges

Figure 3. Pin Configuration (Top View)

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 4.0 V

VI Voltage on any DC input -0.3 VDD+

0.3 V

TST Storage temperature range -65 150 °C

PIN Input power (50) 24 dBm

VESD ESD voltage (Human Body

Model) 500 V

Vss Negative Power supply

voltage (-VDD) -4.0 0.3 V

Parameter Min Typ Max Units

VDD Power Supply Voltage 2.7 3.0 3.3 V

IDD Power Supply Current 250 µA

Digital Input High 0.7xVDD V

Digital Input Low 0.3xVDD V

Digital Input Leakage 1 µA

TOP Operating temperature

range -40 85 °C

Vss Power Supply Voltage -3.3 -3.0 -2.7 V

Iss Power Supply Current -500 µA

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS™

devices are immune to latch-up.

Switching Frequency

The PE94302 has a maximum 25 kHz switching rate.

Pin No. Pin Name

1 C16

2 GND

3 RF1

4 GND

5 Data

6 GND

7 CLK

8 LE

9 VDD

10 GND

11 RS1

12 GND

13 RS2

14 VSS

15 Reset

16 GND

17 P/S

18 GND

19 RF2

20 GND

21 C8

22 C4

23 C2

24 GND

25 GND

26 GND

27 C1

28 C0.5

Paddle GND

Description

Attenuation control bit, 16dB

Ground connection

RF port (Note 1).

Ground connection

Serial interface data input

Ground connection

Serial interface clock input.

Latch Enable input (Note 2).

Power supply pin.

Ground connection

Redundant Signal (note 3)

Ground connection

Redundant Signal (Note 3)

Negative supply voltage (Note 4)

Reset (Note 5)

Ground connection

Parallel/Serial mode select.

Ground connection

RF port (Note 1).

Ground connection

Attenuation control bit, 8 dB.

Attenuation control bit, 4 dB.

Attenuation control bit, 2 dB.

Ground connection

Attenuation control bit, 1 dB.

Attenuation control bit, 0.5 dB.

Ground connection

PE94302

2511

5

3

17

19

1

2

418

6

7

20

21

16

15

26

24

27

28

23

22

10

9

8

12

13

14

C16

GND

RF1

GND

GND GND

GND

GND GND

GND

Data

CLK

LE

VDD

RS1

RS2

VSS

Reset

P/S

RF2

C8

C4

C2

C1

C0.5

Note 1: Both RF ports must be held at 0 VDC or DC blocked with an

external series capacitor.

2: Latch Enable (LE) has an internal 100 k resistor to VDD.

3: Must be tied to Vdd or GND un der normal operation.

4: Must be tied to external supply with VSS = -VDD

5: Must be tied to GND under normal operation

Exceeding absolut e maximum ratings may cause

permanent damage. Operation should be restricted to

the limits in the Operating Ranges table. Operation

between operating range maximum and absolute

maximum for extended periods may reduce reliability.

Product Specification

PE94302

Page 3 of 6

Programming Options

Parallel/Serial Selection

Either a parallel or serial interface can be used to

control the PE94302. The P/S bit provides this

selection, with P/S=LOW selecting the parallel

interface and P/S=HIGH selecting the serial

interface.

Parallel Mode Interface

The parallel interface consists of six CMOS-

compatible control lines that select the desired

attenuation state, as shown in Table 5.

The parallel interface timing requirements are

defined by Figure 5 (Parallel Interface Timing

Diagram), Table 8 (Parallel Interface AC

Characteristics), and switching speed (Table 1).

For latched parallel programming the Latch Enable

(LE) should be held LOW while changing attenuation

state control values, then pulse LE HIGH to LOW

(per Figure 5) to latch new attenuation state into

device.

For direct parallel programming, the Latch Enable

(LE) should be either pulled high or floated (see

Table 2, note 2). Changing attenuation state control

values will change device state to new attenuation.

Direct Mode is ideal for manual control of the device

(using hardwire, switches, or jumpers).

P/S C16 C8 C4 C2 C1 C0.5

Attenuation

State

0 0 0 0 0 0 0 Reference Loss

0 0 0 0 0 0 1 0.5 dB

0 0 0 0 0 1 0 1 dB

0 0 0 0 1 0 0 2 dB

0 0 0 1 0 0 0 4 dB

0 0 1 0 0 0 0 8 dB

0 1 0 0 0 0 0 16 dB

0 1 1 1 1 1 1 31.5 dB

Table 5. Truth Table

Note: Not all 64 possible combinations of C0.5-C16 are shown in table

Serial Interface

The serial interface is a 6-bit serial-in, parallel-out

shift register buffered by a transparent latch. It is

controlled by three CMOS-compatible signals : Data,

Clock, and Latch Enable (LE). The Data and Clock

inputs allow data to be serially entered into the shift

register, a process that is independent of the state of

the LE input.

The LE input controls the latch. When LE is HIGH,

the latch is transparent and the contents of the serial

shift register control the attenuator. When LE is

brought LOW, data in the shift register is latched.

The shift register should be loaded while LE is held

LOW to prevent the attenuator value from changing

as data is entered. The LE input should then be

toggled HIGH and brought LOW again, latching the

new data. The timing for this operation is defined by

Figure 4 (Serial Interface Timing Diagram) and Tabl e

7 (Serial Interface AC Characteristics).

Product Specification

PE94302

Page 4 of 6

Table 6. 6-Bit Attenuator Serial Programming

Register Map

Table 8. Parallel Interface AC Characteristics

Figure 5. Parallel Interface Timing Diagram

Table 7. Serial Interface AC Characteristics

Figure 4. Serial Interface Timing Diagram

LE

Clock

Data MSB LSB

t

LESUP

t

SDSUP

t

SDHLD

t

LEPW

B5 B4 B3 B2 B1 B0

C16C8C4C2C1C0.5

↑↑

LSB (last in)MSB (first in)

t

PDSUP

t

PDHLD

Parallel Data

C16:C0.5

LE

t

LEPW

Symbol Parameter Min Max Unit

fClk Serial data clock

frequency (Note 1) 10 MHz

tClkH Serial clock HIGH time 30 ns

tClkL Serial clock LOW time 30 ns

tLESUP LE set-up time after last

clock falling edge 10 ns

tLEPW LE minimum pulse width 30 ns

tSDSUP Serial data set-up time

before clock rising edge 10 ns

tSDHLD Serial data hold time

after clock falling edge 10 ns

Note: fClk is verified during the functional pattern test. Serial

programming sections of the functional pattern are clocked at

10 MHz to verify fclk specification.

Symbol Parameter Min Max Unit

tLEPW LE minimum pulse width 10 ns

tPDSUP Data set-up time before

rising edge of LE 10 ns

tPDHLD Data hold time after

falling edge of LE 10 ns

VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified

Product Specification

PE94302

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Figure 8. Insertion Loss

Figure 6. Input Return Loss vs. Frequency Figure 7. Output Return Loss vs. Frequency

Typical Performance Data @ 25°C, VDD = 3.0 V

Figure 9. Attenuation Setting vs. Frequency

Product Specification

PE94302

Page 6 of 6

Figure 10. Attenuation Error vs. Frequency Figure 11. Attenuation Error vs. Setting

Typical Performance Data @ 25°C, VDD = 3.0 V

Figure 12. IIP3 vs. Frequency Figure 13. 1 dB Compression vs. Frequency

Product Specification

PE94302

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Table 9. Ordering Information

Order Code Part Marking Description Package

Shipping

Method

94302-01 94302 PE94302-28CQFP-50B Engineering Samples 28-lead CQFP 25 Count Trays

94302-11 94302 PE94302-28CQFP-50B Production Units 28-lead CQFP 25 Count Trays

94302-00 PE94302-EK PE94302 Evaluation Kit Evaluation Board 1 / Box

Figure 14. Package Drawing (dimensions in inches)

28-lead CQFP

Product Specification

PE94302

Page 8 of 6

Sales Offices

The Americas

Peregrine Semiconductor Corporation

9380 Carroll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Fax: 858-731-9499

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F-92380 Garches, France

Tel: +33-1-4741-9173

Fax : +33-1-4741-9173

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preli m inary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine

decides to change the specifications, Peregrine will notify

customers of the intended changes by issuing a DCN

(Document Change Notice).

The information in this data sheet is beli eved to be reliable.

However, Peregrine assumes no li ability for the use of this

information. Use shall be entirely at the user ’s own risk.

No patent rights or licenses to any circuits describe d in this

data sheet are implied or gran ted to any third party.

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to supp ort or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregrine assumes no li ability for damages, including

consequential or incidental da mages, arising out of the use of

its products in such applications.

The Peregrine name, logo, and UTSi are registered trademarks

and UltraCMOS and HaRP ar e trademarks of Peregrine

Semiconductor Corp.

Space and Defense Products

Americas:

Tel: 858-731-9453

Europe, Asia Pacific:

180 Rue Jean de Guiram and

13852 Aix-En-Provence Cedex 3, France

Tel: +33-4-4239-3361

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Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

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Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

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