Product Specification PE94302 Product Description The PE94302 is a high linearity, 6-bit UltraCMOSTM RF Digital Step Attenuator (DSA). This 50-ohm RF DSA covers a 31.5 dB attenuation range in 0.5 dB steps. It provides both parallel and serial CMOS control interface. The PE94302 maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and power consumption. 50 RF Digital Step Attenuator For Rad-Hard Space Applications 6-bit, 31.5 dB, DC - 4.0 GHz Features * Attenuation: 0.5 dB steps to 31.5 dB * Flexible parallel and serial programming interfaces * 100 Krads (Si) Total Dose * Positive CMOS control logic The PE94302 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. Fabricated in Peregrine's UltraCMOSTM technology, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, the PE94302 offers excellent RF performance and intrinsic radiation tolerance. * High attenuation accuracy and linearity over temperature and frequency * Low power - 100 A at 3.0V * 50 impedance Figure 1. Functional Schematic Diagram Figure 2. Package Type 28-lead CQFP Switched Attenuator Array RF Input RF Output Parallel Control 6 Serial Control 3 Control Logic Interface Table 1. Electrical Specifications @ -40C Temp +85C, 2.7V VDD 3.30V Parameter Test Conditions Operation Frequency Typical 8.5 dB - 31.5 dB Atten. Units DC - 1.0 GHz 1.5 2.75 dB + (0.55 + 3.7% of atten. setting) - (0.55 + 3.7% of atten. setting) + 0.9 0.5 dB - 4.0 dB Atten. + (0.70 + 3.0% of atten. setting) 4.5 dB - 31.5 dB Atten. + 0.9 0.5 dB - 23.0 dB Atten. 1.0 - 2.2 GHz 23.5 dB - 31.5 dB Atten. 1 dB Compression dB - (0.7+ 3.0% of atten. setting) - (0.6 + 9.0% of atten. setting) 1 MHz - 2.2 GHz Two-tone inputs Return Loss DC - 2.2 GHz 33 dBm 52 dBm 15 dB RF Input Power (50 ) Switching Speed Max MHz DC - 2.2 GHz 0.5 dB - 8.0 dB Atten. Input IP3 Min DC - 4000 Insertion Loss Attenuation Accuracy Frequency 12 Min to Max Atten. State 1 dBm s Notes: 1. Device Linearity will begin to degrade below 1 MHz 2. Maximum Operating Power = +12 dBm 3. Specs are guaranteed to 2.2 GHz, Characterized to 4.0 GHz Document No. 70-0186-04 www.psemi.com (c)2005-2008 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 6 PE94302 Product Specification 22 C4 23 C2 24 GND 25 GND 26 GND 27 C1 28 C0.5 Figure 3. Pin Configuration (Top View) Symbol C16 1 21 C8 GND 2 20 GND RF1 3 19 RF2 GND 4 18 GND Data 5 17 P/S GND 6 16 GND CLK 7 15 Reset 14 VSS 13 GND 12 RS2 11 RS1 9 GND 10 8 LE VDD PE94302 Table 3. Absolute Maximum Ratings Parameter/Conditions Min Max Units VDD Power supply voltage -0.3 4.0 V Vss Negative Power supply voltage (-VDD) -4.0 0.3 V VI Voltage on any DC input -0.3 VDD+ V TST Storage temperature range -65 150 C Input power (50) 24 dBm ESD voltage (Human Body Model) 500 V PIN VESD 0.3 Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Table 2. Pin Descriptions Pin No. Pin Name 1 2 3 4 5 6 7 C16 GND RF1 GND Data GND CLK Attenuation control bit, 16dB Ground connection RF port (Note 1). Ground connection Serial interface data input Ground connection Serial interface clock input. Description 8 LE Latch Enable input (Note 2). 9 10 11 12 13 VDD GND RS1 GND RS2 Power supply pin. Ground connection Redundant Signal (note 3) Ground connection Redundant Signal (Note 3) 14 15 16 17 18 19 20 21 VSS Reset GND P/S GND RF2 GND C8 Negative supply voltage (Note 4) Reset (Note 5) Ground connection Parallel/Serial mode select. Ground connection RF port (Note 1). Ground connection Attenuation control bit, 8 dB. 22 C4 Attenuation control bit, 4 dB. 23 24 25 26 27 C2 GND GND GND C1 Attenuation control bit, 2 dB. Ground connection Ground connection Ground connection Attenuation control bit, 1 dB. 28 Paddle C0.5 GND Attenuation control bit, 0.5 dB. Ground connection Note 1: Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor. 2: Latch Enable (LE) has an internal 100 kresistor to VDD. 3: Must be tied to Vdd or GND under normal operation. 4: Must be tied to external supply with VSS = -VDD 5: Must be tied to GND under normal operation (c)2005-2008 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 6 Table 4. Operating Ranges Parameter Min Typ Max Units VDD Power Supply Voltage 2.7 3.0 3.3 V Vss Power Supply Voltage -3.3 -3.0 -2.7 V 250 A IDD Power Supply Current Iss Power Supply Current -500 TOP Operating temperature range -40 Digital Input High A 85 V 0.7xVDD Digital Input Low Digital Input Leakage C 0.3xVDD V 1 A Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Switching Frequency The PE94302 has a maximum 25 kHz switching rate. Document No. 70-0186-04 UltraCMOSTM RFIC Solutions PE94302 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE94302. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of six CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 5 (Parallel Interface Timing Diagram), Table 8 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 5) to latch new attenuation state into device. Serial Interface The serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 4 (Serial Interface Timing Diagram) and Table 7 (Serial Interface AC Characteristics). For direct parallel programming, the Latch Enable (LE) should be either pulled high or floated (see Table 2, note 2). Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Table 5. Truth Table P/S C16 C8 C4 C2 C1 C0.5 Attenuation State 0 0 0 0 0 0 0 Reference Loss 0 0 0 0 0 0 1 0.5 dB 0 0 0 0 0 1 0 1 dB 0 0 0 0 1 0 0 2 dB 0 0 0 1 0 0 0 4 dB 0 0 1 0 0 0 0 8 dB 0 1 0 0 0 0 0 16 dB 0 1 1 1 1 1 1 31.5 dB Note: Not all 64 possible combinations of C0.5-C16 are shown in table Document No. 70-0186-04 www.psemi.com (c)2005-2008 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 6 PE94302 Product Specification Figure 4. Serial Interface Timing Diagram Table 6. 6-Bit Attenuator Serial Programming Register Map LE Clock Data MSB tLESUP tSDHLD B4 B3 B2 B1 B0 C8 C4 C2 C1 C0.5 MSB (first in) LSB tSDSUP B5 C16 LSB (last in) tLEPW Figure 5. Parallel Interface Timing Diagram LE Parallel Data C16:C0.5 tPDSUP tLEPW tPDHLD Table 7. Serial Interface AC Characteristics Table 8. Parallel Interface AC Characteristics VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol Parameter Min Max Unit 10 MHz fClk Serial data clock frequency (Note 1) tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tLESUP LE set-up time after last clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns tSDSUP Serial data set-up time before clock rising edge 10 ns tSDHLD Serial data hold time after clock falling edge 10 ns Note: Symbol Parameter Min Max Unit tLEPW LE minimum pulse width 10 ns tPDSUP Data set-up time before rising edge of LE 10 ns tPDHLD Data hold time after falling edge of LE 10 ns fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. (c)2005-2008 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 6 Document No. 70-0186-04 UltraCMOSTM RFIC Solutions PE94302 Product Specification Typical Performance Data @ 25C, VDD = 3.0 V Figure 6. Input Return Loss vs. Frequency Figure 8. Insertion Loss Document No. 70-0186-04 www.psemi.com Figure 7. Output Return Loss vs. Frequency Figure 9. Attenuation Setting vs. Frequency (c)2005-2008 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 6 PE94302 Product Specification Typical Performance Data @ 25C, VDD = 3.0 V Figure 10. Attenuation Error vs. Frequency Figure 11. Attenuation Error vs. Setting Figure 12. IIP3 vs. Frequency Figure 13. 1 dB Compression vs. Frequency (c)2005-2008 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 6 Document No. 70-0186-04 UltraCMOSTM RFIC Solutions PE94302 Product Specification Figure 14. Package Drawing (dimensions in inches) 28-lead CQFP Table 9. Ordering Information Order Code Part Marking Description Shipping Method Package 94302-01 94302 PE94302-28CQFP-50B Engineering Samples 28-lead CQFP 25 Count Trays 94302-11 94302 PE94302-28CQFP-50B Production Units 28-lead CQFP 25 Count Trays 94302-00 PE94302-EK PE94302 Evaluation Kit Evaluation Board 1 / Box Document No. 70-0186-04 www.psemi.com (c)2005-2008 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 6 PE94302 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Europe Peregrine Semiconductor Europe Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Space and Defense Products Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). (c)2005-2008 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 6 The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. Document No. 70-0186-04 UltraCMOSTM RFIC Solutions