MC14584BFR2 - ON Semiconductor

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3 1Publication Order Number:

MC14584B/D

MC14584B

Hex Schmitt Trigger

The MC14584B Hex Schmitt Trigger is constructed with MOS

P–channel and N–channel enhancement mode devices in a single

monolithic structure. These devices find primary use where low power

dissipation and/or high noise immunity is desired. The MC14584B

may be used in place of the MC14069UB hex inverter for enhanced

noise immunity to “square up” slowly changing waveforms.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load over the Rated Temperature Range

•Double Diode Protection on All Inputs

•Can Be Used to Replace MC14069UB

•For Greater Hysteresis, Use MC14106B which is Pin–for–Pin

Replacement for CD40106B and MM74Cl4

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range –0.5 to +18.0 V

Vin, Vout Input or Output V oltage Range

(DC or Transient) –0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin ±10 mA

PDPower Dissipation,

per Package (Note 3.) 500 mW

TAAmbient Temperature Range –55 to +125 °C

Tstg Storage Temperature Range –65 to +150 °C

TLLead Temperature

(8–Second Soldering) 260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either VSS or VDD). Unused outputs must be left open.

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A = Assembly Location

WL or L = W afer Lot

YY or Y = Year

WW or W = Work Week

MARKING

DIAGRAMS

PDIP–14

P SUFFIX

CASE 646

MC14584BCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

TSSOP–14

DT SUFFIX

CASE 948G

14584B

AWLYWW

584B

ALYW

SOEIAJ–14

F SUFFIX

CASE 965

MC14584B

AWLYWW

Device Package Shipping

ORDERING INFORMATION

MC14584BCP PDIP–14 2000/Box

MC14584BD SOIC–14 55/Rail

MC14584BDR2 SOIC–14 2500/Tape & Reel

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

MC14584BDTEL TSSOP–14 2000/Tape & Reel

MC14584BDT TSSOP–14 96/Rail

MC14584BF SOEIAJ–14 See Note 1.

MC14584BFEL SOEIAJ–14 See Note 1.

MC14584B

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PIN ASSIGNMENT

105

OUT 5

IN 5

OUT 6

IN 6

VDD

OUT 4

IN 4

OUT 2

IN 2

OUT 1

IN 1

VSS

OUT 3

IN 3

LOGIC DIAGRAM

VDD = PIN 14

VSS = PIN 7

EQIVALENT CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN)

MC14584B

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

– 55

C 25

C 125

Characteristic Symbol

VDD

Vdc Min Max Min Typ (4.) Max Min Max Unit

Output Voltage “0” Level

Vin = VDD VOL 5.0

—

0.05

—

0.05

—

0.05

Vdc

Vin = 0 “1” Level VOH 5.0

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

—

4.95

9.95

14.95

—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH 5.0

5.0

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

mAdc

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

Input Current Iin 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

Input Capacitance

(Vin = 0) Cin — — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package) IDD 5.0

—

0.25

0.5

1.0

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

7.5

µAdc

Total Supply Current (5.) (6.)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

IT5.0

IT = (1.8 µA/kHz) f + IDD

IT = (3.6 µA/kHz) f + IDD

IT = (5.4 µA/kHz) f + IDD

µAdc

Hysteresis Voltage VH (7.) 5.0

0.27

0.36

0.77

1.0

1.3

1.7

0.25

0.3

0.6

0.7

1.1

1.0

1.2

1.5

0.21

0.25

0.50

1.0

1.2

1.4

Vdc

Threshold Voltage

Positive–Going VT+ 5.0

1.9

3.4

5.2

3.5

7.0

10.6

1.8

3.3

5.2

2.7

5.3

8.0

3.4

6.9

10.5

1.7

3.2

5.2

3.4

6.9

10.5

Vdc

Negative–Going VT– 5.0

1.6

3.0

4.5

3.3

6.7

9.7

1.6

3.0

4.6

2.1

4.6

6.9

3.2

6.7

9.8

1.5

3.0

4.7

3.2

6.7

9.9

Vdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25

6. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

7. VH = VT+ – VT– (But maximum variation of VH is specified as less than VT + max – VT – min).

MC14584B

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25

Characteristic Symbol VDD

Vdc Min Typ (8.) Max Unit

Output Rise T ime tTLH 5.0

—

100

200

100

Output Fall T ime tTHL 5.0

—

100

200

100

Propagation Delay T ime tPLH, tPHL 5.0

—

125

250

100

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14584B

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Figure 1. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR

VDD

INPUT CL

VSS

OUTPUT

ns VDD

VSS

VOH

VOL

90%

50%

10%

90%

50%

10%

tPLH

tPHL

OUTPUT

INPUT

tftr

VDD

VT+

VT–

VSS

VDD

VSS

Vout

Vin

VHVHVDD

VT+

VT–

VSS

VDD

VSS

Vout

Vin

VDD

0VDD

VT+

VT–

0VH

Vin, INPUT VOLTAGE (Vdc)

Vout, OUTPUT VOLTAGE (Vdc)

Figure 2. Typical Schmitt Trigger Applications

(b) A Schmitt trigger offers maximum noise immunity

in gate applications.

(a) Schmitt Triggers will square up inputs with slow

rise and fall times.

Figure 3. Typical Transfer Characteristics

Vin Vout

MC14584B

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PACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

14 8

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 18.80

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

M––– 10 ––– 10

N0.015 0.039 0.38 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

HG DK

SEATING

PLANE

–T–

14 PL

0.13 (0.005)

J0.290 0.310 7.37 7.87

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A–

–B–

P7 PL

14 8

71 M

0.25 (0.010) B M

0.25 (0.010) A S

–T–

RX 45

SEATING

PLANE D14 PL K

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

____

MC14584B

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PACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C––– 1.20 ––– 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS. MOLD

FLASH OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT

EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE –W–.

____

U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L–U–

SEATING

PLANE

0.10 (0.004)

–T–

ÇÇÇ

SECTION N–N

DETAIL E

JJ1

ÉÉ

DETAIL E

–W–

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

–V–

14X REFK

MC14584B

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PACKAGE DIMENSIONS

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 965–01

ISSUE O

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

––– 1.42 ––– 0.056

LEQ1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION A T MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

14 8

VIEW P

DETAIL P

0.50

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MC14584B/D

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