7
SCDCT2542 Rev G
69 62 RT FLAG
Remote terminal flag - Input signal used to control the terminal flag bit in the status
register. If LOW when the status word is updated, the terminal flag bit would be set; if
HIGH, it would be cleared. Normally connected to RTFAIL; (pin 28, Plug-In Pkg); (pin
67, Flat Pkg).
70 60 TEST 1 Factory test point - DO NOT USE. (See note 6).
71 58 BUSY Subsystem busy - Input from the subsystem used to control the busy bit in the status
register. If LOW when the status word is updated, the busy bit will be set; if HIGH, it will
be cleared. If the busy bit is set in the status register, no data will be requested from the
subsystem in response to a transmit command. On receive commands, data will still be
transferred to subsystem.
72 56 SS FLAG
Subsystem flag - Input from the subsystem used to control the subsystem flag bit in the
status register. If LOW when the status word is updated, the subsystem flag will be set; if
HIGH, it will be cleared.
73 54 MESS ERR
Message error - Output signal that goes LOW and stays low whenever there is a format or
word error with the received message over the 1553 data bus. Cleared by the next NBGT.
74 52 RXDATAIN A Input from the HIGH side of the primary side of the coupling transformer that contacts to
the A channel of the 1553 bus.
75 50 GND A Power supply return connection for the A channel transceiver.
76 48 N/C No connection. (See note 7).
77 46 TXDATAOUT A LOW output to the primary side of the coupling transformer that connects to the A
channel of the 1553 bus.
78 44 STATEN Status word enable - LOW level active output signal present when the status word is
enabled on the parallel data bus.
NOTES:
1. When INCMD is LOW during the DTSTR immediately following NBGT, A0 through A4 are valid and equal to WC0
through WC4 of the received command word. The remaining time while INCMD is LOW and A5 through A9 are not
all zeros or ones (i.e. MODE), A0 through A4 are equal to the last current word count plus one. When INCMD is HIGH
and A5 through A9 are not MODE, A0 through A4 represent the current word counter. If A5 through A9 are equal to
MODE, A0 through A4 are equal to WC0 through WC4 of the received command word, independent of the state of
INCMD.
2. Pulse width is typically 125 ns.
3. Pin 31 for Plug-In Pkg, and pin 61 for Flat Pkg - (TEST 2) factory test point output: This pin provides the output of the
device BIT comparison output. It indicates the loop test results for every word transmitted by the device. A test can be
performed by actuating the RTU to transmit while the test fixture opens the receiver lines to force an error condition.
A logic 1 (high) indicates the loop test passed. Normally this pin is left open. For Plug-In Pkg and Flat Pkg TEST 2 is
not implemented and should be left open.
4. Pulse width is typically 375 ns.
5. Pin 67 for Plug-In Pkg, and pin 66 for Flat Pkg - BUF ENA: This pin is typically tied to DTACK, causing the device
to drive the shared data bus only while DTACK is active. If desired BUF ENA can be gounded. The data will remain
latched on the data bus pins for 19 µs from DTSRB and 4 µs for the last word of a message as the devices status word
or BIT word is transferred to the BC (STATEN or BITEN low). Once the STATUS or BIT word transfer is complete,
the data bus will automatically again contain the last data word. The device will automatically switch the direction of
the internal buffers during a transmit operation.
6. Pin 70 for Plug-In Pkg, and pin 60 for Flat Pkg - (TEST 1) factory test point: This test allows the user to force the active
channel to transmit indefinitely, in order to test the built-in watchdog timer feature of the device. When this pin is
grounded and the active channel is stimulated with a valid transmit command, the device will respond with a status
word and contiguous data (last data word loaded or STATUS WORD if none is loaded) until the built-in timeout
occurs. Normally this pin is left open or an optional pull-up can be used. For Plug-In Pkg and Flat Pkg (TEST 1) is not
implemented and should be left open.
7. For Flat Pkg, pins 1, 41, 42, and 82 are no connections.
TERMINAL CONNECTIONS AND PIN FUNCTIONS (con’t)
Plug-In
Pkg
Flat
Pkg Function Description