14-Bit, 500 kSPS
PulSAR ADC in MSOP
AD7946
Rev. A
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FEATURES
14-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.4 LSB typical, ±1 LSB maximum (±0.0061% of FSR)
SINAD: 85 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Pseudo differential analog input range
0 V to REF with REF up to VDD
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface, SPI/QSPI/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
3.3 mW @ 5 V/100 kSPS
3.3 μW @ 5 V/100 SPS
Standby current: 1 nA
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin compatible with the 16-bit AD7686
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
APPLICATION DIAGRAM
AD7946
REF
GND
VDD
IN+
IN–
VIO
SDI
SCK
SDO
CNV
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
0.5
V
TO 5V 5
V
0V TO REF
04656-001
Figure 1.
GENERAL DESCRIPTION
The AD7946 is a 14-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 14-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to REF with respect
to a ground sense IN−. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus, or it provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7946 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC
Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver
14-Bit AD7940 AD79421AD79461
16-Bit AD7680 AD76851AD76861AD79801ADA4941
AD7683 AD76871AD76881AD79831ADA4841
AD7684 AD7694 AD76931
18-Bit AD76911AD76901AD79821ADA4941
AD79841ADA4841
1 Pin-for-pin compatible.
AD7946
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Application Diagram........................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Ter mi no log y .................................................................................... 11
Theory of Operation ...................................................................... 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Driver Amplifier Choice............................................................ 14
Voltage Reference Input ............................................................ 14
Power Supply............................................................................... 15
Supplying the ADC from the Reference.................................. 15
Single-Supply Application......................................................... 15
Digital Interface.......................................................................... 16
CS MODE 3-Wire, No BUSY Indicator .................................. 17
CS Mode 3-Wire with BUSY Indicator ................................... 18
CS Mode 4-Wire, No BUSY Indicator..................................... 19
CS Mode 4-Wire with BUSY Indicator ................................... 20
Chain Mode, No BUSY Indicator ............................................ 21
Chain Mode with BUSY Indicator........................................... 22
Application Guidelines .................................................................. 23
Layout .......................................................................................... 23
Evaluating the AD7946’s Performance.................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
12/07—Rev. 0 to Rev. A
QFN Package Available......................................................Universal
Changes to Table 1............................................................................ 1
Changes to Table 5............................................................................ 6
Changes to Ordering Guide .......................................................... 24
7/05—Revision 0: Initial Version
AD7946
Rev. A | Page 3 of 24
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 REF V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 V
IN− −0.1 0.1 V
Analog Input CMRR fIN = 200 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 14 Bits
Differential Linearity Error −0.7 ±0.3 +0.7 LSB1
Integral Linearity Error −1 ±0.4 +1 LSB
Transition Noise REF = VDD = 5 V 0.33 LSB
Gain Error2, TMIN to TMAX ±0.3 ±6 LSB
Gain Error Temperature Drift ±1 ppm/°C
Offset Error2, TMIN to TMAX ±0.3 ±6 LSB
Offset Temperature Drift ±1 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.1 LSB
THROUGHPUT
Conversion Rate 0 500 kSPS
Transient Response Full-scale step 400 ns
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, REF = 5 V 84.5 85 dB3
f
IN = 20 kHz, REF = 2.5 V 84 dB
Spurious-Free Dynamic Range fIN = 20 kHz −100 dB
Total Harmonic Distortion fIN = 20 kHz −100 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, REF = 5 V 84.5 85 dB
f
IN = 20 kHz, REF = 5 V, −60 dB input 25 dB
Intermodulation Distortion4 100 dB
1 LSB means least significant bit. With the 5 V input range, one LSB is 305.2 μV.
2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale.
AD7946
Rev. A | Page 4 of 24
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 500 kSPS, REF = 5 V 100 μA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 9 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
VIL −0.3 0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA
DIGITAL OUTPUTS
Data Format Serial 14-bits straight binary
Pipeline Delay Conversion results available immediately
after completed conversion
VOL ISINK = +500 μA 0.4 V
VOH ISOURCE = −500 μA VIO − 0.3 V
POWER SUPPLIES
VDD Specified performance 4.5 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current1, 2VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5 V, 100 SPS throughput 3.3 μW
VDD = 5 V, 100 kSPS throughput 3.3 3.8 mW
VDD = 5 V, 500 kSPS throughput 19 mW
TEMPERATURE RANGE3
Specified Performance TMIN to TMAX −40 +85 °C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended the temperature range.
AD7946
Rev. A | Page 5 of 24
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 1.6 μs
Acquisition Time tACQ 400 ns
Time Between Conversions tCYC 2 μs
CNV Pulse Width (CS Mode) tCNVH 10 ns
SCK Period (CS Mode) tSCK 15 ns
SCK Period (Chain Mode) tSCK
VIO Above 4.5 V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns
VIO Above 2.3 V 20 ns
SCK Low Time tSCKL 7 ns
SCK High Time tSCKH 7 ns
SCK Falling Edge to Data Remains Valid tHSDO 5 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 4.5 V 14 ns
VIO Above 3 V 15 ns
VIO Above 2.7 V 16 ns
VIO Above 2.3 V 17 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN
VIO Above 4.5 V 15 ns
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 3 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns
SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI
VIO Above 4.5 V 15 ns
VIO Above 2.3 V 26 ns
AD7946
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+1, IN−1GND − 0.3 V to VDD + 0.3 V or
±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
10-Lead MSOP 200°C/W
10-Lead QFN 48.7°C/W
θJC Thermal Impedance
10-Lead MSOP 44°C/W
10-Lead QFN 2.96°C/W
Lead Temperature
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
04656-002
500µA I
OL
500µA I
OH
1.4
V
TO
SDO C
L
50pF
Figure 2. Load Circuit for Digital Interface Timing
04656-003
30% VIO
70% OVDD
2V or VIO – 0.5V
1
0.8V or 0.5V
2
0.8V or 0.5V
2
2V or OVDD – 0.5V
1
t
DELAY
t
DELAY
NOTES
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Levels for Timing
AD7946
Rev. A | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04656-004
REF
VDD
IN+
IN–
GND
VIO
SDI
SCK
SDO
CNV
1
2
3
4
5
10
9
8
7
6
AD7946
TOP VIEW
(Not to Scale)
Figure 4. 10-Lead MSOP Pin Configuration
04656-005
REF
VDD
IN+
IN–
GND
VIO
SDI
SCK
SDO
CNV
AD7946
TOP VIEW
(Not to Scale)
1
2
3
4
5
10
9
8
7
6
Figure 5. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1Description
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD, and is referred to the GND pin. This pin
should be decoupled closely to the pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI
Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−,
is 0 V to REF.
4 IN− AI Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode,
the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the
ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete,
the BUSY indicator feature is enabled.
10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
1 AI = analog input, DI = digital input, DO = digital output, and P = power.
AD7946
Rev. A | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL (LSB)
04656-006
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0 4096 8192 12288 16384
POSITIVE INL = +0.17LSB
NEGATIVE INL = –0.26LSB
Figure 6. Integral Nonlinearity vs. Code
04656-046
0
50000
100000
150000
200000
250000
300000
2009 200A 200B 200C 200D 200E 200F
CODE IN HEX
COUNTS
000 0
261120
00
VDD = REF = 5V
Figure 7. Histogram of a DC Input at the Code Center
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
04656-008
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
0 20 40 60 80 100 120 140 160 180 200 220 240
8192 POINT FFT
VDD = REF = 5V
f
S = 500kSPS
f
IN = 20.14kHz
SNR = 85.3dB
THD = –105.2dB
SECOND HARMONIC = –106dB
THIRD HARMONIC = –110dB
Figure 8. FFT Plot
CODE
DNL (LSB)
04656-009
POSITIVE DNL = +0.20LSB
NEGATIVE DNL = –0.13LSB
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0 4096 8192 12288 16384
Figure 9. Differential Nonlinearity vs. Code
04656-047
0
25000
50000
75000
100000
125000
150000
2059 205A 205B 205C 205D 205E
CODE IN HEX
COUNTS
0
0
131592 129528
00
VDD = REF = 5V
Figure 10. Histogram of a DC Input at the Code Transition
INPUT LEVEL (dB)
SNR REFERENCE TO FULL SCALE (dB)
04656-011
80
82
84
86
88
90
–10–8–6–4–2
Figure 11. SNR vs. Input Level
AD7946
Rev. A | Page 9 of 24
REFERENCE VOLTAGE (V)
SNR, SINAD (dB)
90.0
87.5
85.0
82.5
80.0
04656-012
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.513.0
13.5
14.0
14.5
15.0
ENOB (Bits)
SNR
SINAD
ENOB
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
TEMPERATURE (°C)
SNR (dB)
04656-013
80.0
82.5
85.0
87.5
90.0
–55 –35 –15 5 25 45 65 85 105 125
REF = 5V
Figure 13. SNR vs. Temperature
FREQUENCY (kHz)
SINAD (dB)
04656-014
70
75
80
85
90
95
100
0 50 100 150 200
REF = 5V, –10dB
REF = 5V, –1dB
Figure 14. SINAD vs. Frequency
SFDR
THD
REFERENCE VOLTAGE (V)
THD, SFDR (dB)
04656-015
–120
–115
–110
–105
–100
–95
–90
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
Figure 15. THD, SFDR vs. Reference Voltage
TEMPERATURE (°C)
THD (dB)
04656-016
–130
–120
–110
–100
–
90
–55 –35 –15 5 25 45 65 85 105 125
REF = 5V
Figure 16. THD vs. Temperature
FREQUENCY (kHz)
THD (dB)
04656-017
–120
–110
–100
–90
–80
–70
–
60
0 50 100 150 200
REF = 5V, –1dB
REF = 5V, –10dB
Figure 17. THD vs. Frequency
AD7946
Rev. A | Page 10 of 24
04656-048
0
250
500
750
1000
4.50 4.75 5.00 5.25 5.50
SUPPLY (V)
OPER
A
TING CURRENT (µA)
VDD
VIO
f
S
= 100kSPS
Figure 18. Operating Current vs. Supply
04656-050
0
250
500
750
1000
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
POWER-DOWN CURRENT (nA)
VDD+VIO
Figure 19. Power-Down Current vs. Temperature
04656-049
0
250
500
750
1000
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
OPER
A
TING CURRENT (µA)
VDD = 5V
VIO
f
S
= 100kSPS
Figure 20. Operating Current vs. Temperature
TEMPERATURE (°C)
OFFSET AND GAIN ERROR (LSB)
04656-021
3
2
1
0
–1
–2
–3
–55 –35 –15 5 25 45 65 85 105 125
OFFSET ERROR
GAIN ERROR
Figure 21. Offset and Gain Error vs. Temperature
04656-022
SDO CAPACITIVE LOAD (pF)
1200 20406080100
T
DSDO
DELAY (ns)
25
20
15
10
5
0
VDD = 5V, 85°C
VDD = 5V, 25°C
Figure 22. tDSDO Delay vs. Capacitance Load and Supply
AD7946
Rev. A | Page 11 of 24
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (Figure 24).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (152.6 μV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
Aperture delay is the measurement of the acquisition perform-
ance and is the time between the rising edge of the CNV input
and when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accu-
rately acquire its input after a full-scale step function is applied.
AD7946
Rev. A | Page 12 of 24
THEORY OF OPERATION
SW+MSB
4096C
4096C
IN+
LSB
COMP CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C 2C C C8192C
8192C
SW–MSB LSB
4C 2C C C
04656-023
Figure 23. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7946 is a fast, low power, single-supply, precise 14-bit
ADC using a successive approximation architecture.
The AD7946 can convert 500,000 samples per second (500 kSPS)
and powers down between conversions. When operating at
100 SPS, for example, it consumes 3.3 μW typically, ideal for
battery-powered applications.
The AD7946 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7946 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
It is pin-for-pin compatible with the 16-bit ADC AD7686.
CONVERTER OPERATION
The AD7946 is a successive approximation ADC based on a
charge redistribution DAC. Figure 23 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, the terminals of the array that are
tied to the comparator’s input are connected to GND via SW+
and SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (REF/2, REF/4 … REF/16,384).
The control logic toggles these switches, starting with the MSB,
in order to bring the comparator back into a balanced condition.
After completing this process, the part returns to the acquisition
phase, and the control logic generates the ADC output code and
a BUSY signal indicator.
Because the AD7946 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Transfer Functions
The ideal transfer characteristic for the AD7946 is shown in
Figure 24 and Table 7.
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE (Straight Binary)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
04656-024
Figure 24. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
Analog Input
REF = 5 V Digital Output Code Hexa
FSR − 1 LSB 4.999695 V 3FFF1
Midscale + 1 LSB 2.500305 V 2001
Midscale 2.5 V 2000
Midscale − 1 LSB 2.499695 V 1FFF
−FSR + 1 LSB 305.2 μV 0001
−FSR 0 V 00002
1 This is also the code for an overranged analog input (VIN+ − VIN− above REF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
AD7946
Rev. A | Page 13 of 24
TYPICAL CONNECTION DIAGRAM
Figure 25 shows an example of the recommended connection diagram for the AD7946 when multiple supplies are available.
AD7946
REF
GND
VDD
IN–
IN+
VIO
SDI
SCK
SDO
CNV
3- OR 4-WIRE INTERFACE
(NOTE 5)
100nF
100nF
5V
10µF
(NOTE 2)
V+
V+
V–
1.8V TO VDD
REF
0V TO REF
33Ω
2.7nF
04656-025
NOTES
1. SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2
.
C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3
. SEE DRIVE
R
AMPLIFIER CHOICE SECTION.
4
. OPTION
A
L FILTER. SEE ANALOG INPUT SECTION.
5. SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
(NOTE 1)
(ADA4841
OR NOTE 3)
(NOTE 4)
Figure 25. Typical Application Diagram with Multiple Supplies
ANALOG INPUT
Figure 26 shows an equivalent circuit of the input structure of
the AD7946.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to begin to forward-
bias and start conducting current. These diodes can handle a
maximum forward-biased current of 130 mA. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, an input
buffer with a short-circuit current limitation can be used to
protect the part.
C
IN
R
IN
D1
D2
C
PIN
IN+
OR IN–
GND
VDD
04656-026
Figure 26. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 27, which represents the typical
CMRR over frequency. For instance, by using IN− to sense a
remote signal ground, ground potential differences between the
sensor and the local ADC ground are eliminated.
FREQUENCY (kHz)
CMRR (dB)
04656-027
50
40
60
70
101 100 1k 10k
VDD = 5V
Figure 27. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series connec-
tion of RIN and CIN. CPIN is primarily the pin capacitance. RIN is
typically 600 Ω and is a lumped component made up of some
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, when the switches are opened, the
input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter, which reduces undesirable aliasing effects and
limits the noise.
When the source impedance of the driving circuit is low, the
AD7946 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
AD7946
Rev. A | Page 14 of 24
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 28.
FREQUENCY (kHz)
THD (dB)
04656-028
–105
–110
–100
–90
–95
–85
–
80
0 255075
100
R
S
= 33Ω
R
S
= 50Ω
R
S
=100Ω
R
S
= 250Ω
Figure 28. THD vs. Analog Input Frequency and Source Resistance
DRIVER AMPLIFIER CHOICE
Although the AD7946 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7946. Note that the AD7946
has a noise much lower than most of the other 14-bit
ADCs and, therefore, can be driven by a noisier amplifier
to meet a given system noise specification. The noise
coming from the amplifier is filtered by the AD7946 analog
input circuit 1-pole, low-pass filter made by RIN and CIN or
by the external filter, if one is used.
• For ac applications, the driver should have a THD perform-
ance commensurate with the AD7946. Figure 17 shows the
THD vs. frequency that the driver should exceed.
• For multichannel multiplexed applications, the driver
amplifier and the AD7946 analog input circuit must settle a
full-scale step onto the capacitor array at a 14-bit level
(0.006%). In the amplifier’s data sheet, settling at 0.1% to
0.01% is more commonly specified. This could differ
significantly from the settling time at a 14-bit level and
should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841 Very low noise, small and low power
AD8021 Very low noise and high frequency
AD8655 5 V single-supply, low noise, and low power
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single-supply, low power
AD8519 Small, low power, and low frequency
AD8031 High frequency and low power
VOLTAGE REFERENCE INPUT
The AD7946 voltage reference input REF has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8603, a
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
AD7946
Rev. A | Page 15 of 24
POWER SUPPLY
The AD7946 is specified at 4.5 V to 5.5 V. It uses two power
supply pins: a core supply VDD and a digital input/output
interface supply VIO. VIO allows direct interface with any
logic between 1.8 V and VDD. To reduce the supplies needed,
the VIO and VDD can be tied together. The AD7946 is
independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 29,
which represents PSRR over frequency.
FREQUENCY (kHz)
PSRR (dB)
04656-029
50
40
30
60
90
80
70
101 100 1k 10k
VDD = 5V
Figure 29. PSRR vs. Frequency
The AD7946 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 30. This makes the part
ideal for low sampling rate (even a few Hz) and low battery-
powered applications.
04656-051
0.001
0.1
1
0.01
10
100
1000
10 100 1k 10k 100k 1M
SAMPLING RATE (SPS)
OPER
A
TING CURRENT (µA)
VIO
VDD = 5V
Figure 30. Operating Currents vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7946, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 31. The reference line can be driven by one of
the following:
• The system power supply directly.
• A reference voltage with enough current output capability,
such as the ADR43x.
• A reference buffer, such as the AD8031 or AD8603,
which can also filter the system power supply, as shown
in Figure 31.
AD8603
AD7946
VIOREF
(NOTE 1)
VDD
10µF 1µF
10kΩ
1kΩ
47kΩ
5V
5V
1µF
04656-031
NOTES
1. OPTIONAL REFERENCE BUFFER AND FILTER
Figure 31. Example of Application Circuit
SINGLE-SUPPLY APPLICATION
Figure 32 shows a typical 14-bit single-supply application. There
are different challenges to doing a single-supply, high resolution
design, and the ADA4841 addresses these nicely. The combina-
tion of low noise, low power, wide input range, rail-to-rail output,
and high speed make the ADA4841 a perfect driver solution for
low power, single-supply 14-bit ADCs, such as the AD7946. In a
single-supply system, one of the main challenges is to use the
amplifier in buffer mode to have the lowest output noise and
still preserve linearity compatible with the ADC. Rail-to-rail
input amplifiers usually have higher noise than the ADA4841
and cannot be used on their entire input range in buffer mode
because of the nonlinear region around the crossover point of
their input stage. The ADA4841, which has no crossover region
but has a wide linear input range from ground to 1 V below
positive rail, solves this issue, as shown in Figure 32, where it
can accept the 0 V to 4.096 V input range with a supply as low
as 5.2 V. This supply allows using a small, low dropout, low
temperature drift ADR364 reference voltage. Note that, like any
rail-to-rail output amplifier at the low end of its output range
close to ground, the ADA4841 can exhibit some nonlinearity on
a small region of approximately 25 mV from ground. The
ADA4841 drives a 1-pole, low-pass filter. This filter limits the
already very low noise contribution from the amplifier to the
AD7946.
AD7946
Rev. A | Page 16 of 24
AD7946
REF
GND
VDD
IN–
IN+
VIO
SDI
SCK
SDO
CNV
100nF
10µF
ADR364
33Ω
2.7nF
0V TO 4.096V
ADA4841
100nF
>5.2
V
100nF
04656-052
Figure 32. Example of a Single-Supply Application Circuit
DIGITAL INTERFACE
Although the AD7946 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7946, when in CS mode, is compatible with SPI, QSPI™,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals mini-
mizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
The AD7946, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The operating mode depends on the SDI level when the CNV
rising edge occurs. CS mode is selected if SDI is high, and chain
mode is selected if SDI is low. The SDI hold time is such that
when SDI and CNV are connected, the chain mode is always
selected.
In either mode, the AD7946 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
BUSY indicator feature is enabled
• In CS mode, if CNV or SDI is low when the ADC
conversion ends (see Figure 36 and Figure 40).
• In chain mode, if SCK is high during the CNV rising edge
(see Figure 44).
AD7946
Rev. A | Page 17 of 24
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 33 and the corresponding timing is given in
Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7946
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDOSDI DATA IN
CLK
CONVERT
V
IO
DIGITAL HOST
AD7946
04656-032
Figure 33. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDO D13 D12 D11 D1 D0
t
DIS
SCK
123 121314
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
04656-033
Figure 34. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
AD7946
Rev. A | Page 18 of 24
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 35, and the
corresponding timing is given in Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7946 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
If multiple AD7946s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
DATA IN
IRQ
CLK
CONVERT
VIO DIGITAL HOST
04656-034
47kΩ
CNV
SCK
SDOSDI
V
IO
AD7946
Figure 35. CS Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDO D13 D12 D1 D0
t
DIS
SCK 123 131415
t
SCK
t
SCKL
tSCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
tCONV
t
CYC
t
CNVH
tACQ
ACQUISITION
SDI = 1
04656-035
Figure 36. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
AD7946
Rev. A | Page 19 of 24
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7946s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7946s is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7946 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by subse-
quent SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 14th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7946 can be read.
DATA IN
CLK
CS1
CONVERT
CS2
DIGITAL HOST
04656-036
CNV
SCK
SDOSDI
AD7946
CNV
SCK
SDOSDI
AD7946
Figure 37. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
SDO D13 D12 D11 D1 D0
t
DIS
SCK 123 262728
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI(CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
12 13
t
SCK
t
SCKL
t
SCKH
D0 D13 D12
15 1614
SDI(CS2)
04656-037
Figure 38. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
AD7946
Rev. A | Page 20 of 24
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7946 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15th SCK falling edge or SDI going high, whichever is earlier, the
SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
VIO DIGITAL HOST
04656-038
47kΩ
CNV
SCK
SDOSDI
AD7946
CS1
Figure 39. CS Mode 4-Wire with BUSY Indicator Connection Diagram
SDO D13 D12 D1 D0
t
DIS
SCK 123 131415
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
04656-039
Figure 40. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
AD7946
Rev. A | Page 21 of 24
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7946s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7946s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO, and the AD7946 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 14 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. The maximum conver-
sion rate may be reduced due to the total readback time. For
instance, with a 3 ns digital host setup time and 3 V interface,
up to four AD7946s running at a conversion rate of 360 kSPS
can be daisy-chained on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
04656-040
CNV
SCK
SDOSDI
AD7946
B
CNV
SCK
SDOSDI
AD7946
A
Figure 41. Chain Mode, No BUSY Indicator Connection Diagram
SDOA = SDIBDA13 DA12 DA11
SCK 1 2 3 262728
tSSDISCK
tHSDISCK
tEN
CONVERSIONACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
12 13
tSCK
tSCKL
tSCKH
DA0
15 1614
SDIA = 0
SDOBDB13 DB12 DB11 DA1DB1D
B0D
A13 DA12
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
04656-041
Figure 42. Chain Mode, No BUSY Indicator Serial Interface Timing
AD7946
Rev. A | Page 22 of 24
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7946s on a
3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7946s is shown
in Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
Figure 43) SDO is driven high. This transition on SDO can
be used as a BUSY indicator to trigger the data readback
controlled by the digital host. The AD7946 then enters the
acquisition phase and powers down. The data bits stored in
the internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. For instance, with a
3 ns digital host setup time and 3 V interface, up to four AD7946s
running at a conversion rate of 360 kSPS can be daisy-chained
to a single 3-wire port.
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
04656-042
CNV
SCK
SDOSDI
AD7946
C
CNV
SCK
SDOSDI
AD7946
A
CNV
SCK
SDOSDI
AD7946
B
Figure 43. Chain Mode with BUSY Indicator Connection Diagram
SDO
A
= SDI
B
D
A
13 D
A
12 D
A
11
SCK 123 31 41 42
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV = SDI
A
D
A
1
413
t
SCK
t
SCKH
t
SCKL
D
A
0
15 3014
SDO
B
= SDI
C
D
B
13 D
B
12 D
B
11 D
A
1D
B
1D
B
0D
A
13 D
A
12
43
t
SSDISCK
t
HSDISCK
t
HSDO
t
DSDO
SDO
C
D
C
13 D
C
12 D
C
11 D
A
1D
A
0D
C
1D
C
0D
A
12
17 27 2816 29
D
B
1D
B
0D
A
13D
B
13 D
B
12
t
DSDOSDI
t
SSCKCNV
t
HSCKCNV
0
4656-043
D
A
0
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
Figure 44. Chain Mode with BUSY Indicator Serial Interface Timing
AD7946
Rev. A | Page 23 of 24
APPLICATION GUIDELINES
LAYOUT
The printed circuit board that houses the AD7946 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7946, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7946 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7946s.
The AD7946 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
Finally, the power supplies VDD and VIO of the AD7946
should be decoupled with ceramic capacitors (typically 100 nF)
placed close to the AD7946 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
An example of layout following these rules is shown in
Figure 45 and Figure 46.
EVALUATING THE AD7946’S PERFORMANCE
Other recommended layouts for the AD7946 are outlined
in the documentation of the evaluation board for the AD7946
(EVAL-AD7946CB). The evaluation board package includes a
fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
04656-044
Figure 45. Example of Layout of the AD7946 (Top Layer)
04656-045
Figure 46. Example of Layout of the AD7946 (Bottom Layer)
AD7946
Rev. A | Page 24 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.23
0.08
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
PIN 1
COPLANARITY
0.10
3.10
3.00
2.90
3.10
3.00
2.90
5.15
4.90
4.65
Figure 47.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
101207-B
TOP VIEW
10
1
6
5
0.30
0.23
0.18
*EXPOSED
PAD
(BOTTOM VIEW)
PIN 1 INDEX
AREA
3.00
BSC SQ
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.05 MAX
0.02 NOM
0.80 MAX
0.55 NOM
1.74
1.64
1.49
2.48
2.38
2.23
0.50
0.40
0.30
0.50 BSC
PIN 1
INDICATOR
(R 0.19)
*PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES
Figure 48. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Ordering Quantity Branding
AD7946BRM −40°C to +85°C 10-Lead MSOP RM-10 Tube, 50 C1E
AD7946BRM-RL7 −40°C to +85°C 10-Lead MSOP RM-10 Reel, 1,000 C1E
AD7946BRMZ1−40°C to +85°C 10-Lead MSOP RM-10 Tube, 50 C4X
AD7946BRMZRL71−40°C to +85°C 10-Lead MSOP RM-10 Reel, 1,000 C4X
AD7946BCPZRL71−40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 1,000 C4X
AD7946BCPZRL1−40°C to +85°C 10-Lead QFN (LFCSP_WD) CP-10-9 Reel, 5,000 C4X
EVAL-AD7946CBZ1, 2 Evaluation Board
EVAL-CONTROL BRD3Z1, 3 Evaluation Board
T
1 Z = RoHS Compliant Part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3Z for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designator.
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04656-0-12/07(A)
TTT
