LT3942
1
Rev. 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
36V, 2A Synchronous
Buck-Boost Converter and
LED Driver
The LT
®
3942 is a monolithic 4-switch synchronous buck-
boost LED driver. The driver can regulate the LED string
current up to 34V with input voltages above, below, or
equal to the output voltage. The proprietary peak-buck
peak-boost current mode control scheme allows adjust-
able and synchronizable 300kHz to 2MHz fixed frequency
operation, or internal 25% triangle spread spectrum oper-
ation for low EMI. With 3V to 36V input, 0V to 36V output
and seamless low-noise transitions between operation
regions, the LT3942 is ideal for LED driver applications
in automotive, industrial and battery-powered systems.
The LT3942 provides LED current regulation with up to
128:1 internal and 5000:1 external PWM dimming using
an optional high-side PMOS switch. The CTRL pin pro-
vides flexible 20:1 analog dimming with ±2.5% LED cur-
rent regulation at 100mV full scale. Robust fault protec-
tion detects an open or short LED condition, during which
the LT3942 retries, latches off, or keeps running.
93% Efficient, 12W (12V, 1A) 2MHz Buck-Boost LED Driver
Efficiency vs VIN
n 4-Switch Single Inductor Architecture Allows VIN
Above, Below or Equal to VOUT
n Proprietary Peak-Buck Peak-Boost Current Mode
n 3V to 36V Input Voltage Range
n 0V to 36V Output Voltage Range
n ±1.5% Output Voltage Regulation
n ±3% LED Current Regulation
n 5000:1 External and 128:1 Internal PWM Dimming
n Rail-to-Rail LED Current Sense and Monitor Output
n Open and Short LED Protection with Fault Reporting
n 300kHz to 2MHz Fixed Switching Frequency with
External Frequency Synchronization
n Flicker-Free Spread Spectrum for Low EMI
n Available in 28-Lead QFN (4mm × 5mm)
APPLICATIONS
n General Purpose LED Driver
n Automotive and Industrial Lighting
n Voltage Regulator with Accurate Current Limit All registered trademarks and trademarks are the property of their respective owners.
14.3k
2MHz
1k
22nF
2.2nF
VIN
8V TO 36V
1A
3942 TA01a
ANALOG DIM
PWM DIM
12V
1A
LED
VLED
LT3942
PVOUT
FB
ISP
ISN
PWMTG
PVIN
VIN
EN/UVLO
OVLO
INTVCC
FAULT
VREF
CTRL
PWM
RP
GND
1M
69.8k
1M
34.8k
499k
115k
1µF 100k
0.22µF
10µF10µF
100mΩ
0.1µF 0.1µF
3.3µH
BST1 SW1 SW2 BST2
VC
SS
RT
SYNC/SPRD
ISMON
V
LED
= 12V
I
LED
= 1A
BOOST
BUCK
INPUT VOLTAGE (V)
0
5
10
15
20
25
30
35
40
70
75
80
85
90
95
100
EFFICIENCY (%)
3942 TA01b
LT3942
2
Rev. 0
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
PVIN, VIN, EN/UVLO ..................................................40V
PVOUT, ISP, ISN .........................................................40V
SW1, SW2 .................................................................40V
BST1, BST2 ............................................................... 45V
BST1−SW1, BST2−SW2, INTVCC ................................5V
OVLO, CTRL, FB, PWM, SYNC/SPRD, FA U LT ..............5V
ISP−ISN ...........................................................−1V to 1V
Operating Junction Temperature (Notes 2, 3)
LT3942E ............................................. −40˚C to 125˚C
LT3942J/LT3942H .............................. −40˚C to 150˚C
Storage Temperature Range ................... −65˚C to 150˚C
(Note 1)
9 10
TOP VIEW
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
PVIN
PVIN
VIN
INTVCC
EN/UVLO
OVLO
RP
PWM
PVOUT
PVOUT
PWMTG
SYNC/SPRD
RT
VC
FB
SS
SW1
SW1
BST1
BST2
SW2
SW2
VREF
CTRL
ISP
ISN
ISMON
FAULT
7
17
18
19
20
21
22
16
815
29
GND
ORDER INFORMATION
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input and Output
PVIN/VIN Operating Voltage Range l3 36 V
PVIN/VIN Quiescent Current VEN/UVLO = 0.3V
VEN/UVLO = 1.3V, Not Switching
0.9
2.6
2
4
µA
mA
PVOUT Operating Voltage Range l0 36 V
PVOUT Quiescent Current VEN/UVLO = 0.3V, PVOUT = 12V
VEN/UVLO = 1.3V, PVOUT = 12V, Not Switching
20
0.1
40
0.5
60
µA
µA
EN/UVLO Shutdown Threshold l0.3 0.6 0.9 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PVIN = VIN = 12V, VEN/UVLO = VIN unless otherwise noted.
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3942EUFD#PBF LT3942EUFD#TRPBF 3942 28-Lead (4mm x 5mm) Plastic QFN –40˚C to 125˚C
LT3942JUFD#PBF LT3942JUFD#TRPBF 3942 28-Lead (4mm x 5mm) Plastic QFN –40˚C to 150˚C
LT3942HUFD#PBF LT3942HUFD#TRPBF 3942 28-Lead (4mm x 5mm) Plastic QFN –40˚C to 150˚C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
LT3942
3
Rev. 0
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ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
EN/UVLO Enable Threshold Falling l1.196 1.220 1.244 V
EN/UVLO Enable Hysteresis 15 mV
EN/UVLO Hysteresis Current VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
VEN/UVLO = 1.3V
–0.1
2.2
–0.1
0
2.5
0
0.1
2.8
0.1
µA
µA
µA
OVLO Threshold Rising 1.196 1.220 1.244 V
OVLO Hysteresis 35 mV
Linear Regulators
INTVCC Regulation Voltage IINTVCC = 10mA 3.5 3.65 3.8 V
INTVCC Load Regulation IINTVCC = 0mA to 30mA 0.8 2 %
INTVCC Line Regulation IINTVCC = 10mA, VIN = 4V to 36V 0.1 0.5 %
INTVCC Current Limit VINTVCC = 3V 40 mA
INTVCC Dropout Voltage (VIN – INTVCC) IINTVCC = 10mA, VIN = 3V 120 200 mV
INTVCC UVLO Threshold Falling 2.27 2.37 2.47 V
INTVCC UVLO Hysteresis 120 mV
VREF Regulation Voltage IVREF = 100µA l1.97 2.00 2.03 V
VREF Load Regulation IVREF = 0mA to 1mA 0.5 1 %
VREF Line Regulation IVREF = 100µA, VIN = 4V to 36V 0.1 0.5 %
VREF Current Limit VREF = 1.8V 2.5 mA
VREF UVLO Threshold Falling 1.78 1.84 1.90 V
VREF UVLO Hysteresis 45 mV
Current Regulation Loop
CTRL Pin Current VCTRL = 0.75V, Current Out of Pin 0 13 50 nA
CTRL Dim-Off Threshold Falling l190 200 210 mV
CTRL Dim-Off Hysteresis 25 mV
Full Scale LED Current Regulation V(ISP-ISN) VCTRL = 2V, VISP = 12V
VCTRL = 2V, VISP = 0V
l
l
97
97
100
100
103
103
mV
mV
1/2 LED Current Regulation V(ISP-ISN) VCTRL = 0.75V, VISP = 12V
VCTRL = 0.75V, VISP = 0V
l
l
47.5
47.5
50
50
52.5
52.5
mV
mV
1/20th LED Current Regulation V(ISP-ISN) VCTRL = 0.30V, VISP = 12V
VCTRL = 0.30V, VISP = 0V
l
l
3
3
5
5
7
7
mV
mV
ISP Pin Current VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
–0.1
23
–10
0
0.1
µA
µA
µA
ISN Pin Current VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V
–0.1
23
–10
0
0.1
µA
µA
µA
ISP/ISN Input Common Mode Range l0 36 V
ISP/ISN Low Side to High Side Switchover Voltage VISP = VISN 1.7 V
ISP/ISN High Side to Low Side Switchover Voltage VISP = VISN 1.6 V
LED Current Regulation Amplifier gm2000 µS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PVIN = VIN = 12V, VEN/UVLO = VIN unless otherwise noted.
LT3942
4
Rev. 0
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ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Voltage Regulation Loop
FB Pin Current FB in Regulation, Current Out of Pin 17 40 nA
FB Regulation Voltage VC = 1.2V l0.985 1.00 1.015 V
FB Line Regulation VIN = 3V to 36V 0.02 0.1 %
FB Load Regulation 0.02 0.1 %
FB Voltage Regulation Amplifier gm650 µS
VC Output Impedance 10 MΩ
VC Standby Leakage Current VC = 1.2V, PWM dimming off –20 0 20 nA
Power Switches
Maximum Switch Current Limit Peak-Buck Current Mode
Peak-Boost Current Mode
2.2
2.2
2.5
2.5
2.8
2.8
A
A
Switch A On-Resistance (From PVIN to SW1) ISW = 1A 150 mΩ
Switch B On-Resistance (From SW1 to GND) ISW = 1A 150 mΩ
Switch C On-Resistance (From SW2 to GND) ISW = 1A 150 mΩ
Switch D On-Resistance (From PVOUT to SW2) ISW = 1A 150 mΩ
Oscillator
Switching Frequency VSYNC/SPRD = 0V, RT = 14.3kΩ
VSYNC/SPRD = 0V, RT = 43.2kΩ
VSYNC/SPRD = 0V, RT = 178kΩ
l1900
925
275
2000
975
290
2100
1025
305
kHz
kHz
kHz
SYNC/SPRD Pin Current VSYNC/SPRD = 3.6V –0.1 0 0.1 µA
SYNC Frequency 300 2000 kHz
SYNC/SPRD Threshold Voltage 0.4 1.5 V
Highest Spread Spectrum Above Oscillator Frequency VSYNC/SPRD = 3.6V 19 22 25 %
Fault
FB Overvoltage Threshold (VFB) Rising l1.03 1.05 1.07 V
FB Overvoltage Hysteresis l20 25 30 mV
FB Open LED Threshold (VFB) Rising, V(ISP-ISN) = 0V l0.93 0.95 0.97 V
FB Open LED Hysteresis V(ISP-ISN) = 0V l40 50 60 mV
FB Short LED Threshold (VFB) Falling l0.23 0.25 0.27 V
FB Short LED Hysteresis l40 50 60 mV
ISP/ISN Over Current Threshold V(ISP-ISN) VISP = 12V 700 mV
ISP/ISN Open LED Threshold V(ISP-ISN) Falling, VFB = 1.0V 8 11 14 mV
ISP/ISN Open LED Hysteresis VFB = 1.0V 3 mV
FAULT Pull-Down Resistance 130 200 Ω
SS Hard Pull-Down Resistance 130 200 Ω
SS Pull-Up Current VFB = 0.8V, VSS = 0V 11 12.5 14 µA
SS Pull-Down Current VFB = 1.0V, VSS = 2V 1.1 1.25 1.4 µA
SS Fault Latch-Off Threshold 1.75 V
SS Fault Reset Threshold 0.2 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PVIN = VIN = 12V, VEN/UVLO = VIN unless otherwise noted.
LT3942
5
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3942E is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3942J and LT3942H are guaranteed over the –40°C to 150°C
operating junction temperature range.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Current Monitor
ISMON Voltage V(ISP-ISN) = 100mV, VISP = 12V/0V
V(ISP-ISN) = 10mV, VISP = 12V/0V
V(ISP-ISN) = 0mV, VISP = 12V/0V
1.22
0.32
0.22
1.25
0.35
0.25
1.28
0.38
0.28
V
V
V
PWM Dimming
External PWM Dimming Threshold Rising, RP = 10kΩ 1.3 1.4 1.5 V
External PWM Dimming Hysteresis 200 mV
Internal PWM Dimming Duty Cycle VPWM = 1V, RP ≥ 28.7kΩ
VPWM = 1.5V, RP ≥ 28.7kΩ
VPWM = 2V, RP ≥ 28.7kΩ
47
97
3
53
%
%
%
Switching Frequency to Internal PWM Dimming Frequency
Ratio
RP = 28.7kΩ
RP = 332kΩ
256
16384
Minimum VOUT for PWMTG to be On PWM Dimming On 3 4.0 V
PWMTG On Voltage V(VOUT-PWMTG) VOUT = 12V 4.6 5 5.4 V
PWMTG Off Voltage V(VOUT-PWMTG) VOUT = 12V –0.1 0 0.1 V
PWM to PWMTG Turn On Propagation Delay
PWM to PWMTG Turn Off Propagation Delay
CPWMTG = 3.3nF to VOUT, 50% to 50%
CPWMTG = 3.3nF to VOUT, 50% to 50%
130
120
ns
ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PVIN = VIN = 12V, VEN/UVLO = VIN unless otherwise noted.
Note 3: The LT3942 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
LT3942
6
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs LED Current
(Buck Region)
Efficiency vs LED Current
(Buck-Boost Region)
Efficiency vs LED Current
(Boost Region)
Switching Waveforms
(Buck Region)
Switching Waveforms
(Buck-Boost Region)
Switching Waveforms
(Boost Region)
LED Current vs
Combined PVIN/VIN
Combined PVIN/VIN Shutdown
Current
Combined PVIN/VIN Quiescent
Current
FRONT PAGE APPLICATION
V
IN
= 24V, V
LED
= 12V, f
SW
= 2MHz
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
40
50
60
70
80
90
100
EFFICIENCY (%)
3942 G01
FRONT PAGE APPLICATION
V
IN
= 12V, V
LED
= 12V, f
SW
= 2MHz
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
40
50
60
70
80
90
100
EFFICIENCY (%)
3942 G02
FRONT PAGE APPLICATION
V
IN
= 8V, V
LED
= 12V, f
SW
= 2MHz
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
40
50
60
70
80
90
100
EFFICIENCY (%)
3942 G03
500ns/DIV
VSW1
10V/DIV
VSW2
10V/DIV
IL
1A/DIV
3942 G04
FRONT PAGE APPLICATION
VIN = 24V, ILED = 1A
500ns/DIV
VSW1
10V/DIV
VSW2
10V/DIV
IL
1A/DIV
3942 G05
FRONT PAGE APPLICATION
VIN = 12V, ILED = 1A
500ns/DIV
VSW1
10V/DIV
VSW2
10V/DIV
IL
1A/DIV
3942 G06
FRONT PAGE APPLICATION
VIN = 8V, ILED = 1A
FRONT PAGE APPLICATION
V
IN
(V)
0
5
10
15
20
25
30
35
40
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
I
LED
(A)
3942 G07
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
0.5
1.0
1.5
2.0
2.5
3.0
I
Q
(µA)
3942 G08
VIN = 36V
VIN = 12V
VIN = 3V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.8
2.0
2.2
2.4
2.6
2.8
I
Q
(mA)
3942 G09
VIN = 36V
VIN = 12V
VIN = 3V
LT3942
7
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Voltage vs Temperature INTVCC Voltage vs VIN INTVCC UVLO Threshold
VREF Voltage vs Temperature VREF Voltage vs VIN VREF UVLO Threshold
EN/UVLO Enable Threshold EN/UVLO Hysteresis Current OVLO Threshold
I
INTVCC
= 30mA
I
INTVCC
= 0mA
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
3.50
3.55
3.60
3.65
3.70
3.75
3.80
V
INTVCC
(V)
3942 G10
I
INTVCC
= 10mA
V
IN
(V)
0
5
10
15
20
25
30
35
40
3.45
3.50
3.55
3.60
3.65
3.70
3.75
V
INTVCC
(V)
3942 G11
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
V
INTVCC
(V)
3942 G12
I
VREF
= 1mA
I
VREF
= 0mA
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.96
1.97
1.98
1.99
2.00
2.01
2.02
2.03
2.04
V
REF
(V)
3942 G13
I
VREF
= 100µA
V
IN
(V)
0
5
10
15
20
25
30
35
40
1.96
1.97
1.98
1.99
2.00
2.01
2.02
2.03
2.04
V
REF
(V)
3942 G14
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.70
1.75
1.80
1.85
1.90
1.95
2.00
V
REF
(V)
3942 G15
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.200
1.205
1.210
1.215
1.220
1.225
1.230
1.235
1.240
V
EN/UVLO
(V)
3942 G16
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
2.0
2.2
2.4
2.6
2.8
3.0
I
HYS
(µA)
3942 G17
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
V
OVLO
(V)
3942 G18
LT3942
8
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
CTRL Dim-Off Threshold V(ISP-ISN) Regulation vs VCTRL V(ISP-ISN) Regulation vs VISP
V(ISP-ISN) Regulation vs
Temperature FB Regulation vs Temperature V(ISP-ISN) Regulation vs VFB
RDS(ON) vs Temperature Peak Current vs Temperature
Minimum On-Time vs
Temperature
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.10
0.15
0.20
0.25
0.30
V
CTRL
(V)
3942 G19
V
CTRL
(V)
0
0.25
0.50
0.75
1
1.25
1.50
1.75
2
0
25
50
75
100
125
V
(ISP–ISN)
(mV)
3942 G20
V
ISP
(V)
0
5
10
15
20
25
30
35
40
94
96
98
100
102
104
106
V
(ISP–ISN)
(mV)
3942 G21
ISP = 0V
ISP = 12V
ISP = 36V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
94
96
98
100
102
104
106
V
(ISP–ISN)
(mV)
3942 G22
V
IN
= 3V
V
IN
= 12V
V
IN
= 36V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.97
0.98
0.99
1.00
1.01
1.02
1.03
V
FB
(V)
3942 G23
V
FB
(V)
0.96
0.97
0.98
0.99
1
1.01
1.02
1.03
1.04
0
20
40
60
80
100
120
V
(ISP–ISN)
(mV)
3942 G24
Switch A
Switch B
Switch C
Switch D
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
50
100
150
200
250
300
R
DS(ON)
(mOhm)
3942 G25
BUCK
BOOST
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
I
SW
(A)
3942 G26
SW1
SW2
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
10.00
11.00
12.00
13.00
14.00
15.00
D
SW
(%)
3942 G27
LT3942
9
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum On-Time vs
Temperature FB Overvoltage Threshold FB Open LED Threshold
FB Short LED Threshold ISP/ISN Open LED Threshold SS Current vs Temperature
Frequency vs Temperature ISMON Voltage vs V(ISP–ISN) ISMON vs Temperature
SW1
SW2
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
85.00
86.00
87.00
88.00
89.00
90.00
D
SW
(%)
3942 G28
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.80
0.85
0.90
0.95
1.00
1.05
1.10
V
FB
(V)
3942 G29
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.80
0.85
0.90
0.95
1.00
1.05
1.10
V
FB
(V)
3942 G30
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.10
0.15
0.20
0.25
0.30
0.35
0.40
V
FB
(V)
3942 G31
FALLING
RISING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
V
(ISP-ISN)
(mV)
3942 G32
PULL–DOWN
PULL–UP
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
2.5
5.0
7.5
10.0
12.5
15.0
I
SS
(µA)
3942 G33
RT = 14.3k
RT = 43.2k
RT = 178k
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
500
1000
1500
2000
2500
SWITCHING FREQUENCY (kHz)
3942 G34
V
(ISP–ISN)
(mV)
0
10
20
30
40
50
60
70
80
90
100
0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
1.15
1.25
ISMON (V)
3942 G35
V
(ISP–ISN)
= 100mV
V
(ISP–ISN)
= 10mV
V
(ISP–ISN)
= 0mV
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
0.25
0.50
0.75
1.00
1.25
1.50
V
ISMON
(V)
3942 G36
LT3942
10
Rev. 0
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PIN FUNCTIONS
PVIN: Power Input. The PVIN pins connect to the power
input of the LED driver. Bypass this pin to ground with a
ceramic capacitor. The bypass capacitor should be placed
as close to the chip as possible with vias directly down to
the ground plane.
V
IN
: Bias Supply. The V
IN
pin supplies the internal circuitry
and the INTVCC linear regulator. Connect this pin to PVIN
or another power supply. Bypass this pin to ground with
a ceramic capacitor.
INTVCC: Internal 3.6V Linear Regulator Output. Powered
from the VIN pin, the INTVCC supplies the internal control
circuitry and gate drivers. Bypass this pin to ground with
a minimum 1µF ceramic capacitor.
EN/UVLO: Enable and Undervoltage Lockout. Force the
pin below 0.3V to shut down the chip and reduce VIN qui-
escent current below 2µA. Force the pin above 1.235V for
normal operation. The accurate 1.220V falling threshold
can be used to program an undervoltage lockout (UVLO)
threshold with a resistor divider from PVIN to ground. An
accurate 2.5µA pull-down current allows the program-
ming of PVIN UVLO hysteresis. If neither function is used,
tie this pin directly to VIN.
OVLO: Overvoltage Lockout. The OVLO pin can be used to
program an overvoltage lockout (OVLO) threshold with a
resistor divider from PVIN to ground. Force the pin above
1.220V to pull SS pin to ground and stop switching. If not
used, tie this pin to ground.
RP: Internal PWM Dimming Frequency Setting. The RP
pin is used to set the internal PWM dimming frequency
with a resistor to ground. Do not use a resistor larger than
1MΩ and do not leave this pin open. For external PWM
dimming, tie this pin to ground.
PWM: PWM Dimming Input. The PWM pin can be used
in two ways: external PWM dimming and internal PWM
dimming. For external PWM dimming, drive this pin with a
digital pulse from 0V to a voltage higher than 1.5V to con
-
trol PWM dimming of the LED string. Make sure the RP
pin is tied to ground this case. For internal PWM dimming,
apply an analog voltage between 1V and 2V to generate
an internal digital pulse. If PWM dimming is not used, tie
this pin to INTVCC. Forcing the pin low turns off all power
switches, disconnects the VC pin from all internal loads
and turns off PWMTG.
V
REF
: Voltage Reference Output. The V
REF
pin provides
an accurate 2V reference capable of supplying up to 1mA
current. Bypass this pin to ground with a minimum 0.22µF
ceramic capacitor.
CTRL: Control Input for LED Current Sense Threshold. The
CTRL pin is used to program the LED regulation current:
ILED =
V
CTRL −
0.25V
10 •R
LED
The VCTRL can be set by an external voltage reference
or a resistor divider from V
REF
to ground. For 0.25V≤
VCTRL≤1.15V, the current sense threshold linearly goes
up from 0mV to 90mV. For VCTRL≥1.35V, the current
sense threshold is constant at 100mV full scale value.
For 1.15V≤VCTRL≤1.35V, the current sense threshold
smoothly transitions from the linear function of VCTRL to
the 100mV constant value. Tie CTRL pin to VREF for the
100mV full scale threshold. Force the pin below 0.2V to
stop switching.
ISP: Positive Terminal of LED Current Sense Resistor
(RLED). Ensure accurate current sense with Kelvin
connection.
ISN: Negative Terminal of LED Current Sense Resistor
(RLED). Ensure accurate current sense with Kelvin
connection.
ISMON: LED Current Monitor Output. The ISMON pin
generates a buffered voltage that is equal to ten times
V(ISP-ISN) plus 0.25V offset voltage. The voltage on the
ISMON pin will be 1.25V when V(ISP-ISN) is equal to
100mV fullscale.
LT3942
11
Rev. 0
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PIN FUNCTIONS
FAULT: LED Fault Open Drain Output. The FAULT pin is
pulled low when any of the following conditions happens:
1. Open LED (VFB > 0.95V and V(ISP−ISN) < 10mV)
2. Short LED (VFB < 0.25V)
To function, this pin requires an external pull-up resistor.
The FAULT status is updated only during PWM high state
and latched during PWM low state.
SS: Soft-Start Timer Setting. The SS pin is used to set
soft-start timer by connecting a capacitor to ground. An
internal 12.5µA pull-up current charging the external SS
capacitor gradually ramps up FB regulation voltage. A
22nF capacitor is recommended on this pin. Any UVLO,
OVLO, or thermal shutdown immediately pulls SS pin to
ground and stops switching. Using a single resistor from
SS to VREF, the LT3942 can be set in three different fault
modes during open or short LED fault conditions: hiccup
(no resistor), latch-off (499k) and keep-running (100k).
See more details in the Applications Information section.
FB: Voltage Loop Feedback Input. The FB pin is used
for constant-voltage regulation and LED fault protec-
tion. The internal error amplifier with its output VC regu-
lates VFB to 1.00V through the LED driver. During open
LED (VFB>0.95V and V(ISP-ISN) < 10mV) or short LED
(VFB<0.25V) fault conditions, the part pulls the FAULT
pin low and enters one fault mode per customer setting.
During an overvoltage (VFB > 1.05V) condition, the part
turns off all power switches and PWMTG.
VC: Error Amplifier Output to Set Inductor Current
Comparator Threshold. The VC pin is used to compen-
sate the control loop with an external RC network. During
PWM low state, the VC pin is disconnected from all inter-
nal loads to store its voltage information for the highest
PWM dimming performance.
RT: Switching Frequency Setting. Connect a resistor from
this pin to ground to set the internal oscillator frequency
from 300kHz to 2MHz.
SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at the
internal oscillator frequency. Apply a clock signal for
external frequency synchronization. Tie to INTVCC for
25% triangle spread spectrum above internal oscillator
frequency.
PWMTG: PWM Dimming Top Gate Drive. The PWMTG
pin produces a buffered and inverted version of the PWM
input signal and drives an external high side PMOS PWM
switch with a voltage swing from the higher voltage
between (PVOUT−5V) and 1.2V to PVOUT. Leave this pin
open if not used.
PVOUT: Power Output. The PVOUT pins connect to the
power output of the LED driver and also serve as the posi-
tive rail for the PWMTG drive. Bypass this pin to ground
with a ceramic capacitor. The bypass capacitor should be
placed as close to the chip as possible with vias directly
down to the ground plane.
SW2: Boost Side Switch Node. The SW2 pin connects to
the internal power switches and swings from ground to
a diode voltage above PVOUT. Minimize the PCB area and
trace length to keep EMI low.
BST2: Boost Side Bootstrap Floating Driver Supply. The
BST2 pin connects to an integrated bootstrap diode from
the INTV
CC
pin and requires an external bootstrap capaci-
tor to the SW2 pin.
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin connects to an integrated bootstrap diode from
the INTV
CC
pin and requires an external bootstrap capaci-
tor to the SW1 pin.
SW1: Buck Side Switch Node. The SW1 pin connects
to the internal power switches and swings from a diode
voltage drop below ground up to PVIN. Minimize the PCB
area and trace length to keep EMI low.
GND (Exposed Pad): Ground. Solder the exposed pad
directly to the ground plane.
LT3942
12
Rev. 0
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BLOCK DIAGRAM
3942 BD
CTRL
1.25V
SS
1V
–
+
EA2
++
+
–
+
–
+
–
+
–
+
–
CTRL
OVLO
EN/UVLO
FB
PVIN
PVIN
BST1
INTVCC
VIN
VREF
RT
SYNC/SPRD
PVOUT
PVOUT
BST2
PWMTG
0.2V
1.220V
1.220V
1.220V
FB
V(ISP-ISN)
1.05V
0.75V
INHIBIT
SWITCH
LINEAR
REGULATOR
AND
REFERENCE
+
–
+
–
+
–
0.35V
FB
0.25V
ISMON_INT
0.95V
FB
LED
FAULT
LOGIC
12.5µA
10µA
1.25µA
FAULT
OSCILLATOR
A1
+–
BUCK LOGIC
BUCK_MODE
BOOST LOGIC
BOOST_MODE
A = 1
–
+
A = 10
INTVCC
ISP
ISN
PWM
LOGIC
PWM
RP
PWM_INT
PWM_INT
A D
B C
D1 D2
PVOUT – 5V
PVOUT
A2
+–
22
21
25
20
16
11
12
8
7
10
6
5
1
2
26
4
3
9
18
19
14
SW1 SW1
VLS
SW2 SW2
28 27 24 23
ISMONVC
GND SS
1317
29 15
+
2.5µA
ISMON_INT
–
+
EA1
+
250mV
VREF
LT3942
13
Rev. 0
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OPERATION
The LT3942 is a current mode LED driver that can regulate
LED current from input voltage above, below or equal
to the LED string voltage. Four internal low resistance
N-channel DMOS switches minimize the size of the appli-
cation circuit and reduce power losses to maximize effi-
ciency. Internal high side gate drivers, which require only
the addition of two small external capacitors, further sim-
plify the design process. The ADI proprietary peak-buck
peak-boost current mode control scheme directly senses
the inductor current across the internal power switches
and provides smooth transition between buck region,
buck-boost region and boost region. The LT3942 can be
configured to operate over a wide range of switching fre-
quencies, from 300kHz to 2MHz, allowing applications to
be optimized for broad area and efficiency. Its operation
can be best understood by referring to the Block Diagram.
Power Switch Control
Figure1 shows the topology of the LT3942 power stage,
which is comprised of four N-channel DMOS switches
and their associated gate drivers. Figure2 shows the
current mode control as a function of PVIN/PVOUT ratio
and Figure3 shows the operation region as a function of
PVIN/PVOUT ratio. The power switches are properly con-
trolled to smoothly transition between modes and regions.
Hysteresis is added to prevent chattering between modes
and regions.
There are total four states: (1) peak-buck current mode
control in buck region, (2) peak-buck current mode con-
trol in buck-boost region, (3) peak-boost current mode
control in buck-boost region and (4) peak-boost current
mode control in boost region. The following sections give
detailed descriptions for each state with waveforms, in
which the shoot-through protection dead time between
switches A and B, between switches C and D are ignored
for simplification.
Figure1. Power Stage Schematic
C
BST1
C
BST2
L
3942 F01
INTVCC INTVCC
INTVCC INTVCC
PVIN PVOUT
BST1 SW1 SW2 BST2
A
B
D
C
LT3942
GND GND
PEAK-BUCK
PEAK-BOOST
PVIN/PVOUT
1.00 1.04
3942 F02
BUCK
(4)
(3)
(2)
(2)
BOOST
BUCK-BOOST
PV
IN
/PV
OUT
0.850.75 1.00 1.25 1.33
3942 F03
(1)
Figure2. Current Mode vs PVIN/PVOUT Ratio
Figure3. Operation Region vs PVIN/PVOUT Ratio
LT3942
14
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(1) Peak-Buck in Buck Region (PVIN >> PVOUT)
When PVIN is much higher than PVOUT, the LT3942 uses
peak-buck current mode control in buck region (Figure4).
Switch C is always off and switch D is always on. At the
beginning of every cycle, switch A is turned on and the
inductor current ramps up. When the inductor current hits
the peak buck current threshold commanded by VC volt-
age at buck current comparator A1 during (A+D) phase,
switch A is turned off and switch B is turned on for the
rest of the cycle. Switches A and B will alternate, behaving
like a typical synchronous buck regulator.
OPERATION
(3) Peak-Boost in Buck-Boost Region (PVIN <~ PVOUT)
When PVIN is slightly lower than PVOUT, the LT3942 uses
peak-boost current mode control in buck-boost region
(Figure6). Switch A is always turned on for the begin-
ning 80% cycle and switch B is always turned on for the
remaining 20% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. When the inductor current hits the peak boost
current threshold commanded by VC voltage at boost
current comparator A2 during (A+C) phase, switch C is
turned off and switch D is turned on for the rest of the
cycle. After 80% cycle, switch A is turned off and switch
B is turned on for the rest of the cycle.
A
B
C
D
IL
100% ON
100% OFF
A+D B+D
3942 F04
A
B
C
D
I
L
80% 80%
A+C B+DA+C
A+DA+D
B+D
3942 F05
20%20%
Figure4. Peak-Buck in Buck Region (PVIN >> PVOUT)
Figure5. Peak-Buck in Buck-Boost Region (PVIN ~> PVOUT)
Figure6. Peak-Boost in Buck-Boost Region (PVIN <~ PVOUT)
(2) Peak-Buck in Buck-Boost Region (PVIN ~> PVOUT)
When PVIN is slightly higher than PVOUT, the LT3942 uses
peak-buck current mode control in buck-boost region
(Figure5). Switch C is always turned on for the begin-
ning 20% cycle and switch D is always turned on for the
remaining 80% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. After 20% cycle, switch C is turned off and
switch D is turned on, and the inductor keeps ramping
up. When the inductor current hits the peak buck current
threshold commanded by V
C
voltage at buck current com-
parator A1 during (A+D) phase, switch A is turned off and
switch B is turned on for the rest of the cycle.
A
B
C
D
I
L
80% 80%
A+C B+DA+C
A+DA+D
B+D
3942 F06
20%20%
LT3942
15
Rev. 0
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(4) Peak-Boost in Boost Region (PVIN << PVOUT)
When PVIN is much lower than PVOUT, the LT3942
uses peak-boost current mode control in boost region
(Figure7). Switch A is always on and switch B is always
off. At the beginning of every cycle, switch C is turned
on and the inductor current ramps up. When the induc-
tor current hits the peak boost current threshold com-
manded by V
C
voltage at boost current comparator A2
during (A+C) phase, switch C is turned off and switch D
is turned on for the rest of the cycle. Switches C and D
will alternate, behaving like a typical synchronous boost
regulator.
OPERATION
is controlling the four power switches so that either the
FB voltage is regulated to 1V or the current sense voltage
between the ISP and ISN pins is regulated by the CTRL
pin during normal operation. The gains of EA1 and EA2
have been balanced to ensure smooth transition between
constant-voltage and constant-current operation with the
same compensation network.
Light Load Current Operation
At light load, the LT3942 typically still runs at its full
switching frequency in discontinuous conduction mode.
Both buck and boost reserve current sense thresholds
are set to be zero, thus preventing any reverse current
flowing from the output to the input. In the buck region,
switch B is turned off whenever the buck reverse current
threshold is triggered during (B+D) phase. In the boost
region, switch D is turned off whenever the boost reverse
current threshold is triggered during (A+D) phase. In the
buck-boost region, switch D is turned off whenever the
boost reverse current threshold is triggered during (A+D)
phase, and both switches B and D are turned off whenever
the buck reverse current threshold is triggered during
(B+D) phase.
As the load becomes lower and lower, or when a smaller
value inductor is used and the inductor current ripple is
bigger, the LT3942 may run in pulse-skip mode, where
the switches are held off for multiple cycles (i.e., skipping
pulses) to maintain the regulation.
Internal Charge Path
Each of the two high side gate drivers is biased from
its floating bootstrap capacitor CBST1 and CBST2, which
is normally recharged by INTVCC through the integrated
bootstrap diode D1 and D2 when the top power switch is
turned off. When the LT3942 operates exclusively in the
buck or boost regions, one of the top power switches is
constantly on. An internal charge path, from PVOUT and
BST2 to BST1 or from PVIN and BST1 to BST2, charges
the bootstrap capacitor to above 3.3V so that the top
power switch can be kept on.
Figure7. Peak-Boost in Boost Region (PVIN << PVOUT)
A
B
C
D
I
L
100% OFF
100% ON
A+C A+D
3942 F07
Main Control Loop
The LT3942 is a fixed frequency current mode LED driver.
The inductor current is directly sensed across the internal
switch A. The current sense voltage is added to a slope
compensation ramp signal from the internal oscillator.
The summing signal is then fed into the positive termi-
nals of the buck current comparator A1 and boost current
comparator A2. The negative terminals of A1 and A2 are
controlled by the voltage on the V
C
pin, which is the diode-
OR of error amplifiers EA1 and EA2.
Depending on the state of the peak-buck peak-boost cur-
rent mode control, either the buck logic or the boost logic
LT3942
16
Rev. 0
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Shutdown and Power-On-Reset
The LT3942 enters shutdown mode and drains less than
2µA quiescent current when the EN/UVLO pin is below its
shutdown threshold (0.3V minimum). Once the EN/UVLO
pin is above its shutdown threshold (0.9V maximum), the
LT3942 wakes up start-up circuitry, generates the band-
gap reference and powers up the internal INTV
CC
LDO.
The INTV
CC
LDO supplies the internal control circuitry
and gate drivers. When the EN/UVLO is between 0.9V and
1.220V, the LT3942 enters undervoltage lockout (UVLO)
mode with a hysteresis current (2.5µA typical) pulled into
the EN/UVLO pin. When the INTVCC pin is charged above
its rising UVLO threshold (2.49V typical), the EN/UVLO
pin exceeds its rising enable threshold (1.235V typical)
and the junction temperature is less than its thermal shut-
down (165°C typical), the LT3942 enters enable mode
and the EN/UVLO hysteresis current is turned off. When
the voltage on the OVLO pin, which is programmed by a
resistor divider from PV
IN
to GND, exceeds its 1.220V ris-
ing threshold (with 35mV falling hysteresis), the LT3942
enters overvoltage lockout (OVLO) mode. Only when both
UVLO and OVLO are cleared, the voltage reference VREF
can be charged up from ground to regulation. From the
time of entering enable mode to the time of VREF passing
its rising UVLO threshold (1.89V typical), the LT3942 is
going through a power-on-reset (POR), waking up the
entire internal control circuitry and settling to the right
initial conditions. After the POR, the LT3942 is ready and
waiting for the signals on the CTRL and PWM pins to
start switching.
Start-Up and Fault Protection
Figure8 shows the start-up and fault sequence for the
LT3942. In the POR state, the SS pin is hard pulled down
with a 100Ω to ground. In a pre-biased condition, the SS
pin has to be pulled below 0.2V to enter the INIT state,
where the LT3942 wait 10µs so that the SS pin can be
fully discharged to ground. After the 10µs, the LT3942
enters the UP/PRE state when the PWMON signal goes
high. The PWMON high signal happens when the CTRL pin
is above its rising dim-off thresholds (0.225V typical) and
the external or internal PWM dimming is on.
OPERATION
During the UP/PRE state, the SS pin is charged up by a
12.5µA pull-up current while the switching is disabled
and the PWMTG is turned off. Once the SS pin is charged
above 0.25V, the LT3942 enters the UP/TRY state, where
the PWMTG is turned on first while the switching is still
disabled. This is to check that the voltage on the out-
put capacitor is not too high for the LED string before
any switching energy delivery. If a higher voltage output
capacitor is connected to a lower voltage LED string, the
excessive current flowing through the LED string and the
current sense resistor triggers the ISP/ISN over current
(ISOC) signal and resets the LT3942 back to the POR
state. So the LT3942 will hiccup between 0V and 0.25V
and go through the POR, INIT, UP/PRE and UP/TRY states
to slowly discharge the higher voltage output capacitor
until its voltage drops closer to the lower voltage LED
Figure8. Start-Up and Fault Sequence
INIT
SS < 0.2V • SS HARD PULL-DOWN
• SWITCHING DISABLED
• PWMTG TURNED OFF
• NO OPEN/SHORT DETECTION
WAIT 10µs AND
PWMON = HI
WAIT 10µs
POR = HI OR
ISOC = HI
OPEN LED OR
SHORT LED
3942 F08
SS < 0.2V AND
PWMON = HI
SS > 0.25V
SS > 1.75V
SS < 1.7V
UP/PRE
• SS 12.5µA PULL-UP
• SWITCHING DISABLED
• PWMTG TURNED OFF
• NO OPEN/SHORT DETECTION
OK/RUN
• SS 12.5µA PULL-UP
• SWITCHING ENABLED
• PWMTG TURNED ON
• OPEN/SHORT DETECTION
FAULT/RUN
• SS 1.25µA PULL-DOWN
• SWITCHING ENABLED
• PWMTG TURNED ON
• OPEN/SHORT DETECTION
POR
• SS HARD PULL-DOWN
• SWITCHING DISABLED
• PWMTG TURNED OFF
• NO OPEN/SHORT DETECTION
UP/TRY
• SS 12.5µA PULL-UP
• SWITCHING DISABLED
• PWMTG TURNED ON
• NO OPEN/SHORT DETECTION
UP/RUN
• SS 12.5µA PULL-UP
• SWITCHING ENABLED
• PWMTG TURNED ON
• NO OPEN/SHORT DETECTION
DOWN/STOP
• SS 1.25µA PULL-DOWN
• SWITCHING DISABLED
• PWMTG TURNED ON
• NO OPEN/SHORT DETECTION
LT3942
17
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string. After 10µs in the UP/TRY state without triggering
the ISOC signal, the LT3942 enters the UP/RUN state.
In the UP/RUN state, the switching is enabled and the
start-up of the output voltage PVOUT is controlled by the
voltage on the SS pin. When the SS pin voltage is less
than 1V, the LT3942 regulates the FB pin voltage to the
SS pin voltage instead of the 1V reference. This allows the
SS pin to be used to program soft-start by connecting an
external capacitor from the SS pin to GND. The internal
12.5µA pull-up current charges up the capacitor, creating
a voltage ramp on the SS pin. As the SS pin voltage rises
linearly from 0.25V to 1V (and beyond), the output volt-
age PVOUT rises smoothly to its final LED string voltage.
Once the SS pin is charged above 1.75V, the LT3942
enters the OK/RUN state, where the LED fault (both open
LED and short LED) detection is activated. The open LED
indicates that VFB > 0.95V and V(ISP-ISN) < 10mV, and
the short LED indicates that VFB < 0.25V. Both the open
LED and short LED faults are reported to the FAULT pin.
OPERATION
When either fault occurs, the LT3942 enters the FAULT/
RUN state, where a 1.25µA pull-down current slowly dis-
charges the SS pin. Once the SS pin is discharged below
1.7V, the LT3942 enters the DOWN/STOP state, where
the switching is disabled and the LED fault detection is
deactivated with the previous fault latched. Once the SS
pin is discharged below 0.2V and the PWMON signal is still
high, the LT3942 goes back to the UP/RUN state.
In an open or short LED condition, the LT3942 can be set
to hiccup, latch-off, or keep-running fault protection mode
with a resistor between the SS and VREF pins. Without any
resistor, the LT3942 will hiccup between 0.2V and 1.75V
and go through the UP/RUN, OK/RUN, FAULT/RUN and
DOWN/STOP states until the fault condition is cleared.
With a 499k resistor, the LT3942 will latch off until the
EN/UVLO is toggled. With a 100k resistor, the LT3942 will
keep running regardless of the fault.
LT3942
18
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The front page shows a typical LT3942 application circuit.
This Applications Information section serves as a guide-
line for selecting external components for typical applica-
tions. The examples and equations in this section assume
continuous conduction mode unless otherwisespecified.
Switching Frequency Selection
The LT3942 uses a constant frequency control scheme
between 300kHz and 2MHz. Selection of the switching
frequency is a trade-off between efficiency and compo-
nent size. Low frequency operation improves efficiency
by reducing switching losses, but requires larger inductor
and capacitor values. For high power applications, con-
sider operating at lower frequencies to minimize switch-
ing losses. For low power applications, consider operating
at higher frequencies to minimize the total solution size.
In addition, the specific application can play an important
role in switching frequency selection. In a noise-sensitive
system, the switching frequency is usually selected to
keep the switching noise out of a sensitive frequency
band.
Switching Frequency Setting
The switching frequency of the LT3942 can be set by
the internal oscillator. With the SYNC/SPRD pin pulled to
ground, the switching frequency is set by a resistor from
the RT pin to ground. Table1 shows RT resistor values
for common switching frequencies.
Table1. Switching Frequency vs RT Value (1% Resistor)
fOSC (kHz) RT (kΩ)
300 178
400 124
600 78.7
800 56.2
1000 43.2
1200 33.2
1400 26.1
1600 21.5
1800 17.4
2000 14.3
APPLICATIONS INFORMATION
Spread Spectrum Frequency Modulation
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is
a concern. To improve the EMI performance, the LT3942
implements a triangle spread spectrum frequency modu-
lation scheme. With the SYNC/SPRD pin tied to INTVCC,
the LT3942 spreads its switching frequency 25% above
the internal oscillator frequency. Figures 9 and 10 show
the noise spectrum of the front page application with fer-
rite bead EMI filter and spread spectrum enabled.
CISPR 25 Average Conducted EMI
Figure9. Conducted Average EMI Comparison
Figure10. Conducted Peak EMI Comparison
CISPR 25 Average Conducted EMI
CISPR 25 Peak Conducted EMI
CLASS 5 AVERAGE LIMIT
NOISE FLOOR
SSFM ON WITH FILTER
FREQUENCY (MHz)
0.1
1
10
100
–20
–10
0
10
20
30
40
50
60
70
AVERAGE CONDUCTED EMI (dBµV)
3942 F09
CLASS 5 PEAK LIMIT
NOISE FLOOR
SSFM ON WITH FILTER
FREQUENCY (MHz)
0.1
1
10
100
–10
0
10
20
30
40
50
60
70
80
PEAK CONDUCTED EMI (dBµV)
3942 F10
LT3942
19
Rev. 0
For more information www.analog.com
Frequency Synchronization
The LT3942 switching frequency can be synchronized to
an external clock using the SYNC/SPRD pin. Driving the
SYNC/SPRD with a 50% duty cycle waveform is always a
good choice, otherwise maintain the duty cycle between
10% and 90%. Due to the use of a phase-locked loop
(PLL) inside, there is no restriction between the synchro-
nization frequency and the internal oscillator frequency.
The rising edge of the synchronization clock represents
the beginning of a switching cycle, turning on switches
Aand C, or switches A and D.
Maximum Output Current
The LT3942 uses the PVIN/PVOUT ratio to transition
between modes and regions. The IR drop in the power
path caused by RDS(ON) of power switches and DCR of
inductor can limit the output current capability. The maxi-
mum output current at certain PV
OUT
is typically deter-
mined by:
IOUT ≤ 0.1 • VOUT
The R
DS(ON)
and DCR increase at higher junction tem-
perature and the process variation have been included in
the calculation above.
Meanwhile, the maximum output current also depends on
minimum PVIN, maximum VLED, LED current and switch
peak current limit.
Inductor Selection
The switching frequency and inductor selection are inter-
related in that higher switching frequencies allow the use
of smaller inductor and capacitor values. The inductor
value has a direct effect on ripple current. The highest cur-
rent ripple ∆IL% happens in the buck region at PVIN(MAX)
and the lowest current ripple ∆IL% happens in the boost
region at PVIN(MIN). For any given ripple allowance, the
minimum inductance can be calculated as:
LBUCK >
PVOUT • PVIN MAX
( )
– PVOUT
( )
fSW • ILED MAX
( )
• ∆IL% • PVIN MAX
( )
APPLICATIONS INFORMATION
LBOOST >
PVIN MIN
( )
2• PVOUT – PVIN MIN
( )
( )
fSW • ILED MAX
( )
• ∆IL% • PVOUT2
where:
fSW is switching frequency
∆IL% is allowable inductor current ripple
PVIN(MIN) is minimum power input voltage
PVIN(MAX) is maximum power input voltage
PVOUT is output voltage
ILED(MAX) is maximum LED current
Slope compensation provides stability in constant fre-
quency current mode control by preventing subharmonic
oscillations at certain duty cycles. The minimum induc-
tance required for stability can be calculated as:
L>
V
OUT
2 • fSW • ISW MAX
( )
where:
fSW is switching frequency
ISW(MAX) is maximum switch current limit = 2A (Min)
For high efficiency, choose an inductor with low core loss,
such as ferrite. Also, the inductor should have low DC
resistance to reduce the I2R losses and must be able to
handle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor.
CIN and COUT Selection
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out the regulator. A parallel combination of capaci
-
tors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors
are all available in surface mount packages. Capacitors
with low ESR and high ripple current ratings, such as
OS-CON and POSCAP are also available.
CISPR 25 Average Conducted EMI
LT3942
20
Rev. 0
For more information www.analog.com
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
spikes. Ceramic capacitors, ≥ 1µF, should also be placed
from PVIN/VIN to GND and PVOUT to GND as close to
the LT3942 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce input ripple voltage and help reduce power loss
in the higher ESR bulk capacitors. X5R or X7R dielec-
trics are preferred, as these materials retain their capaci-
tance over wide voltage and temperature ranges. Many
ceramic capacitors, particularly 0805 or 0603 case
sizes, have greatly reduced capacitance at the desired
operatingvoltage.
Input Capacitance CIN
Discontinuous input current is highest in the buck region
due to the switch A toggling on and off. Make sure that the
CIN capacitor network has low enough ESR and is sized
to handle the maximum RMS current. In buck region, the
input RMS current is given by:
IRMS ≈ILED MAX
( )
•PVOUT
PVIN
•PVIN
PVOUT
– 1
The formula has a maximum at PVIN = 2PVOUT, where
IRMS =I
LED(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief.
Output Capacitance COUT
Discontinuous current shifts from the input to the output
in the boost region. Make sure that the COUT capacitor
network is capable of reducing the output voltage ripple.
The effects of ESR and the bulk capacitance must be con-
sidered when choosing the right capacitor for a given
output ripple voltage. The maximum steady state ripple
due to charging and discharging the bulk capacitance is
given by:
∆ VCAP BOOST
( )
=
ILED • PVOUT – PVIN MIN
( )
( )
COUT • PVOUT • fSW
APPLICATIONS INFORMATION
∆ VCAP BUCK
()
=
PVOUT • 1– PVOUT
PVIN MAX
( )
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
8 • L • f
SW
2• C
OUT
The maximum steady ripple due to the voltage drop
across the ESR is given by:
∆ VESR BOOST
()
=
PVOUT • ILED MAX
( )
PVIN MIN
( )
• ESR
∆ VESR BUCK
()
=
PVOUT • 1– PVOUT
PVIN MAX
( )
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
L • f
SW
• ESR
INTVCC Regulator
An internal P-channel low dropout regulator produces
3.6V at the INTVCC pin from the VIN supply pin. The
INTVCC powers internal circuitry and gate drivers in the
LT3942. The INTVCC regulator can supply a peak cur-
rent of 40mA and must be bypassed to ground with a
minimum of 1µF ceramic capacitor. Good local bypass is
necessary to supply the high transient current required
by power switch gate drivers.
Higher input supply voltage applications with higher
switching frequencies may cause the maximum junc-
tion temperature rating for the LT3942 to be exceeded.
The system supply current is normally dominated by
the gate charge current that drives the four internal
powerswitches.
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked oper-
ating in continuous mode at maximum PVIN/VIN.
High Side Gate Driver Supply (CBST1, CBST2)
The high side gate drivers for the two top power switches,
A and D, are driven between their respective SW and BST
pin voltages. The boost voltages are biased from floating
bootstrap capacitors C
BST1
and C
BST2
, which are normally
recharged through internal bootstrap diodes D1 and D2
LT3942
21
Rev. 0
For more information www.analog.com
when the respective top power switch is turned off. Both
capacitors are charged to the same voltage as the INTVCC
voltage. In most applications, a typical 0.1µF, X5R or X7R
dielectric capacitor is adequate.
Programming PVIN UVLO and OVLO
A resistor divider from PVIN to the EN/UVLO pin imple-
ments PVIN undervoltage lockout (UVLO). The EN/UVLO
enable falling threshold is set at 1.220V with 15mV hyster-
esis. In addition, the EN/UVLO pin sinks 2.5µA when the
voltage on the pin is below 1.220V. This current provides
user programmable hysteresis based on the value of R1.
The programmable UVLO thresholds are:
VIN UVLO+
()
=1.235V •
R1
+
R2
R2
+2.5µA • R
1
VIN UVLO–
( )
=1.220V •
R1
+
R2
R2
Figure11 shows the implementation of external shutdown
control while still using the UVLO function. The NMOS
grounds the EN/UVLO pin when turned on and puts the
LT3942 in shutdown with quiescent current less than 2µA.
APPLICATIONS INFORMATION
Programming LED Current
The LED current is programmed by placing an appropriate
value current sense resistor, RLED, in series with the LED
string. The voltage drop across RLED is (Kelvin) sensed
by the ISP and ISN pins. The CTRL pin should be tied to a
voltage higher than 1.35V to obtain the full-scale 100mV
obtain (typical) threshold across the sense resistor. The
CTRL pin can be used to dim the LED current to zero,
although relative accuracy decreases with the decreasing
sense threshold. When the CTRL pin voltage, VCTRL, is
less than 1.15V, the LED current is:
ILED =
V
CTRL
– 250mV
10 • R
LED
When VCTRL is between 1.15V and 1.35V, the LED current
varies with VCTRL, but departs from the equation above
by an increasing amount as VCTRL increases. Ultimately,
when VCTRL > 1.35V the LED current no longer varies. The
typical V(ISP-ISN) threshold vs VCTRL is listed in Table2.
Table2. V(ISP-ISN) Threshold vs VCTRL
VCTRL (V) V(ISP-ISN) (mV)
1.15 90
1.20 94.5
1.25 98
1.30 99.5
1.35 100
When V
CTRL
is higher than 1.35V, the LED current is regu-
lated to:
ILED =100mV
R
LED
Figure11. PVIN Undervoltage Lockout (UVLO)
Figure12. PVIN Overvoltage Lockout (OVLO)
LT3942
R1
GND
RUN/STOP
CONTROL
(OPTIONAL)
3942 F11
R2
EN/UVLO
PV
IN
A resistor divider from PVIN to the OVLO pin implements
PVIN overvoltage lockout (OVLO). The OVLO rising
threshold is set at 1.220V with 35mV falling hysteresis.
Figure12 shows the implementation of PVIN OVLO func-
tion. The programmable OVLO thresholds are:
VIN OVLO+
( )
=1.220V • R3 +R4
R4
VIN OVLO–
()
=1.185V •
R3
+
R4
R4
LT3942
R3
GND
3942 F12
R4
OVLO
PV
IN
LT3942
22
Rev. 0
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The CTRL pin should not be left open (tie to VREF if not
used). The CTRL pin can also be used in conjunction with
a thermistor to provide overtemperature protection for
the LED load, or with a resistor divider to PVIN to reduce
output power and switching current when PV
IN
is low.
The presence of a time varying differential voltage ripple
signal across ISP and ISN at the switching frequency is
expected. The amplitude of this signal is increased by
higher LED load current, lower switching frequency or
smaller value output filter capacitor. Some level of ripple
signal is acceptable, and the compensation capacitor
on the VC pin filters the signal so the average difference
between ISP and ISN is regulated to the user-programmed
value. The ripple voltage amplitude (peak-to-peak) in
excess of 20mV should not cause mis-operation, but may
lead to noticeable offset between the average value and
the user-programmed value.
Monitoring LED Current
The ISMON pin provides a linear indication of the current
flowing through the LEDs. It outputs a buffered and ampli-
fied value of the voltage difference between ISP and ISN
pins. The equation for VISMON is:
VISMON = 10 • V(ISP–ISN) + 250mV
Dimming Control
There are two methods to control the LED current for dim-
ming using the LT3942. One method uses the CTRL pin to
adjust the current regulated in the LEDs. A second method
uses the PWM pin to modulate the LED current between
zero and full current to achieve a precisely programmed
average current.
Compared to the analog dimming method, the PWM dim-
ming method offers much higher dimming ratio without
any color shift. To make PWM dimming more accurate, the
switch demand current is stored on the V
C
node when the
PWM signal is low. This feature minimizes recovery time
when the PWM signal goes high. To further improve the
recovery time, a high side PMOS PWM switch should be
used in the LED current path to prevent the output capaci-
tor from discharging during the PWM signal lowphase.
The choice of switching frequency, inductor value and
loop compensation affects the minimum PWM on time,
APPLICATIONS INFORMATION
below which the LT3942 loses the LED current regulation.
For the same application, the LT3942 achieves the highest
PWM dimming ratio (up to 5000:1) in buck region, the
medium PWM dimming ratio (up to 2500:1) in buck-boost
region and the lowest PWM dimming ratio (up to 2000:1)
in boost region.
In either fixed frequency operation set by RT resistor or
spread spectrum frequency operation, the internal oscilla-
tor is synchronized to the PWM signal rising edge, thereby
providing flicker-free PWM dimming performance. In
external frequency synchronization operation, both SYNC
and PWM signals must have synchronized rising edges to
achieve flicker-free PWM dimming performance.
The LT3942 provides both external PWM dimming and
internal PWM dimming. For external PWM dimming,
choose RP resistor less than 30k and apply an external
PWM clock signal to the PWM pin. For internal PWM
dimming, choose RP resistor to one of the seven resis-
tor values in Table3 and apply analog DC voltage to the
PWM pin. The RP resistor sets the internal PWM dimming
frequency, and the 1V to 2V analog DC voltage on the
PWM pin sets the internal PWM dimming duty ratio from
0% to 100% with a discrete 1/128 step size, as shown
in Figure13.
Table3. Internal PWM Dimming Frequency vs RP Value
(1%Resistor)
RP (kΩ) fSW fSW = 200kHz fSW = 1MHz fSW = 2MHz
< 20 External External External External
28.7 fSW/28781Hz 3.91kHz 7.81kHz
47.5 fSW/29391Hz 1.95kHz 3.91kHz
76.8 fSW/210 195Hz 977Hz 1.95kHz
118 fSW/211 98Hz 488Hz 977Hz
169 fSW/212 49Hz 244Hz 488Hz
237 fSW/213 24Hz 122Hz 244Hz
332 fSW/214 12Hz 61Hz 122Hz
PWM (V)
0
PWMTG DUTY
RATIO (%)
100
50
02.51.5 3.02.01.00.5
ALWAYS
OFF
ALWAYS
ON
3942 F13
Figure13. Internal PWM Dimming Duty Ratio vs PWM Voltage
LT3942
23
Rev. 0
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High Side PMOS PWM Switch Selection
A high side PMOS PWM switch is recommended in most
LT3942 applications to maximize the PWM dimming
ratio and protect the LED string during fault conditions.
Compared to a low side NMOS PWM switch, the high side
PMOS PWM switch allows a single wire to the LED string
and ground return path through chassis. The high side
PMOS PWM switch is typically selected for drain-source
voltage VDS, gate-source threshold voltage VGS(TH) and
continuous drain current ID. For proper operations, VDS
rating should exceed the open LED regulation voltage set
by the FB pin, the absolute value of V
GS(TH)
should be less
than 3V, and ID rating should be above ILED(MAX).
Programming Output Voltage and Thresholds
The LT3942 has a voltage feedback pin FB that can be
used to program a constant-voltage output. The output
voltage can be set by selecting the values of R5 and R6
(Figure14) according to the following equation:
VOUT =1.00V •
R5
+
R6
R6
APPLICATIONS INFORMATION
PWMTG to disconnect the LED string for protection. The
output overvoltage threshold can be set as:
VOUT OVP
( )
=1.05V •
R5
+
R6
R6
Make sure the expected VFB during normal operation
stays between the short LED rising threshold 0.3V and
the open LED falling threshold 0.9V:
0.3V ≤VLED •
R6
R5 +R6
≤0.9V
These equations set the maximum LED string voltage with
full open LED protection for the LT3942 to be 34V.
FAULT Pin
The LT3942 provides an open-drain status pin, FAULT,
which is pulled low during either open LED or short LED
conditions. The open LED condition happens when the FB
pin is above 0.95V and the voltage across V(ISP-ISN) is less
than 10mV. The short LED condition happens when the
FB pin is below 0.25V. The FAULT status is updated when
the SS pin is above 1.75V and the PWM signal is high.
Soft-Start and Fault Protection
As shown in Figure8 and explained in the Operation sec-
tion, the SS pin can be used to program soft-start by con-
necting an external capacitor from the SS pin to ground.
The internal 12.5µA pull-up current charges up the capaci-
tor, creating a voltage ramp on the SS pin. As the SS pin
voltage rises linearly from 0.25V to 1V (and beyond), the
output voltage rises smoothly and transitions into LED
current regulation. The soft-start range is defined to be
the voltage range from 0V to the FB voltage in LED cur-
rent regulation. The soft-start time can be calculated as:
tSS =VLED •R6
R5
+
R6 •CSS
12.5µA
Make sure CSS is at least five to ten times larger than the
compensation capacitor on the VC pin. A 22nF ceramic
capacitor is a good starting point.
Figure14. Feedback Resistor Connection
LT3942
R5
GND
3942 F14
R6
FB
PV
OUT
In addition, the FB pin also sets output overvoltage thresh-
old, open LED threshold and short LED threshold. For an
LED driver application with small output capacitors, the
output voltage usually overshoots a lot during an open
LED event. Although the 1.00V FB regulation loop tries to
regulate the output, the loop is usually too slow to prevent
the output from overshooting. Once the FB pin hits its
overvoltage threshold 1.05V, the LT3942 stops switching
by turning off all four power switches and also turns off
LT3942
24
Rev. 0
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APPLICATIONS INFORMATION
The SS pin is also used as a fault timer. Once an open
LED or a short LED fault is detected, a 1.25µA pull-down
current source is activated. Using a single resistor from
the SS pin to the VREF pin, the LT3942 can be set to three
different fault protection modes: hiccup (no resistor),
latch-off (499k) and keep-running (100k).
With a 100k resistor in keep-running mode, the LT3942
continues switching normally, either regulating the pro-
grammed PVOUT during open LED fault or regulating the
current during short LED fault. With a 499k resistor in
latch-off mode, the LT3942 stops switching until the EN/
UVLO pin is pulled low and high to restart. With no resis-
tor in hiccup mode, the LT3942 enters low duty cycle
auto-retry operation. The 1.25µA pull-down current dis-
charges the SS pin to 0.2V and then 12.5µA pull-up cur-
rent charges the SS pin up. If the fault condition has not
been removed when the SS pin reaches 1.75V, the 1.25µA
pull-down current turns on again, initiating a new hiccup
cycle. This will continue until the fault is removed.
Loop Compensation
The LT3942 uses an internal transconductance error
amplifier, the output of which, VC, compensates the con-
trol loop. The external inductor, output capacitor, and
the compensation resistor and capacitor determine the
loopstability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor on the V
C
pin are set to optimize control
loop response and stability. For a typical LED application,
a 2.2nF compensation capacitor on the VC pin is adequate,
and a series resistor should always be used to increase
the slew rate on the VC pin to maintain tighter regulation
of LED current during fast transients on the input supply
of the converter.
Efficiency Considerations
The power efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LT3942 circuits:
1. DC I2R losses. These arise from the resistances
of the MOSFETs, sensing resistor, inductor and PC
board traces and cause the efficiency to drop at high
outputcurrents.
2. Transition loss. This loss arises from the brief amount
of time switch A or switch C spends in the saturated
region during switch node transitions. It depends
upon the input voltage, load current, driver strength
and MOSFET capacitance, among other factors.
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
4. CIN and COUT loss. The input capacitor has the diffi-
cult job of filtering the large RMS input current to the
regulator in buck region. The output capacitor has the
difficult job of filtering the large RMS output current in
boost region. Both CIN and COUT are required to have
low ESR to minimize the AC I2R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in the input
current, then there is no change in efficiency.
LT3942
25
Rev. 0
For more information www.analog.com
TYPICAL APPLICATIONS
93% Efficient 12W (12V, 1A) 2MHz Buck-Boost LED Driver
3942 TA02
+
L1
3.3µH
0.1µF
0.1µF
1µF
499k
115k
100mΩ
1M
64.9k
M1
2.2µF
100k
0.22µF
100k
14.3k
2MHz
3.9k
3.3nF
0.1µF
100k
91k
332k
122Hz
10µF
22µF
10µF
1M
34.8k
100k
ANALOG DIM
BST1
BST2
PV
IN
PV
OUT
EN/UVLO
ISP
ISN
FB
INTV
CC
SSFM ON
NO SSFM/SYNC
SYNC
D1: NEXPERIA PMEG2010EJ
L1: WURTH ELEKTRONIK 74438336033
M1: VISHAY SI2365DS
LT3942
SW2
SW1
V
IN
OVLO
PWMTG
INTV
CC
FAULT
CTRL
ISMON
SYNC/SPRD
V
C
RT
SS
PWM
EXT/ON
INT
V
REF
EXT/ON
INT
RP
GND
FAULT
CURRENT MONITOR
EXT PWM DIM
EXT SYNC
INTVCC
VREF
V
REF
12VLED
1A
VREF
3V TO 36V
LT3942
26
Rev. 0
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TYPICAL APPLICATIONS
12W (12V, 1A) 2MHz Buck-Boost Voltage Regulator
3942 TA03
+
+
L1
3.3µH
0.1µF
0.1µF
1µF
402k
280k
110k
10k
100k
73.2k
L1: WURTH ELEKTRONIK 78438336033
2.2µF
100k
0.22µF
100k
14.3k
2MHz
75k
680pF
0.1µF
10µF
22µF
4.7µF
47µF
4.7µF
1µF
1M
34.8k
BST1
BST2
PVIN
PVOUT
EN/UVLO
ISP
ISN
FB
INTVCC
SSFM ON
NO SSFM/SYNC
SYNC
LT3942
SW2
SW1
VIN
OVLO
PWM
CTRL
INTVCC
FAULT
ISMON
SYNC/SPRD
VC
RT
SS
PWMTG
RP
GND
FAULT
CURRENT MONITOR
EXT SYNC
INTVCC
VREF
12V
1A
VREF
3V TO 36V
10Ω
10Ω
50mΩ
VREF
LT3942
27
Rev. 0
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TYPICAL APPLICATIONS
8W (24V, 330mA) 2MHz Buck-Boost LED Driver
3942 TA04
+
L1
6.8µH
0.1µF
0.1µF
1µF
402k
280k
270mΩ
1M
35.7k
M1
2.2µF
100k
0.22µF
100k
14.3k
2MHz
2.2k
4.7nF
0.1µF
100k
91k
332k
122Hz
10µF
22µF
4.7µF
1M
34.8k
100k
60.9k
BST1
BST2
PV
IN
PV
OUT
EN/UVLO
ISP
ISN
FB
INTV
CC
SSFM ON
NO SSFM/SYNC
SYNC
L1: COILCRAFT XEL4030-682ME
M1: VISHAY SI2319CDS
LT3942
SW2
SW1
V
IN
OVLO
PWMTG
INTV
CC
FAULT
CTRL
ISMON
SYNC/SPRD
V
C
RT
SS
PWM
EXT/ON
INT
V
REF
EXT/ON
INT
RP
GND
FAULT
CURRENT MONITOR
EXT PWM DIM
EXT SYNC
INTVCC
VREF
V
REF
24VLED
330mA
VREF
3V TO 36V
LT3942
28
Rev. 0
For more information www.analog.com
5W (6.5V, 800mA) 2MHz Buck-Boost LED Driver
TYPICAL APPLICATIONS
3942 TA05
+
L1
2.2µH
0.1µF
0.1µF
1µF
402k
280k
120mΩ
1M
124k
M2
2.2µF
100k
0.22µF
100k
14.3k
2MHz
3.3k
2.2nF
0.1µF
100k
91k
332k
122Hz
4.7µF
22µF
22µF
1M
34.8k
100k
110k
BST1
BST2
PV
IN
PV
OUT
EN/UVLO
ISP
ISN
FB
INTV
CC
SSFM ON
NO SSFM/SYNC
SYNC
L1: WURTH ELEKTRONIK 74438336022
M1: VISHAY SI2329DS
3V TO 36V
LT3942
SW2
SW1
V
IN
OVLO
PWMTG
INTV
CC
FAULT
CTRL
ISMON
SYNC/SPRD
V
C
RT
SS
PWM
EXT/ON
INT
V
REF
EXT/ON
INT
RP
GND
FAULT
CURRENT MONITOR
EXT PWM DIM
EXT SYNC
INTVCC
VREF
V
REF
6.5V
LED
800mA
VREF
LT3942
29
Rev. 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
4.00 ±0.10
(2 SIDES)
2.50 REF
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±
0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0816 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50
±0.05
PACKAGE OUTLINE
2.65 ±0.10
3.65 ±0.10
3.65 ±0.05
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
LT3942
30
Rev. 0
For more information www.analog.com
ANALOG DEVICES, INC. 2019
10/19
www.analog.com
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TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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VIN: 4V to 60V, VOUT: 0V to 60V, ±1.5% Voltage Accuracy, ±3% Current Accuracy,
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Sequential Turn and Day Time Running
3942 TA06
+
L1
6.8µH
0.1µF
0.1µF
1µF
1M
34.8k
FB2
ISN
DRAIN
ISP
U1A
VREF
PVOUT
PVIN
383k
10k
M12
56.2k
10k
FB1: TDK MPZ2012S331AT
FB2: TDK MPZ2012S102AT
L1: WURTH ELEKTRONIK 78438357068
M1, M2: ONSEMI 2N7002
M3 - M12: VISHAY Si2318CDS
U1 - U5 ONSEMI NC7WZ16P6X
2.2µF
100k
14.3k
2MHz
2.4k
510k
510k
10µF
33µF
0.1µF
1.5nF
FB1
10µF
4.7µF
102k
402k
BST1
BST2
PVIN
PVOUT
OVLO
100k
54.9k
220nF
VREF
VREF
PWM
INTVCC
CTRL
ISP
ISN
ISP
ISN
FB
INTVCC
SSFM
ON
OFF
LT3942
SW2
SW1
VIN
EN/UVLO
FAULT
INTVCC
SYNC/SPRD
VC
RT
RP
SS
GND
INTVCC
FAULT
6V TO 18V
300mΩ
U1 TO U4
M3 TO M9
AMBER
U5A
M11
WHITE
U5B
M1
M2
0.1µF
15nF
EMIVIN
GND
1µF
5V
VCC
D_IO1
D_IO2
D_IO3
DRAIN
D_IO4
SHUNT1
D_IO5
SHUNT2
D_IO6
SHUNT3
D_IO7
SHUNT4
D_IO8
SHUNT5
D_IO9
SHUNT6
D_IO10
SHUNT7
D_IO11
AMBER
D_IO12
WHITE
µC
GND
D_IO0
FAULT
SHUNT1
M3+U1B
SHUNT2
M4+U2A
SHUNT3
M5+U2B
SHUNT4
M6+U3A
SHUNT5
M7+U3B
SHUNT6
M8+U4A
SHUNT7
M9+U4B
M10
4.7µF
10nF
10nF
PVIN
4.7µF
1nF
5V
IN
OUT
OUT
SENSE
ADJ
REF/BYP
IN
PWRGD
IMAX
GND
LT3065-5
SHDN
4.7k
33nF
33k
5V