83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
1
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83940D is a low skew, 1-to-18 LVPECL-
to-LVCMOS/LVTTL Fanout Buffer and a member
of the HiPerClockS™ f amily of High Performance
Clock Solutions from ICS. The ICS83940D has
two selectable clock inputs. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50Ω series or parallel terminated transmission lines.
The ICS83940D is characterized at full 3.3V and 2.5V or mixed
3.3V core, 2.5V output operating supply modes. Guaranteed
output and part-to-part skew characteristics make the
ICS83940D ideal for those clock distribution applications
demanding well defined performance and repeatability.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
•18 LVCMOS/LVTTL outputs
•Selectable LVCMOS_CLK or LVPECL clock inputs
•PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
•Maximum output frequency: 250MHz
•Output skew: 150ps (maximum)
•Part to part skew: 750ps (maximum)
•Additive phase jitter, RMS: < 0.03ps (typical)
•Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output
supply modes
•0°C to 70°C ambient operating temperature
•Lead-Free package available
•Pin compatible with the MPC940L
HiPerClockS™
ICS
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
Q0:Q17
CLK_SEL
PCLK
nPCLK
LVCMOS_CLK
0
1
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
GND
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
VDD
VDDO
VDDO
Q12
Q13
Q14
GND
Q15
Q16
Q17
GND
Q5
Q4
Q3
VDDO
Q2
Q1
Q0
ICS83940D
18
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
2
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
52,71,21,2,1DNGrewoP.dnuorgylppusrewoP
3KLC_SOMCVLtupnInwodlluP.slevelecafretniLTTVL/SO
MCVL.tupnikcolC
4LES_KLCtupnInwodlluP
kcolcLTTVL/SOMCVLstceleS.tupnitceleskcolC
stupniKLCPn,KLCPstceleS.HGI
Hnehwtupni
.slevelecafretniLTTVL/SOMCVL.WOLnehw
5KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-no
N
6KLCPntupnI /pulluP
nwodlluP
.tupnikcolcLCEPVLlaitnereffidgnitrevnI
V
DD
.gnitaolftfelnehwtluafed2/
12,7V
DD
rewoP.snipylppuseroC
92,61,8V
ODD
rewoP.snipylppustuptuO
,41,31,11,01,9
,22,02,91,81,51
,82,72,62,42,32
23,13,03
,31Q,41Q,51Q,61Q,71Q
,8Q,9Q,0
1Q,11Q,21Q
,3Q,4Q,5Q,6Q,7Q
0Q,1Q,2Q
tuptuO.slevelecafretniLTTVL/SOMCVL.stuptuokcolC
:ETON
nwodlluPdnapulluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
C
DP
ecnaticapaCnoitapissiDrewoP
)tuptuorep( 6Fp
R
puLLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
R
TUO
ecnadepmItuptuO8182Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
tupnIlortnoCkcolC
LES_KLCKLCPn,KLCPKLC_SOMCVL
0detceleSdetceles-eD
1detceles-eDdetceleS
stupnIstuptuO edoMtuptuOottupnIytiraloP
LES_KLCKLC_SOMCVLKLCPKLCPn71Q:0Q
0— 0 1 WOLdednEelgniSotlaitnereffiDgnitrevnIno
N
0— 1 0 HGIHdednEelgniSotlaitnereffiDgnitrevnInoN
0— 0 ;desaiB
1ETON WOLdednEelgniSotdednEelgniSgnitrevnInoN
0— 1 ;desaiB
1ET
ON HGIHdednEelgniSotdednEelgniSgnitrevnInoN
0— 1ETON;desaiB0HGIHdednEelgniSotdednEelgniSgnitrevnI
0— 1ETON;desaiB1WOLde
dnEelgniSotdednEelgniSgnitrevnI
10 ——WOLdednEelgniSotdednEelgniSgnitrevnInoN
11 —— HGIHdednEelgniSotdednEelgniSgnitrevn
InoN
."sleveLdednEelgniStpeccAottupnIlaitnereffiDehtgniriW",noitcesnoitamrofnInoitacilppAehtotreferesa
elP:1ETON
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
3
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 3.6V
Inputs, VI-0.3V to VDD + 0.3V
Outputs, VO-0.3V to VDDO + 0.3V
Input Current, IIN ±20mA
Storage Temperature, T
STG -40°C to 125°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
4
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70°
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnIKLC_SOMCVL4.2V
DD
V
V
LI
egatloVwoLtupnIKLC_SOMCVL8.0V
V
PP
egatloVtupnIkaeP-ot-kaePKLCPn,KLCP0050001Vm
V
RMC
;egatloVedoMnommoCtupnI
2,1ETON KLCPn,KLCPV
DD
4.1-V
DD
6.0-V
I
NI
tnerruCtupnI 002±Aµ
V
HO
egatloVhgiHtuptuOI
HO
Am02-=4.2V
V
LO
egatloVwoLtuptuOI
LO
Am02=5.0V
I
DD
tnerruCylppuSeroC 52Am
siKLCPn,KLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON V
DD
.V3.0+
sadenifedsiegatlovedomnommoC:2ETONV
HI
.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70°
lobmySretemaraPsnoitidnoCtseT -uminiM
mlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 052zHM
t
HLp
yaleDnoitagaporP
;KLCPn,KLCP
5,1ETON f≤zHM0516.10.3sn
;KLC_SOMCVL
5,2ETON f≤zHM0518.10.3sn
t
HLp
yaleDnoitagaporP
;KLCPn,KLCP
5,1ETON f>zHM0516.13.3sn
;KLC_SOMCVL
5,2ETON f>zHM0518.12.3sn
t
)o(ks ;wekStuptuO
5,3ETON
KLCPn,KLCP noderusaeM
V@egdegnisir
ODD
2/
051sp
KLC_SOMCVL 051sp
t
)pp(ks ;wekStraP-ot-traP
6ETON
KLCPn,KLCPf≤zHM0514.1sn
KLC_SOMCVLf≤zHM0512.1sn
t
)pp(ks ;wekStraP-ot-traP
6ETON
KLCPn,KLCPf>zHM0517.1sn
KLC_SOMCVLf>zHM0514.1sn
t
)pp(ks ;wekStraP-ot-traP
5,4ETON
KLCPn,KLCP noderusaeM
V@egdegnisir
ODD
2/
058sp
KLC_SOMCVL 057sp
t
tij
;SMR,rettiJesahPevitiddAreffuB
,noitcesrettiJesahPevitiddAotrefer
7ETON
30.0sp
t
R
/t
F
emiTllaF/esiRtuptuOV4.2ot5.03.01.1sn
cdoelcyCytuDtuptuO f<zHM431540555%
zHM431 ≤f≤zHM052040506%
taderusaemsretemarapllAz
HM002.esiwrehtodetonsselnu
uptuoehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETONVt
ODD
.2/
VmorfderusaeM:2ETON
DD
Vot2/
ODD
.2/
VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON
ODD
.2/
,erutarepmetemas,segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:4ET
ON
Vtaderusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
ODD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:5ETON
lauqehtiwdna,segnaregatlovdnaerutarepm
etssorca,secivedtnereffidnostuptuoneewtebwekssadenifeD:6ETON
taderusaemerastuptuoeht,ecivedhcaenostupn
ifoepytemasehtgnisU.snoitidnocdaol V
ODD
.2/
.kcolctupnienoylnognivirD:7ETON
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
5
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70°
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70°
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnIKLC_SOMCVL4.2V
DD
V
V
LI
egatloVwoLtupnIKLC_SOMCVL8.0V
V
PP
egatloVtupnIkaeP-ot-kaePKLCPn,KLCP0030001Vm
V
RMC
;egatloVedoMnommoCtupnI
2,1ETON KLCPn,KLCPV
DD
4.1-V
DD
6.0-V
I
NI
tnerruCtupnI 002±Aµ
V
HO
egatloVhgiHtuptuOI
HO
Am02-=8.1V
V
LO
egatloVwoLtuptuOI
LO
Am02=5.0V
I
DD
tnerruCylppuSeroC 52Am
siKLCPn,KLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON V
DD
.V3.0+
sadenifedsiegatlovedomnommoC:2ETONV
HI
.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 052zHM
t
HLp
yaleDnoitagaporP
;KLCPn,KLCP
5,1ETON f≤zHM0517.12.3sn
;KLC_SOMCVL
5,2ETON f≤zHM0517.10.3sn
t
HLp
yaleDnoitagaporP
;KLCPn,KLCP
5,1ETON f>zHM0516.14.3sn
;KLC_SOMCVL
5,2ETON f>zHM0518.13.3sn
t
)o(ks ;wekStuptuO
5,3ETON
KLCPn,KLCP noderusaeM
V@egdegnisir
ODD
2/
051sp
KLC_SOMCVL 051sp
t
)pp(ks ;wekStraP-ot-traP
6ETON
KLCPn,KLCPf≤zHM0515.1sn
KLC_SOMCVLf≤zHM0513.1sn
t
)pp(ks ;wekStraP-ot-traP
6ETON
KLCPn,KLCPf>zHM0518.1sn
KLC_SOMCVLf>zHM0515.1sn
t
)pp(ks ;wekStraP-ot-traP
5,4ETON
KLCPn,KLCP noderusaeM
V@egdegnisir
ODD
2/
058sp
KLC_SOMCVL 057sp
t
tij
;SMR,rettiJesahPevitiddAreffuB
,noitcesrettiJesahPevitiddAotrefer
7ETON
30.0sp
t
R
/t
F
emiTllaF/esiRtuptuOV8.1ot5.03.02.1sn
cdoelcyCytuDtuptuOf<zHM431540555%
taderusaemsretemarapllAzHM002.esiwrehtodeton
sselnu
uptuoehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETONVt
ODD
.2/
VmorfderusaeM:2ETON
DD
Vot2/
ODD
.2/
VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON
ODD
.2/
,erutarepmetemas,segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:4ET
ON
Vtaderusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
ODD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:5ETON
lauqehtiwdna,segnaregatlovdnaerutarepm
etssorca,secivedtnereffidnostuptuoneewtebwekssadenifeD:6ETON
taderusaemerastuptuoeht,ecivedhcaenostupn
ifoepytemasehtgnisU.snoitidnocdaol V
ODD
.2/
.kcolctupnienoylnognivirD:7ETON
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
6
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70°
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnIKLC_SOMCVL2V
DD
V
V
LI
egatloVwoLtupnIKLC_SOMCVL8.0V
V
PP
kaeP-ot-kaeP
egatloVtupnI KLCPn,KLCP0030001Vm
V
RMC
;egatloVedoMnommoCtupnI
2,1ETON KLCPn,KLCPV
DD
4.1-V
DD
6.0-V
I
NI
tnerruCtupnI 002±Aµ
V
HO
egatloVhgiHtuptuOI
HO
Am21-=8.1V
V
LO
egatloVwoLtuptuOI
LO
Am21=5.0V
I
DD
tnerruCylppuSeroC 52Am
siKLCPn,KLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON V
DD
.V3.0+
sadenifedsiegatlovedomnommoC:2ETONV
HI
.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70°
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 002zHM
t
HLp
;yaleDnoitagaporP
;KLCPn,KLCP
5,1ETON f≤zHM0512.18.3sn
;KLC_SOMCVL
5,2ETON f≤zHM0515.12.3sn
t
HLp
;yaleDnoitagaporP
;KLCPn,KLCP
5,1ETON f>zHM0515.17.3sn
;KLC_SOMCVL
5,2ETON f>zHM05126.3sn
t
)o(ks ;wekStuptuO
5,3ETON
KLCPn,KLCP noderusaeM
V@egdegnisir
ODD
2/
002sp
KLC_SOMCVL 002sp
t
)pp(ks ;wekStraP-ot-traP
6ETON
KLCPn,KLCPf≤zHM0516.2sn
KLC_SOMCVLf≤zHM0517.1sn
t
)pp(ks ;wekStraP-ot-traP
6ETON
KLCPn,KLCPf>zHM0512.2sn
KLC_SOMCVLf>zHM0517.1sn
t
)pp(ks ;wekStraP-ot-traP
5,4ETON
KLCPn,KLCP noderusaeM
V@egdegnisir
ODD
2/
2.1sn
KLC_SOMCVL 0.1sn
t
tij
;SMR,rettiJesahPevitiddAreffuB
,noitcesrettiJesahPevitiddAotrefer
7ETON
30.0sp
t
R
t/
F
emiTllaF/esiRtuptuOV8.1ot5.03.02.1sn
cdoelcyCytuDtuptuOf<zHM4315455%
taderusaemsretemarapllAzHM002.esiwrehtodetons
selnu
uptuoehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETONVt
ODD
.2/
VmorfderusaeM:2ETON
DD
Vot2/
ODD
.2/
VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON
ODD
.2/
,erutarepmetemas,segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:4ET
ON
Vtaderusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
ODD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:5ETON
,segnaregatlovdnaerutarepmetssorca,sec
ivedtnereffidnostuptuoneewtebwekssadenifeD:6ETON
taderusaemerastuptuoeht,ecivedhcaenostupnifoepytemase
htgnisU.snoitidnocdaollauqehtiwdna V
ODD
.2/
.kcolctupnienoylnognivirD7ETON
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
7
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
Input/Output Additive Phase Jitter
at 155.52MHz = 0.03ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
8
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2.5V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V±5%
VDDO
-1.25V±5%
VDD
1.25V±5%
GND
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
VDD,
VDDO
1.65V±5%
-1.65V±5%
GND
DIFFERENTIAL INPUT LEVEL
PART-TO-PART SKEW OUTPUT SKEW
t
sk(o)
V
DDO
2
V
DDO
2
Qy
Qx
SCOPE
Qx
LVCMOS
VDD,
VDDO
1.25V±5%
-1.25V±5%
GND
V
CMR
Cross Points
V
PP
GND
PCLK
nPCLK
VDD
t
sk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
PA RT 2
PART 1
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
9
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
PROPAGATION DELAY
Q0:Q17
3.3V OUTPUT RISE/FALL TIME
Clock Outputs
0.5V
2.4V 2.4V
0.5V
tRtF
2.5V OUTPUT RISE/FALL TIME
Clock Outputs
0.5V
1.8V 1.8V
0.5V
t
R
t
F
t
PD
V
DDO
2
➤
➤
V
DD
2
PCLK
nPCLK
LVCMOS_CLK
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
10
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
APPLICATION INFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R2
1K
V_REF
C1
0.1u
R1
1K
Single Ended Clock Input
PCLK
nPCLK
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
11
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements.
Figures 2A to 2F
show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
mination requirements.
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
PCLK/nPCLK
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
HiPerClockS
PCLK
nPCLK
PCLK/nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
PCLK
nPCLK
R2
84
R3
125
Input
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
C2
R2
1K
R5
100
Zo = 50 Ohm
3.3V
3.3V
C1
R3
1K
LVDS
R4
1K
HiPerClockS
PCLK
nPCLK
R1
1K
Zo = 50 Ohm
3.3V
PCLK/nPCLK
3.3V
R5
100 - 200
3.3V
3.3V
HiPerClockS
PCLK
nPCLK
R1
125
PCLK/nPCLK
R2
125
R3
84
C1
C2
Zo = 50 Ohm
R4
84
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
Zo = 50 Ohm
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
12
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS83940D is: 820
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
13
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS
ABB
MUMINIMLANIMONMUMIXAM
N23
A----06.1
1A 50.0--51.0
2A 53.104.154.1
b03.073.054.0
c90.0--02.0
DCISAB00.9
1D CISAB00.7
2D .feR06.5
ECISAB00.9
1E CISAB00.7
2E .feR06.5
eCISAB08.0
L54.006.057.
0
θθ
θ
θθ 0
°
-- 7
°
ccc ----01.0
Reference Document: JEDEC Publication 95, MS-026
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
14
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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YD04938SCIYD04938SCIPFQLdaeL23yartrep052C°07otC°0
TYD04938SCIYD04
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The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
83940DY www.icst.com/products/hiperclocks.html REV. B JUNE 15, 2004
15
Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
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