1. THOMSON COMPOSANTS MILITAIRES ET SPATIAUX EF 6850 NMOS ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER (ACIA) DESCRIPTION . The EF 6850 Asynchronous Communications Interface Adapter provides the data formatting and contro! to inter- face serial asynchronous data communications information to bus organized systems such as the EF 6800 Microproces- sing Unit. The bus interface of the EF 6850 includes select, enable, read/write, interrupt and bus interface logic to allow data transfer over an &-bit bidirectional and data bus. The paral- lel data of the bus system is serially transmitted and recei- ved by the asynchronous data interface, with proper format- ting and error checking. The functional configuration of the ACIA is programmed via the data bus during system initiali- zation. A programmable Control Register provides variable word lengths, clock division ratios, transmit control, receive control, and interrupt contro{. For peripheral or modem ope- tation, three control lines are provided. MAIN FEATURES wm 8- and 9-bit transmission, w Optional even and odd parity. w Parity, overrun and framing error checking. m Programmable contro! register. @ Optional +1, +16 and +64 clock modes. @ Up to 1.0 Mbps transmission. False start bit deletion. @ Peripheralfmodem contro! functions. m Double buffered. m One- or two-stop bit operation. @ Three available versions : EF 6850 (1.0 MHz), EF 68A50 (1.5 MHz), EF 68B50 (2 MHz) - 0C to 70C only. SCREENING / QUALITY This product is manufactured in full compliance with either : m@ MIL-STD-883 class B. m@ NFC 96863 class G. or according to TMS standards. July 1992 Ceramic Cerdip package J suffix DIL 24 C suffix DIL 26 Ceramic Side Brazed package itary Leadless Ceramic Chip Carrier package E suffix LOCC 28 See the ordering Information 11. Pin connection : see 10. THCSS00156 1/20EF 6850 SUMMARY A - GENERAL DESCRIPTION B - DETAILED SPECIFICATIONS 1 - SCOPE 2 - APPLICABLE DOCUMENTS 2.1 - MIL-STD-883 3 - REQUIREMENTS 3.1 - General 3.2 - Design and construction 3.3 - Electrical characteristics 3.4 - Thermal characteristics 3.5 - Mechanical and environment 3.6 - Marking 4 - QUALITY CONFORMANCE INSPECTION 4.1 - MIL-STD-883 5 - ELECTRICAL CHARACTERISTICS 5.1 - General requirements 5.2 - Static characteristics 5.3 - Dynamic (switching) characteristics 6 - FUNCTIONAL DESCRIPTION 6.1 - Device operation 6.2 - Input/output functions 6.3 - ACIA registers 7 - PREPARATION FOR DELIVERY 7.1 - Packaging 7.2 - Certificate of compliance 8 - HANDLING 9 - PACKAGE MECHANICAL DATA 9.1 - 24 pins - DIL Ceramic Side Brazed package 9.2 - 24 pins - DIL Cerdip package 9.3 - 28 pins - Leadless Ceramic Chip Carrier package 10 - TERMINAL CONNECTIONS 10.1 - 24 pins - Pin assignment (DIL) 10.2 - 28 pins - Pin assignment (LCCC) 11 - ORDERING INFORMATION 11.1 - Hi-REL product 11.2 - Standard product 2/20 4.\ THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 A - GENERAL DESCRIPTION Data OataBus <--> Bus | ? Figure 2: Clock pulse width, low-state. Figure 3: Clock pulse width, high-state. es Tu Chk \ SY Rx Oata 5 Co 'trpo ~~ _> . tADS Tx Data Rx Clock Figure 4: Transmit data output delay. Figure 5: Receive data setup time (+ 1 Mode). . . ae / Enable \ Rx Cik {. preg oN | ers x Rx Oata . < 1A_> Figure 6 : Receive data hold time (+1 Mode). __ = . RQ / Figure 7: Request-to-send delay and interrupt-request release times. Note : Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. 7120 1.\ THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 Table 5 - Bus timing characteristics - see Notes 1, 2 and Figure 8 Ident. ; EF 6850 EF 68A50 EF 68B50 Number Symbol Characteristic Min Max Min Max Min Max Unit 1 toyc Cycle time 1.0 10 0.67 10 0.5 10 us 2 PWEL Pulse width, E low 430 9500 280 9500 210 9500 ns 3 PWEH Pulse width, E high 450 9500 280 9500 220 9500 ns 4 tr, tt Clock rise and fall time 25 25 20 ns 9 taH Address hold time 10 10 10 ns 13 tas | Ratress setuo time 80 60 40 ns 14 tcs boo setup time 80 60 40 ns 15 tCH Chip select hold time 10 10 10 ns 18 tDHR Read data hold time 20 50* 20 50 20 50* ns 21 tpHW Write data hold time 10 10 10 ns 30 tppDR Output data delay time . 290 180 150 ns 31 tosw Input data setput time 165 80 60 ns * The data bus output buffers are not longer sourcing or sinking current by toHR Max (high impedance). Note 1: Voltage levels shown are Vi < 0.4V, VH > 2.4 V, unless otherwise specified. Note 2: Measurements points shown are 0.8 V and 2.0 V, unless otherwise specified. 8/20 1. Voltage levels shown are V; <0.4 V, Vij2 2.4 V, unless otherwise specified. 2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified. 1 R/W, Address (Non-Muxed) cs Read Data MPU Read Data Non-Muxed Non-Muxed Write Data MPU White Data Non-Muxed Muxed Figure 8: Bus timing characteristics. Load A Load B (00-07, ATS, Tx Data) (iRQ Only} SOV $0V RL = 2.5 kO 30 Tast Pont 1N414B Test Point or Equiv. a 100 pF 1N916 or equiv. Ce 130nF tor DOO? R= 11.7kN for 60-07 | = 30 pF tor ATS and Ta Data = 24 kM tor RTS and Tx Oste Figure 9: Bus timing test loads. 4.8 THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 6 - FUNCTIONAL DESCRIPTION Tranemit Clock 4 Cloch Parity Gen Gen Enable 14 F ~ F ReadWrite 13 -h Chip Chip Select O 8 Pi Select Transmit Transmit Chip Select 110 By ond Data Shift nnn 6G Tranemt Date Chip Select 2. 9 C)AesdWiie Register Register Register Select 11 r| Controt f ~ Transmit Control 24 Clear to-Send DO 22 <-> Status c__ } 0121 <> Kc Regi D2 20 <-> we cole O 7 Interrupt Request 03 19 ~i-py (ate a Bus . pats Butters 23 Data Carcier Detect 05 17

) D- > 5 Request to Send O7 18 <>! Contral | Register Receive Parity Control Check a v j v = Pin 12 Receive Receive . Ves= Pin 1 : ! Data om Shift + 2 Receive Osta Register Register f Clock Sync Gea Le] Logic a Receive Ctock 3 Figure 10: Expanded block diagram. - Device operation A the bus interface, the ACIA appears as two addressable memory locations. Internally, there are four registers : two read- only and two write-only registers. The read-only registers are Status and Receive Data ; the write-only registers are Control and Transmit Data. The seria! interface consists of serial input and output lines with independent clocks, and three periphera!/mo- dem control lines. 6.1.1 - Power on/master reset The master reset (CRO, CR1) should be set during system initialization to insure the reset condition and prepare for program- ming the ACAI functional configuration when the communications channel is required. During the first master reset, the [RQ and RTS outputs are held at level 1. On all other master resets, the RTS output can be programmed high or low with the IRQ output held high. Control bits CR5 and CR6 should also be programmed to define the state of RTS whenever master reset is utilized. The ACIA also contains internal power-on reset logic to detect the power line turn-on transition and hold the chip in a reset state to prevent erroneous output transitions prior to initialization. This circuity depends on clean power turn on transi- tions. The power-on reset released by means of the bus-programmed master reset which must be applied prior to operating the: ACIA. After master resetting the ACIA, the programmable Control Register can be set for a number of options such as variable clock divider rations, variable word-length, one or two stop bits, parity (even, odd, or none), etc. 6.1.2 - Transmit A typical transmitting sequence consists of reading the ACIA Status Register either as a result of an interrupt or in the ACIAs turn in a polling sequence. A character may be written into the Transmit Data Register if the status read operation has indica- ted that the Transmit Data Register is empty. This character is transferred to a Shift Register where it is serialized and trans- mitted from the Transmit Data output preceded by a start bit and followed by one or two stop bits. Internal parity (odd or even) can be optionally added to the character and will occur between the last data bit and the first stop bit. After the first character is written in the Data Register, the Status Register can be read again to check for a Transmit Data Register Empty condition and current peripheral status. If the register is empty, another character can be loaded for transmission even through the first character is in the process of being transmitted (because of double buffering). The second character will be automatically transterred into the Shift Register when the first character transmission is completed. This sequence continues until all the characters have been transmitted. 6.1.3 - Receive Data is received from a peripheral by means of the Receive Data input. A divide-by-one clock ratio is provided for an externally synchronized clock (to its data) while the divide-by-16 and 64 ratios are provided for internal synchronization. Bit synchroniza- tion in the divide-by-16 and 64 modes is initiated by the detection of 8 or 32 low samples on the receive line in the divide-by-16 and 64 modes respectively. False start bit deletion capability insures that a full half bit of a start bit has been received before 9/20 1. THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 4 the internal clock is synchronized to the bit time. As a character is being received, parity (odd or even) will be checked and the error indication will be available in the Status Register along with framing error, overrun error, and Receive Data Register full. in a typical receiving sequence, the Status Register is read to determine if a character has been received from a peripheral. If the Receiver Data Register is full, the character is placed on the 8-bit ACIA bus when a Read Data command is received from the MPU. When parity has been selected for a 7-bit word (7 bits plus parity), the receiver strips the parity bit (D7 = 0) so that data alone is transferred to the MPU. This feature reduces MPU pragramming. The Status Register can continue to be read to determine when another character is available in the Receive Data Register. The receiver is also double buffered so that a cha- racter can be read from the data register as another character is being received in the shift register. The above sequence conti- nues until alf characters have been received. 6.2 - Input/output functions 6.2.1 - ACIA interface signals for MPU The ACIA interfaces to the 6800 MPU with an 8-bit bidirectional data bus, three chip select lines, a register select line, an inter- rupt request line, read/write line, and enable line. These signals permit the MPU to have complete contro! over the ACIA. ACIA Bidirectional Data (DO-D7) - The bidirectional data lines (D0-D7) allow for data transfer between the ACIA and the MPU. The data bus output drivers are three-state devices that remain in the high-impedance (off) state except when the MPU per- forms an ACIA read operation. wot ACIA Enable (E} - The Enable signal, E, is a high-impedance TTL-compatible input that enables the bus input/output data buf- fers and clocks data to and from the ACIA. This signal will normally be a derivative of the EF 6800 #9 Clock or EF 6809E clock. Read/Write (RW) - The Read/Mrite line is a high-impedance input that is TTL compatible and is used to control the direction of data flow through the ACIAs input/output data bus interface. When Read/Write is high (MPU Read cycte), ACIA output dri- vers are turned on and a selected register is read. When it is low, the ACIA output drivers are turned off and the MPU writes into a selected register. Therefore, the Read/Write signal is used to select read only or write-only registers within the ACIA. Chip Select (CSO, CS1, CS2) - These three high-impedance TTL-compatible input lines are used to address the ACIA. The ACIA is selected when CSO and CS1 are high and. is low. Transfers of data to and from the ACIA are then performed under the control of the Enable Signal, Read Write, and Register Select. Register Sefect (RS) - The Register Select is a high-impedance input that is TTL compatible. A high level is used to select the Transmit/Receive Data Registers and a low level the Control/Status Registers. The Read/Write signal line is used in conjuction with Register Select to select the read-only or write-only register in each register pair. Interupt Request (IRQ) - Interrupt Request is a TTL-compatible, open-drain (no internal pullup), active Jow output that is used to interrupt the MPU. The IRQ output_ remains low as long as the cause of the interrupt is present and the appropriate interrupt enable within the ACIA is set. The {RQ status bit, when high, indicates the (RO outputs is in the active state. Interrupts result from conditions in both the transmitter and receiver sections of the ACIA. The transmitter section causes an interrupt when the Transmitter Interrupt Enabled condition is selected (CR5eCR6), and the Transmit Data Register Empty (TDRE) status bit is high.The TDRE status bit indicates the current status of the Transmitter Data Register except when inhibi- ted by Clear-to-Send (CTS) being high or the ACIA being maintained in the Reset condition. The interrupt is cleared by writting data into the Transmit Data Register. The interrupt is masked by disabling the Transmitter Interrupt via CR5 or CR6 or by the loss of CTS which inhibits the TORE status bits. The Receiver section causes an interrupt when the Receiver Interrupt Enable is set and the Receive Data Register Fuil (RDRF) status bit is high, an Overrun has occured, or Data Carrier Detect (DCD) has gone high. An interrupt resulting from the RORF status bit can bi cleared by reading data or resetting the ACIA. Interrupts cau- sed by Overrun or lou: of DCD are cleared by reading the status register after the error condition has occurred an then reading the Receive Data Register or reseting the ACIA. The receiver interrupt is masked by resetting the Receiver Interrupt Enable. 6.2.2 - Clock inputs Separate high-impedance TTl-compatible Inputs are provided for clocking of transmitted and received data. Clock frequencies of 1, 16, or 64 times the data rate may be selected. Transmit Clock (Tx CLK) - The Transmit Clock input is used for the clocking of transmitted data. The transmitter initiates data on the negative transition of the clock. a Receive Clock (Rx CLK) - The Receive Clock input is used for synchronization of received data. (In the + 1 mode, the clock and data must be synchronized externally). The receiver samples the data on the positive transition of the clock. 6.2.3 - Serial input/output lines . Receive Data (RX Data) - The Receive Data is a high-impedance TTL-compatible input through which data is received a serial format. Synchronization with a clock for detection of data is accomplished Internally when clock rates of 16 or 64 times the bit rate are used. Transmit Data (Tx Data) - The Transmit Data ouptut line transfers serial to a modem or other peripheral. 6.2.4 - Peripheral/modem controi The ACIA includes several functions that permit limited contro! of a peripheral or modem. The functions included are Clear-to- Send, Request-to-Send and Data Carrier Detect. Clear-to-Send (CTS) - This high-impedance TTL-compatible input provides automatic control of the transmitting end of a com- munications link via the modem Clear-to-Send active low output by inhibiting the Transmit Data Register Empty (TDRE) status bit. 10/20 1 THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 Request:to'Send (RTS) - The Request-to-Send output enables the MPU to control a peripheral or modem via the data bus. The RTS output corresponds to the state of the Control Register bits CR5 and CR6. When CR6 = 0 or both CR5 and CR6 = 1, the RTS output is low (the active state). This output can also be used for Data Terminal Ready (DTR). Data Carrier Detect (DCD) - This high-impedance TTL-compatible input provides automatic control, such as in the receiving end of a communications link by means of a modem Data Carrier Detect output. The DCD Input inhibits and initializes the re- ceiver section of the ACIA when high. A low-to-high transition of the Data Carrier Detect initiates an interrupt to the MPU to indicate the occurence of a loss of carrier when the Receive Interrupt Enable bit is set. The Rx CLK must be running for proper DCD operation. 6.3 - ACIA registers The expanded block diagram for the ACIA indicates the internal registers on the chip that are used for the status, control, re- ceiving, and transmitting of data. The content of each of the registers is summarized in Table 6. 6.3.1 - Transmit data register (TOR) Data is written in the Transmit Data Register during the negative transition of enable (E) when the ACIA has been addressed with RS high and R/W low. Writing data into the register causes the Transmit Data Register Empty bit in the Status Register to go low. Data can then be transmitted. If the transmitter is idling and no,character is being transmitted, then the transfer will take place within 1-bit time of the trailing edge of the Write command. If a character is being transmitted, the new data charac- ter will commence as soon as the previous character is complete. The transfer of data causes the Transmit Data Register Empty (TDRE) bit to indicate empty. 6.3.2 - Receive data register (RDR) Data is automatically transferred to the empty Receive Data Register (RDR) from the receiver deserializer (a shift register) upon receiving a complete character. This event causes the Receive Data Register Full bit (RORF) in the status buffer to go high (full). Data may then be read through the bus by addressing the ACIA and selecting the Receive Data Register with RS and R/W high when the ACIA is enabled. The non-destructive read cycle causes the RDRF bit to be cleared to empty although the data is retained in the ROR. The status is maintained by RDRF as to whether or not the data is current. When the Receive Data Re- gister is full, the automatic transfer of data from the Receiver Shift Register to the Data register is inhibited and the ROR con- tents remain valid with its current status stored in the Status Register. Table 6 - Definition of ACIA register contents Buffer address Data bus RS RIW RS RW RS + RW RS RW line number Transmit Receive Control Status register register register register (Write only) (Read only) (Write only) (Read only) . . Counter Divide Receive Data Register Data Bit 0* ata Bit Data Bit 0 Select 1 (CRO) Full (RDRF) . ; Counter Divide Transmit Data Register Data B 1 ata Bit 1 Data Bit 1 Select 2 (CR1) Empty (TDRE) . Word Select 1 Data Carrier Detect Data Bit 2 it 2 2 ja it Data Bit (CR2) (DCD) Word Select 2 Clear to Send : Data Bi : r to. 3 ata Bit 3 Data Bit 3 (CR3) (GTS) : : Word Select 3 Framing Error D. B 4 ata Bit 4 Data Bit 4 (CR4) (FE) Transmit Control 1 Receiver Overrun Data Bi i 5 ata Bit 5 Data Bit 5 (CRS) (OVRN) 6 Data Bit 6 Data Bit 6 Transmit Control 2 Parity Error (PE) (CR6} ae +) pane Receive Interrupt Interrupt Request 7 Data Bit 7 Data Bit 7 Enable (CR7) (IRQ) * Leading bit = LSB = Bit 0. ** Data bit is don't care in 7-bit plus parity modes. ** Data bit will be zero in 7-bit plus parity modes. 11/20 1,\ THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 6.3.3 - Control register The ACIA Control Register consists of eight bits of write-only buffer that are selected when RS and RIW are low. This register controls the function of the receiver, transmitter, interrupt enables, and the Request-to-Send peripheral/modem contro} out- put. Counter Divide Select Bits (CRO and CR1) - The Counter Divide Select Bits (CRO and CR1) determine the divide ratios utilized in both the transmitter and receiver sections of the ACIA. Additionally, these bits are used to provide a master reset for the ACIA which clears the Status Register {except for external conditions on CTS and DCD) and initializes both the receiver and transmitter. Master reset does not affect other Control Register bits. Note that after power-on or a power fail/restart, these bits must be set high to reset the ACIA. After resetting, the clock divide ratio may be selected. These counter select bits provide for the following clock divide ratios : CR1i | CRO Function 0 0 +1 0 1 +16 1 0 +64... > 1 1 Master Reset Word Select Bits (CR2, CR3, and CR4) - The Word Select bits are used to select word length, parity, and the number of stop bits. The encoding format is as follows: Word tenth , Parity Select, and Stop Bit changes are not buffered and therefore become effective immediately. cra | cr3 | cre Function 0 |7 Bits + Even Parity + 2 Stop Bits 7 Bits + Odd Parity + 2 Stop Bits ? Bits + Even Parity + 1 Stop Bit 7 Bits + Odd Parity + 1 Stop Bit 8 Bits + 2 Stop Bits 8 Bits + 1 Stop Bit 8 Bits + Even Parity + 1 Stop Bit 8 Bits + Odd Parity + 1 Stop Bit ~s wt Bt OOO 8 et aot OO 2B = CO CO ~ Of OF CO = Transmitter Control Bits (CR5 and CR6) - Two Transmitter Control bits provide for the control of the interrupt from the Trans- mit Data Register Empty condition, the Request-to-Send (ATS) output, and the transmission of a Break fevel (space). The follo- wing encoding format is used: CR6 | CR5 Function 0 0 | RTS = tow, Transmitting Interrupt Disabled 1 | ATS = low, Transmitting Interrupt Enabled 1 0 | RTS = high, Transmitting Interrupt Disabled 1 1 RTS = low, Transmits a Break level on the Transmit Data Output. Transmitting Interrupt Disabled Receive Interrupt Enable Bit (CR7) - The following interrupts will be enabled by a high level in bit position 7 of the Control Re- gister (CR7): Receive Data Register Full, Overrun, or a low-to-high transition on the Data Carrier Detect (DCD) signal line. 6.3.4 - Status register Information on the status of the ACIA is available to the MPU by reading the ACIA Status Register. This read-only register is selected when RS is low and R/W is high. information stored in this register indicates the status of the Transmit Data Register, the Receive Data Register and error logic, and the peripheralimodem status Inputs of the ACIA. Receive Data Register Full (RDRF), Bit 0 - Receive Data Register Full indicates that received data has been transferred to the Receive Data Register. RDRF is cleared after an MPU read of the Receive Data Register or by a master reset. The cleared or empty state indicates that the contents of the Receive Data Register are not current. Data Carrier Detect being high also cau- ses RDRF to indicate empty. 12/20 4. THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 t Transmit Data Register Empty (TDRE), Bit 1 - The Transmit Data Register Empty bit being set high indicates that the Transmit Data Register contents have been transferred and that new data may be entered. The low state indicates that the register is fult and that transmission of a new character has not begun since the last write data command. Data Carrier Detect (DCD), Bit 2 - The Data Carrier Detect bit wil! be high when the DCD input from a modem has gone high to indicate that a carrier is not present. This bitgoing high causes an Interrupt Request to be generated when the Receive Inter- rupt Enable is set. It remains high after the DCD input is returned low until cleared by first reading the Status Register and then the Data Register or until a master reset occurs. If the DCD input remains high after read status and read data or master reset has occurred, the interrupt is cleared, the OCD status bit remains high and will follow the OCD input. Clear-to-Send (CTS), Bit 3 - The Clear-to-Send bit indicates the state of the Clear-to-Send input from a modem. A low CTS indi- cates that there is a Clear-to-Send from the modem. In the high state, the Transmit Data Register Empty bit is inhibited and the Clear-to-Send status bit wifl be high Master reset does not affect the Ciear-to-Send status bit. Framing Error (FE), Bit 4 - Framing error indicates that the received character In improperly framed by a start and a stop bit and is detected by the absence of the first stop bit. This error indicates a synchronization error, fauity tranmission, or a break condition. The framing error flag is set or reset during the receive data transfer time. Therefore, this error indicator is present throught the time that the associated character is avaitabie. 7 . Receiver Overrun (OVRN), Bit 5 - Overrun is an error flag that indicates that one or more characters in the data stream were lost. That is, a character or number of characters were received but not read from the Receive Data Register (RDR) prior to sub- sequent characters being received. The overrun condition begins at the midpoint of the last bit of the second character recei- ved in succession without a read of the RDR having occured. The Overrun does not occur in the Status Register until the valid character prior to Overrun has been read. The RDRF bit remains set until the Overrun is reset. Character synchronization is maintained during the Overrun condition. The Overrun indication is reset after the reading of data from the Receive Data Re- gister or by a Master Reset. Parity Error (PE), Bit 6 - The parity error flag indicates that the number of highs (ones) in the character does not agree with the preselected odd or even parity. Odd parity is defined to be when the total number of ones is odd. The parity error indication will be present as long as the data characteris in the RDR. if no parity selected, then both the transmitter parity generator ou- tupt and the receiver parity check results are inhibited. Interrupt Request (IRQ), Bit 7 - The IRQ bit indicates the state of the IRQ output. Any interrupt condition with its applicable enable will be indicated_in this status bit. Anytime the IRQ output is low the IRQ bit will be high to indicate the interrupt or service request status. [RQ is cleared by a read operation to the Receive Data Register or a write operation to the Transmit Data Register. 3/20 4. THOMSON COMPOSANTS MILITAIRES ET SPATIAUX !EF 6850 7 - PREPARATION FOR DELIVERY 7.1 - Packaging Microcircuit are prepared for delivery in accordance with MIL-M-38510 or CECC 90000. 7.2 - Certificate of compliance TMS offers a certificate of compliance with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 or CECC 90000 and guarantying the parameters are tested at extreme temperatures for the entire temperature range. 8 - HANDLING MOS device must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended : a) Device should be handled on benches with conductive and grounded surface. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50 %, if pratical. ~ 7 of = /.8 THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 . 4 9 - PACKAGE MECHANICAL DATA . 9.1 - 24 pins - DIL Ceramic Side Brazed package aim on a8 Sis als =|2 cle oles vit g x = = 3c oln Nhs SIai al 1 S| lo TY 100 +005 | | O18 2.002 0107? 2.54 20.13 0.46 +0.05 -of.____-.001 won " +0.05 0.25 5 gos .600 Typ 4 peo eo 15.24 Typ alS So - sla ) + Ma Q See ees 1 \ : 12 Pin N 1 index { 1.200 2.012 30.48 0.30 9.2 - 24 pins - DIL Cerdip package ; alr : Sls we S15 oy tT oI S| eS .100 +.002 .018 +.002 2.54 0.05 0.46 0.05 24 13 .700 +.015 Po ot fy dh Ay Ay Ay ty ch th th 17.78 20.38 8 2 3 4 H ale . + 12 a a a a a ae a a a ea | 1 12 1.250 +.010 31.75 20.25 15/20 1. THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 9.3 - 28 pins - Leadiess Ceramic Chip Carrier package TOP VIEW BOTTOM VIEW -080 +.007 2.03 20.18 18 12 19 tt me ma elke = ae P29 ol, s'| 2 + eye 7 8 mn Pin N1 index 25 5 i TF 26 1 4 .010 . 450. 995 .065 2.007 025 Typ +0.25 . 1.65 +0.18 0.64 Typ 11.43 943 ; t 10 - TERMINAL CONNECTIONS 10.1 - 24 pins - Pin assignment (DIL) 10.2 - 28 pins - Pin assignment (LCCC) Vss C1 24) CTS RxData [_}2 ma DCD AxCLK [7]3 Do TxCLK 4 01 NC _ NC ATs CJs5 02 Ne TxData (6 r} 3 ars ind C7 FI D4 TxData cso (|s ] 05 ino cs2 (Jo 7 pe cso csi J 7 RS Ie Voc ] Aw 16/20 1.) THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 11 - ORDERING INFORMATION 11.1 - Hi-REL product etna Norms Package Tomperneg range Pry Drawing number (see Note) EF6850JMG/B NFC 96863 class G DIL Cerdip 55/ +125 1 Data sheet EF6850CMG/B* NFC 96863 class G DIL Side Brazed ~55/ +125 1 Data sheet EF6850EMG/B NFC 96863 class G LCCC 55/ +125 1 Data sheet EF68AS50JMG/B NFC 96863 class G Dit. Cerdip 65/ +125 1.5 Data sheet EF68A50CMG/B* NFC 96863 class G DIL Side Brazed 55/ 4125 1.5 Data sheet EF68A50EMG/B NFC 96863 class G LCCC veep 7557 +125 1.5 Data sheet EF6850JMB/C MIL-STD-883 class B DIL Cerdip 55/ +125 1 Data sheet EF6850C1MB/C* MIL-STD-883 class B DIL Side Brazed ~55/ +125 1 Data sheet EF6850E1MB/C MIL-STD-883 class B LCCC 55/ +125 1 Data sheet EF68AS0JMB/C MIL-STD-883 class B | DIL Cerdip 55/ +125 15 Data sheet EF68A50C1MB/C* MIL-STD-883 class 8 _s{- DIL. Side Srazed 55/ +125 1.5 Data sheet EF68ASOEMB/T MILSTDS89 class B | ECCC 55} +125 15 Data sheet * Non considered anymore as standard package, Cerdip is preferred. Note : THOMSON COMPOSANTS MILITAIRES ET SPATIAUX. 11.2 - Standard product CopartNumber Norms Package romped) range Frequency Drawing number (see Note) EF6850CV* TMS standard DIL Side Brazed 40/ +85 1 Data sheet EF6850JV TMS standard DIL Cerdip ~-~40/ +85 1 Data sheet EF68A50CV* TMS standard DIL Side Brazed -40/ +85 1.5 Data sheet EF68A50J/V TMS standard DIL Cerdip -~40/ +85 1.5 Data sheet EF6850JM TMS standard DIL Cerdip 55/ +125 1 Data sheet EF6850CM* TMS standard DIL Side Brazed ~65/ +125 1 Data sheet EF6850EM TMS standard LCCC -55/ +125 1 Data sheet EF68A50JM TMS standard DIL Cerdip 55/ +125 15 Data sheet . EF68A50CM* TMS standard DIL Side Brazed 55/ +125 1.5 Data sheet EF68A50EM TMS standard LCCC 55/ +125 1.5 Data sheet EF6850C* TMS standard DIL Side Brazed O/ +70 1 Data sheet EF6850J TMS standard DIL Cerdip 0! +70 1 Data sheet EF68A50C* TMS standard DIL Side Brazed 0/ +70 15 Data sheet EF68B50J TMS standard DIL Cerdip 0/ +70 2 Data sheet * Non considered anymore as standard package, Cerdip is preferred. Note: THOMSON COMPOSANTS MILITAIRES ET SPATIAUX. 17/20 4. THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 EF6850 C M B/C Type Packages: Screening: C = Ceramic DIL (side brazed) ___ = Standard C1 = Gold lead, tin lead. G/B = NFC 96883 CI.G E = Ceramic LCC - | BC = MIL STD 883 Ci.B E1 = LCC+HOT Solder DIP B/T = according to MIL STD 883 = Tin dipped Cerdip DIL class B Temperature /Tcase: M = -55C/ +125C wo V = -40C/ +85C _ = Of +70C . 1) THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 19/20 4. THOMSON COMPOSANTS MILITAIRES ET SPATIAUXEF 6850 f.\ THOMSON COMPONENTS AND TUBE es Divan S CORPORATION 40G Commerce Way, Post Office Box 540, Totowa, New J ; ' , erey 07511-054 PHONE: (973) 812-9000 FAX: (973) 812-4191 Information furnished is believed to be accurate and reliable. However THOMSON COMPOSANTS MILITAIRES ET SPATIAUX assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of THOMSON COMPOSANTS MILITAIRES ET SPATIAUX. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. THOMSON COMPOSANTS MILITAIRES ET SPATIAUX products are not authorized for use as critical components in life support devices or systems without express written approval from THOMSON COMPOSANTS MILITAIRES ET SPATIAUX. 1992 THOMSON COMPOSANTS MILITAIRES ET SPATIAUX - Printed in France - All rights reserved. This product is man oa Fh ERANAAR ARAL AAMDACARITS MIE ITAIRES ET CDATIAUX - 38521 SAINT-EGREVE 4 THO For turther informatio THC MSON COMPONENTS AND TUBES CORPORATION timpaud- 92402 COURBEVOIE ( 34.17.57. 40G Commerce Way, Post Office Box 540, Totowa New Jere , , y 07511-0540 PHONE: (973) 812-9000 FAX: (973) 812-4191 20/20 1. THOMSON COMPOSANTS MILITAIKES EI SFAIIAUA ' ORDER CODE : DSEF6850T/0792 Imprme en France par Graphic Exaress . Tel (1) 4655.27.24 - 8007 - 07792